From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 2/3] x86: add missing CheckRegSize
Date: Wed, 23 Nov 2022 11:34:34 +0100 [thread overview]
Message-ID: <3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com> (raw)
In-Reply-To: <dd561fd8-329c-eabb-2ef2-4c1844cacb77@suse.com>
To properly and predictably determine operand size encoding (operand
size or REX.W prefixes), consistent operand sizes need to be specified.
Add CheckRegSize where this was previously missing.
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -928,11 +928,11 @@ ud2, 0xf0b, None, Cpu186, NoSuf, {}
// alias for ud2
ud2a, 0xf0b, None, Cpu186, NoSuf, {}
// 2nd. official undefined instr.
-ud1, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ud1, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// alias for ud1
-ud2b, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ud2b, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// 3rd official undefined instr (older CPUs don't take a ModR/M byte)
-ud0, 0xfff, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ud0, 0xfff, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
cmov<cc>, 0xf4<cc:opc>, None, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
next prev parent reply other threads:[~2022-11-23 10:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 10:32 [PATCH 0/3] x86: correct checking of matching operand sizes Jan Beulich
2022-11-23 10:33 ` [PATCH 1/3] x86: correct handling of LAR and LSL Jan Beulich
2022-11-23 10:34 ` Jan Beulich [this message]
2022-11-23 10:35 ` [PATCH 3/3] x86: widen applicability and use of CheckRegSize Jan Beulich
2022-11-29 23:57 ` H.J. Lu
2022-11-23 21:39 ` [PATCH 0/3] x86: correct checking of matching operand sizes H.J. Lu
2022-11-24 8:38 ` Jan Beulich
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