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From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 0/3] x86: correct checking of matching operand sizes
Date: Wed, 23 Nov 2022 13:39:34 -0800	[thread overview]
Message-ID: <CAMe9rOr17M9Tp_pfBSMnqcc2C1oHV6cihyG8MLWJXJQDVKDyiQ@mail.gmail.com> (raw)
In-Reply-To: <dd561fd8-329c-eabb-2ef2-4c1844cacb77@suse.com>

On Wed, Nov 23, 2022 at 2:32 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> I've spotted a few cases where operand sizes matching wasn't really
> checked, leading to malformed insn/operand combinations to be
> accepted (in the first patch another anomaly is also taken care of).
> This mainly, but not only affects Intel Syntax.
>
> 1: correct handling of LAR and LSL
> 2: add missing CheckRegSize
> 3: widen applicability and use of CheckRegSize
>
> Jan

OK to all.

Thanks.

-- 
H.J.

  parent reply	other threads:[~2022-11-23 21:40 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-23 10:32 Jan Beulich
2022-11-23 10:33 ` [PATCH 1/3] x86: correct handling of LAR and LSL Jan Beulich
2022-11-23 10:34 ` [PATCH 2/3] x86: add missing CheckRegSize Jan Beulich
2022-11-23 10:35 ` [PATCH 3/3] x86: widen applicability and use of CheckRegSize Jan Beulich
2022-11-29 23:57   ` H.J. Lu
2022-11-23 21:39 ` H.J. Lu [this message]
2022-11-24  8:38   ` [PATCH 0/3] x86: correct checking of matching operand sizes Jan Beulich

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