From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>
Cc: binutils@sourceware.org
Subject: [PATCH 1/1] RISC-V: Check shift amount against XLEN (disasm)
Date: Sat, 30 Jul 2022 12:51:12 +0900 [thread overview]
Message-ID: <41005df437c5a738c13970c629bdea4181091a51.1659153057.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1659153057.git.research_trasio@irq.a4lg.com>
Although the assembler does the equivalent, the disassembler did not
have shift amount checking. Instead of actually rejecting invalid shift
amount, this commit prints invalid shift amount as "invalid0x[SHAMT]".
It also changes the style so that style-aware disassembler can distinguish
regular shift amount (immediate) and invalid one.
gas/ChangeLog:
* testsuite/gas/riscv/shamt-dis.s: New disassembler test.
* testsuite/gas/riscv/shamt-dis-32.d: Likewise.
* testsuite/gas/riscv/shamt-dis-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Print invalid shift amount as
"invalid0x[SHAMT]" where SHAMT is represented in hexadecimal.
---
gas/testsuite/gas/riscv/shamt-dis-32.d | 34 +++++++++++++++++++
gas/testsuite/gas/riscv/shamt-dis-64.d | 34 +++++++++++++++++++
gas/testsuite/gas/riscv/shamt-dis.s | 47 ++++++++++++++++++++++++++
opcodes/riscv-dis.c | 16 ++++++---
4 files changed, 127 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/shamt-dis-32.d
create mode 100644 gas/testsuite/gas/riscv/shamt-dis-64.d
create mode 100644 gas/testsuite/gas/riscv/shamt-dis.s
diff --git a/gas/testsuite/gas/riscv/shamt-dis-32.d b/gas/testsuite/gas/riscv/shamt-dis-32.d
new file mode 100644
index 00000000000..85a247f7e25
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-dis-32.d
@@ -0,0 +1,34 @@
+#as: -march=rv32ic_zba_zbb_zbs
+#source: shamt-dis.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+01f59513[ ]+slli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+02059513[ ]+slli[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+01f5d513[ ]+srli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+0205d513[ ]+srli[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+41f5d513[ ]+srai[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4205d513[ ]+srai[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+057e[ ]+c\.slli[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,invalid0x20
+[ ]+[0-9a-f]+:[ ]+817d[ ]+c\.srli[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,invalid0x20
+[ ]+[0-9a-f]+:[ ]+857d[ ]+c\.srai[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+9501[ ]+c\.srai[ ]+a0,invalid0x20
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6205d513[ ]+rori[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+09f5951b[ ]+\.4byte[ ]+0x9f5951b
+[ ]+[0-9a-f]+:[ ]+0a05951b[ ]+\.4byte[ ]+0xa05951b
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4a059513[ ]+bclri[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+2a059513[ ]+bseti[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6a059513[ ]+binvi[ ]+a0,a1,invalid0x20
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4a05d513[ ]+bexti[ ]+a0,a1,invalid0x20
diff --git a/gas/testsuite/gas/riscv/shamt-dis-64.d b/gas/testsuite/gas/riscv/shamt-dis-64.d
new file mode 100644
index 00000000000..d10e90d9d30
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-dis-64.d
@@ -0,0 +1,34 @@
+#as: -march=rv64ic_zba_zbb_zbs
+#source: shamt-dis.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+01f59513[ ]+slli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+02059513[ ]+slli[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+01f5d513[ ]+srli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+0205d513[ ]+srli[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+41f5d513[ ]+srai[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4205d513[ ]+srai[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+057e[ ]+c\.slli[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+817d[ ]+c\.srli[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+857d[ ]+c\.srai[ ]+a0,0x1f
+[ ]+[0-9a-f]+:[ ]+9501[ ]+c\.srai[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6205d513[ ]+rori[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+09f5951b[ ]+slli\.uw[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+0a05951b[ ]+slli\.uw[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4a059513[ ]+bclri[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+2a059513[ ]+bseti[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6a059513[ ]+binvi[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4a05d513[ ]+bexti[ ]+a0,a1,0x20
diff --git a/gas/testsuite/gas/riscv/shamt-dis.s b/gas/testsuite/gas/riscv/shamt-dis.s
new file mode 100644
index 00000000000..a6e292242d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-dis.s
@@ -0,0 +1,47 @@
+target:
+ # slli a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 1, a0, a1, 0x000 | 31
+ .insn i OP_IMM, 1, a0, a1, 0x000 | 32
+ # srli a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 5, a0, a1, 0x000 | 31
+ .insn i OP_IMM, 5, a0, a1, 0x000 | 32
+ # srai a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 5, a0, a1, 0x400 | 31
+ .insn i OP_IMM, 5, a0, a1, 0x400 | 32
+
+ # RVC
+ # c.slli a0,SHAMT [31/32]
+ .insn ci 2, 0, a0, 31
+ .insn ci 2, 0, a0, 32 - 0x40
+ # Although c.sr[la]i are CB-format instructions,
+ # encode them as CI-type for immediate consistency.
+ # c.srli a0,SHAMT [31/32]
+ .insn ci 1, 4, x2, 31
+ .insn ci 1, 4, x2, 32 - 0x40
+ # c.srai a0,SHAMT [31/32]
+ .insn ci 1, 4, x10, 31
+ .insn ci 1, 4, x10, 32 - 0x40
+
+ # Zbb extension (or Zbkb)
+ # rori a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 5, a0, a1, 0x600 | 31
+ .insn i OP_IMM, 5, a0, a1, 0x600 | 32
+
+ # Zba extension
+ # slli.uw a0,a1,SHAMT [31/32] (invalid on RV32)
+ .insn i OP_IMM_32, 1, a0, a1, 0x080 | 31
+ .insn i OP_IMM_32, 1, a0, a1, 0x080 | 32
+
+ # Zbs extension
+ # bclri a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 1, a0, a1, 0x480 | 31
+ .insn i OP_IMM, 1, a0, a1, 0x480 | 32
+ # bseti a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 1, a0, a1, 0x280 | 31
+ .insn i OP_IMM, 1, a0, a1, 0x280 | 32
+ # binvi a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 1, a0, a1, 0x680 | 31
+ .insn i OP_IMM, 1, a0, a1, 0x680 | 32
+ # bexti a0,a1,SHAMT [31/32]
+ .insn i OP_IMM, 5, a0, a1, 0x480 | 31
+ .insn i OP_IMM, 5, a0, a1, 0x480 | 32
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 164fd209dbd..3e9519525d4 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -286,8 +286,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
(int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
break;
case '>':
- print (info->stream, dis_style_immediate, "0x%x",
- (int)EXTRACT_CITYPE_IMM (l) & 0x3f);
+ if (((unsigned)EXTRACT_CITYPE_IMM (l) & 0x3fU) >= xlen)
+ print (info->stream, dis_style_text, "invalid0x%x",
+ (unsigned)EXTRACT_CITYPE_IMM (l) & 0x3fU);
+ else
+ print (info->stream, dis_style_immediate, "0x%x",
+ (unsigned)EXTRACT_CITYPE_IMM (l) & 0x3fU);
break;
case '<':
print (info->stream, dis_style_immediate, "0x%x",
@@ -481,8 +485,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
case '>':
- print (info->stream, dis_style_immediate, "0x%x",
- (int)EXTRACT_OPERAND (SHAMT, l));
+ if ((unsigned)EXTRACT_OPERAND (SHAMT, l) >= xlen)
+ print (info->stream, dis_style_text, "invalid0x%x",
+ (unsigned)EXTRACT_OPERAND (SHAMT, l));
+ else
+ print (info->stream, dis_style_immediate, "0x%x",
+ (unsigned)EXTRACT_OPERAND (SHAMT, l));
break;
case '<':
--
2.34.1
prev parent reply other threads:[~2022-07-30 3:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 10:06 [RFC PATCH 0/3] RISC-V: Check shift amount against XLEN (disassembler) Tsukasa OI
2022-05-23 10:06 ` [RFC PATCH 1/3] RISC-V: Add xlen to match_func Tsukasa OI
2022-05-23 10:06 ` [RFC PATCH 2/3] RISC-V: Check shift amount against XLEN Tsukasa OI
2022-05-23 10:06 ` [RFC PATCH 3/3] RISC-V: Add disassembler tests for shift amount Tsukasa OI
2022-07-30 3:47 ` [RFC PATCH 0/3] RISC-V: Check shift amount against XLEN (disassembler) Tsukasa OI
2022-07-30 3:51 ` [PATCH 0/1] " Tsukasa OI
2022-07-30 3:51 ` Tsukasa OI [this message]
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