[PATCH 0/1] RISC-V: Check shift amount against XLEN (disassembler)

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

This patchset is going to support shift amount checking on the disassembler.

Previous Patchset:
<https://sourceware.org/pipermail/binutils/2022-May/120956.html>
<https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_shift_xlen>
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_shift_xlen_2>


In the disassembler, there's no validation whether shift amount is valid on the
specific architecture (RV32/64).

My previous Idea 1 patchset tried to fix that by adding xlen argument to every
match_func (in opcode entries).  However, it requires bigger core disassembler
changes and maintaining is relatively hard.

Idea 2 patchset (this patchset) fixes that by printing invalid0x[SHAMT] instead
of actual shift width (SHAMT in hexadecimal like regular shift amounts).  If we
don't have to print "unrecognized instruction" (such as .4byte) on instrucitons
with invalid shift amounts, this patch would be the simplest solution for the
invalid shift amount checking support on the disassembler.


This patchset supports styling. invalid shift amounts are printed as text, not
immediate.  It makes invalid shift amounts default white opposed to blue on
valid ones.
See an example with the GitHub Wiki page linked above.


Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Check shift amount against XLEN (disasm)

 gas/testsuite/gas/riscv/shamt-dis-32.d | 34 +++++++++++++++++++
 gas/testsuite/gas/riscv/shamt-dis-64.d | 34 +++++++++++++++++++
 gas/testsuite/gas/riscv/shamt-dis.s    | 47 ++++++++++++++++++++++++++
 opcodes/riscv-dis.c                    | 16 ++++++---
 4 files changed, 127 insertions(+), 4 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/shamt-dis-32.d
 create mode 100644 gas/testsuite/gas/riscv/shamt-dis-64.d
 create mode 100644 gas/testsuite/gas/riscv/shamt-dis.s


base-commit: b245c595aaa59812f8f3a0e8b70ea5f52e045627
-- 
2.34.1