From: Andrew Carlotti <andrew.carlotti@arm.com>
To: binutils@sourceware.org
Cc: Richard Earnshaw <richard.earnshaw@arm.com>
Subject: [PATCH 04/11] aarch64: Add +jscvt flag for existing fjcvtzs instruction
Date: Fri, 12 Jan 2024 01:42:36 +0000 [thread overview]
Message-ID: <412363bf-2b36-82cf-ee7b-4fbd72d28120@e124511.cambridge.arm.com> (raw)
In-Reply-To: <1496882f-bd18-37f7-761c-e33e5fca6a4b@e124511.cambridge.arm.com>
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c2f77a40ef225efc6998855885ae0d0757a86479..b77b160fe1f95409afaed399e6aaf8888476d912 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10284,6 +10284,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURES (2, F16, SIMD)},
{"compnum", AARCH64_FEATURE (COMPNUM),
AARCH64_FEATURES (2, F16, SIMD)},
+ {"jscvt", AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)},
{"rcpc", AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
{"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
{"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.d b/gas/testsuite/gas/aarch64/fp-armv8_3.d
index dd37a1180f29e38242e85052a13722e08d0ea861..a502c582b12e4c0866bda39b94ded34dd11b6701 100644
--- a/gas/testsuite/gas/aarch64/fp-armv8_3.d
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.d
@@ -1,5 +1,6 @@
#objdump: -dr
#as: -march=armv8.3-a
+#as: -march=armv8-a+jscvt
.*: file .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 95fe50249871ecff0dbffc920a041b39eedb1516..eb42b87a00263cfa633e4bd6c35fd912941a15a8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -99,6 +99,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_RCPC,
/* Complex # instructions. */
AARCH64_FEATURE_COMPNUM,
+ /* JavaScript conversion instructions. */
+ AARCH64_FEATURE_JSCVT,
/* Dot Product instructions. */
AARCH64_FEATURE_DOTPROD,
/* SM3 & SM4 instructions. */
@@ -246,7 +248,8 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V8_3A_FEATURES(X) (AARCH64_FEATBIT (X, V8_3A) \
| AARCH64_FEATBIT (X, PAC) \
| AARCH64_FEATBIT (X, RCPC) \
- | AARCH64_FEATBIT (X, COMPNUM))
+ | AARCH64_FEATBIT (X, COMPNUM) \
+ | AARCH64_FEATBIT (X, JSCVT))
#define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \
| AARCH64_FEATBIT (X, DOTPROD) \
| AARCH64_FEATBIT (X, FLAGM) \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2ddeca99d0bff80869216368f5f0f47cea5ae99f..007bf018af89c4bc74e59bc70e8560caacb3eac7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2518,6 +2518,8 @@ static const aarch64_feature_set aarch64_feature_pac =
AARCH64_FEATURE (PAC);
static const aarch64_feature_set aarch64_feature_compnum =
AARCH64_FEATURE (COMPNUM);
+static const aarch64_feature_set aarch64_feature_jscvt =
+ AARCH64_FEATURE (JSCVT);
static const aarch64_feature_set aarch64_feature_rcpc =
AARCH64_FEATURE (RCPC);
static const aarch64_feature_set aarch64_feature_dotprod =
@@ -2631,6 +2633,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define FP_V8_3A &aarch64_feature_fp_v8_3a
#define PAC &aarch64_feature_pac
#define COMPNUM &aarch64_feature_compnum
+#define JSCVT &aarch64_feature_jscvt
#define RCPC &aarch64_feature_rcpc
#define SHA2 &aarch64_feature_sha2
#define AES &aarch64_feature_aes
@@ -2717,6 +2720,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
{ NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -3741,7 +3746,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
__FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
__FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
- {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3A, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL },
+ JSCVT_INSN ("fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_W_D, 0),
/* Floating-point conditional compare. */
__FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),
next prev parent reply other threads:[~2024-01-12 1:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 1:39 [PATCH 00/11] aarch64: New feature flags and flag fixes Andrew Carlotti
2024-01-12 1:40 ` [PATCH 01/11] aarch64: Fix +lse feature flag dependency Andrew Carlotti
2024-01-12 1:41 ` [PATCH 02/11] aarch64: Add +fcma alias for +compnum Andrew Carlotti
2024-01-12 1:42 ` [PATCH 03/11] aarch64: Fix option parsing to disallow prefixes of valid options Andrew Carlotti
2024-01-12 1:42 ` Andrew Carlotti [this message]
2024-01-12 1:43 ` [PATCH 05/11] aarch64: Add +frintts flag for existing instructions Andrew Carlotti
2024-01-12 1:43 ` [PATCH 06/11] aarch64: Add +flagm2 " Andrew Carlotti
2024-01-12 1:44 ` [PATCH 07/11] aarch64: Add +rcpc2 " Andrew Carlotti
2024-01-12 1:44 ` [PATCH 08/11] aarch64: Add +wfxt " Andrew Carlotti
2024-01-12 1:45 ` [PATCH 09/11] aarch64: Add +xs " Andrew Carlotti
2024-01-12 1:45 ` [PATCH 10/11] aarch64: Make FEAT_ASMv8p2 instruction aliases always available Andrew Carlotti
2024-01-12 1:46 ` [PATCH 11/11] aarch64: Remove unused code Andrew Carlotti
2024-01-12 13:47 ` [PATCH 00/11] aarch64: New feature flags and flag fixes Nick Clifton
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