From: Andrew Carlotti <andrew.carlotti@arm.com>
To: binutils@sourceware.org
Cc: Richard Earnshaw <richard.earnshaw@arm.com>
Subject: [PATCH 10/11] aarch64: Make FEAT_ASMv8p2 instruction aliases always available
Date: Fri, 12 Jan 2024 01:45:57 +0000 [thread overview]
Message-ID: <fbe2b3db-35fc-b276-8273-f8022d9561a0@e124511.cambridge.arm.com> (raw)
In-Reply-To: <1496882f-bd18-37f7-761c-e33e5fca6a4b@e124511.cambridge.arm.com>
There's no reason to disallow the aliases when the aliased instructions are
always available. The new behaviour matches existing LLVM behaviour.
diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d
index 45ddcf5905a677ab807c9e8f7d93dd8b10bd77a1..610382b91d1a096027ef115451d7985b2ed40e61 100644
--- a/gas/testsuite/gas/aarch64/alias-2.d
+++ b/gas/testsuite/gas/aarch64/alias-2.d
@@ -1,5 +1,5 @@
#objdump: -dr
-#as: -march=armv8.2-a
+#as: -march=armv8-a
.*: file format .*
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 95f7757e8ebaa5ca1958be212283aa17cacdcc5b..3df273c74f3af26195039a8ed23c4e6c3784b404 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3572,7 +3572,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
- V8_2A_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
+ CORE_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
@@ -3645,7 +3645,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0),
CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1),
- V8_2A_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
+ CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0),
next prev parent reply other threads:[~2024-01-12 1:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 1:39 [PATCH 00/11] aarch64: New feature flags and flag fixes Andrew Carlotti
2024-01-12 1:40 ` [PATCH 01/11] aarch64: Fix +lse feature flag dependency Andrew Carlotti
2024-01-12 1:41 ` [PATCH 02/11] aarch64: Add +fcma alias for +compnum Andrew Carlotti
2024-01-12 1:42 ` [PATCH 03/11] aarch64: Fix option parsing to disallow prefixes of valid options Andrew Carlotti
2024-01-12 1:42 ` [PATCH 04/11] aarch64: Add +jscvt flag for existing fjcvtzs instruction Andrew Carlotti
2024-01-12 1:43 ` [PATCH 05/11] aarch64: Add +frintts flag for existing instructions Andrew Carlotti
2024-01-12 1:43 ` [PATCH 06/11] aarch64: Add +flagm2 " Andrew Carlotti
2024-01-12 1:44 ` [PATCH 07/11] aarch64: Add +rcpc2 " Andrew Carlotti
2024-01-12 1:44 ` [PATCH 08/11] aarch64: Add +wfxt " Andrew Carlotti
2024-01-12 1:45 ` [PATCH 09/11] aarch64: Add +xs " Andrew Carlotti
2024-01-12 1:45 ` Andrew Carlotti [this message]
2024-01-12 1:46 ` [PATCH 11/11] aarch64: Remove unused code Andrew Carlotti
2024-01-12 13:47 ` [PATCH 00/11] aarch64: New feature flags and flag fixes Nick Clifton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fbe2b3db-35fc-b276-8273-f8022d9561a0@e124511.cambridge.arm.com \
--to=andrew.carlotti@arm.com \
--cc=binutils@sourceware.org \
--cc=richard.earnshaw@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).