Re: [PATCH v5 1/1] opcodes: microblaze: Add new bit-field instructions

[Michael Eager <eager@eagercon.com>]

On 10/10/23 00:59, Neal Frager wrote:
> This patches adds new bsefi and bsifi instructions.
> BSEFI- The instruction shall extract a bit field from a
> register and place it right-adjusted in the destination register.
> The other bits in the destination register shall be set to zero.
> BSIFI- The instruction shall insert a right-adjusted bit field
> from a register at another position in the destination register.
> The rest of the bits in the destination register shall be unchanged.
> 
> Further documentation of these instructions can be found here:
> https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
> 
> This patch has been tested for years of AMD Xilinx Yocto
> releases as part of the following patch set:
> 
> https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils
> 
> Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
> V1->V2:
>   -corrected relocation values for the linker
> V2->V3:
>   - fixed build issue for 32-bit hosts
>   - added test cases for bsefi and bsifi instructions
> V3->V4:
>   - fixed GNU coding standard issues
> V4->V5:
>   - fixed a remaining line of code > 80 chars


Please do NOT send me incremental changes to this (or any other) patch.
They clutter up my inbox and I will not review or apply incomplete patches.

Please provide a FINAL patch which addresses all of the issues 
previously noted.

Include the summary of the binutils test suite runs (gas, ld, binutils) 
or a diff of the .sum file, before and after applying the patch, showing 
no regressions.

-- 
Michael Eager