From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: hjl.tools@gmail.com, binutils@sourceware.org
Subject: Re: [PATCH V4] Support APX NF
Date: Thu, 28 Mar 2024 12:24:39 +0100 [thread overview]
Message-ID: <47e11c46-ae50-4a68-9b09-6f5d5d1d9fe0@suse.com> (raw)
In-Reply-To: <20240326064939.1458879-1-lili.cui@intel.com>
On 26.03.2024 07:49, Cui, Lili wrote:
> --- a/gas/testsuite/gas/i386/x86-64-apx-inval.s
> +++ b/gas/testsuite/gas/i386/x86-64-apx-inval.s
> @@ -2,3 +2,12 @@
> .text
> addq $0xe0, %fs:0, %rdx
> xorq $0xe0, foo(%eax,%edx), %rdx
> + {nf} adc $1, (%rax)
> + {nf} not %r15
> + {nf} rcl $0x7b,%r15
> + {nf} rcr $0x7b,%r15
> + {nf} sbb $0x7b,%r15
> + {nf} pop2 %rax, %rbx
> + {nf} push2 %rbx, %rax
I think it would be nice if one of ADCX/ADOX and at least one of the BMI2
insns not permitting NF would also be covered here.
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
> @@ -0,0 +1,1383 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86_64 APX_F insns (Intel disassembly)
Here, ...
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.d
> @@ -0,0 +1,1383 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 APX_F insns
... here, and ...
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
> @@ -0,0 +1,1378 @@
> +# Check 64bit APX_F instructions
... in this comment NF wants mentioning.
> +
> + .text
> +_start:
> + {nf} add $123, %bl
> + {nf} add $123, %bl, %dl
> + {nf} add $123, %dx
> + {nf} add $123, %dx, %ax
> + {nf} add $123, %ecx
> + {nf} add $123, %ecx, %edx
> + {nf} add $123, %r9
> + {nf} add $123, %r9, %r31
> + {nf} addb $123, 291(%r8, %rax, 4)
> + {nf} add $123, 291(%r8, %rax, 4), %bl
> + {nf} addw $123, 291(%r8, %rax, 4)
> + {nf} add $123, 291(%r8, %rax, 4), %dx
> + {nf} addl $123, 291(%r8, %rax, 4)
> + {nf} add $123, 291(%r8, %rax, 4), %ecx
> + {nf} addq $123, 291(%r8, %rax, 4)
> + {nf} add $123, 291(%r8, %rax, 4), %r9
> + {nf} add %bl, %dl
> + {nf} add %bl, %dl, %r8b
> + {nf} add %bl, 291(%r8, %rax, 4)
> + {nf} add %bl, 291(%r8, %rax, 4), %dl
> + {nf} add %dx, %ax
> + {nf} add %dx, %ax, %r9w
> + {nf} add %dx, 291(%r8, %rax, 4)
> + {nf} add %dx, 291(%r8, %rax, 4), %ax
> + {nf} add %ecx, %edx
> + {nf} add %ecx, %edx, %r10d
> + {nf} add %ecx, 291(%r8, %rax, 4)
> + {nf} add %ecx, 291(%r8, %rax, 4), %edx
> + {nf} add %r9, %r31
> + {nf} add %r9, %r31, %r11
> + {nf} add %r9, 291(%r8, %rax, 4)
> + {nf} add %r9, 291(%r8, %rax, 4), %r31
> + {nf} add 291(%r8, %rax, 4), %bl
> + {nf} add 291(%r8, %rax, 4), %bl, %dl
> + {nf} add 291(%r8, %rax, 4), %dx
> + {nf} add 291(%r8, %rax, 4), %dx, %ax
> + {nf} add 291(%r8, %rax, 4), %ecx
> + {nf} add 291(%r8, %rax, 4), %ecx, %edx
> + {nf} add 291(%r8, %rax, 4), %r9
> + {nf} add 291(%r8, %rax, 4), %r9, %r31
> + {nf} and $123, %bl
> + {nf} and $123, %bl, %dl
> + {nf} and $123, %dx
> + {nf} and $123, %dx, %ax
> + {nf} and $123, %ecx
> + {nf} and $123, %ecx, %edx
> + {nf} and $123, %r9
> + {nf} and $123, %r9, %r31
> + {nf} andb $123, 291(%r8, %rax, 4)
> + {nf} and $123, 291(%r8, %rax, 4), %bl
> + {nf} andw $123, 291(%r8, %rax, 4)
> + {nf} and $123, 291(%r8, %rax, 4), %dx
> + {nf} andl $123, 291(%r8, %rax, 4)
> + {nf} and $123, 291(%r8, %rax, 4), %ecx
> + {nf} andq $123, 291(%r8, %rax, 4)
> + {nf} and $123, 291(%r8, %rax, 4), %r9
> + {nf} and %bl, %dl
> + {nf} and %bl, %dl, %r8b
> + {nf} and %bl, 291(%r8, %rax, 4)
> + {nf} and %bl, 291(%r8, %rax, 4), %dl
> + {nf} and %dx, %ax
> + {nf} and %dx, %ax, %r9w
> + {nf} and %dx, 291(%r8, %rax, 4)
> + {nf} and %dx, 291(%r8, %rax, 4), %ax
> + {nf} and %ecx, %edx
> + {nf} and %ecx, %edx, %r10d
> + {nf} and %ecx, 291(%r8, %rax, 4)
> + {nf} and %ecx, 291(%r8, %rax, 4), %edx
> + {nf} and %r9, %r31
> + {nf} and %r9, %r31, %r11
> + {nf} and %r9, 291(%r8, %rax, 4)
> + {nf} and %r9, 291(%r8, %rax, 4), %r31
> + {nf} and 291(%r8, %rax, 4), %bl
> + {nf} and 291(%r8, %rax, 4), %bl, %dl
> + {nf} and 291(%r8, %rax, 4), %dx
> + {nf} and 291(%r8, %rax, 4), %dx, %ax
> + {nf} and 291(%r8, %rax, 4), %ecx
> + {nf} and 291(%r8, %rax, 4), %ecx, %edx
> + {nf} and 291(%r8, %rax, 4), %r9
> + {nf} and 291(%r8, %rax, 4), %r9, %r31
> + {nf} andn %ecx, %edx, %r10d
> + {nf} andn %r9, %r31, %r11
> + {nf} andn 291(%r8, %rax, 4), %ecx, %edx
> + {nf} andn 291(%r8, %rax, 4), %r9, %r31
> + {nf} bextr %ecx, %edx, %r10d
> + {nf} bextr %ecx, 291(%r8, %rax, 4), %edx
> + {nf} bextr %r9, %r31, %r11
> + {nf} bextr %r9, 291(%r8, %rax, 4), %r31
> + {nf} blsi %ecx, %edx
> + {nf} blsi %r9, %r31
> + {nf} blsi 291(%r8, %rax, 4), %ecx
> + {nf} blsi 291(%r8, %rax, 4), %r9
> + {nf} blsmsk %ecx, %edx
> + {nf} blsmsk %r9, %r31
> + {nf} blsmsk 291(%r8, %rax, 4), %ecx
> + {nf} blsmsk 291(%r8, %rax, 4), %r9
> + {nf} blsr %ecx, %edx
> + {nf} blsr %r9, %r31
> + {nf} blsr 291(%r8, %rax, 4), %ecx
> + {nf} blsr 291(%r8, %rax, 4), %r9
> + {nf} bzhi %ecx, %edx, %r10d
> + {nf} bzhi %ecx, 291(%r8, %rax, 4), %edx
> + {nf} bzhi %r9, %r31, %r11
> + {nf} bzhi %r9, 291(%r8, %rax, 4), %r31
> + {nf} dec %bl
No CLR test here? Oh, I see it's at the bottom. I wants moving here.
Jan
next prev parent reply other threads:[~2024-03-28 11:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-26 6:49 Cui, Lili
2024-03-28 11:24 ` Jan Beulich [this message]
2024-04-01 6:20 ` Cui, Lili
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