From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH] RISC-V: make .insn actually work for 64-bit insns
Date: Fri, 25 Feb 2022 12:06:06 +0100 [thread overview]
Message-ID: <6d807b33-5409-b728-7d1e-9fef8a16490b@suse.com> (raw)
Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:
Error: value conflicts with instruction length `8,0x0000003f'
Eliminate the UB and extend the respective testcase.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3248,7 +3248,7 @@ riscv_ip_hardcode (char *str,
insn->match = values[num - 1];
create_insn (ip, insn);
unsigned int bytes = riscv_insn_length (insn->match);
- if (values[num - 1] >> (8 * bytes) != 0
+ if ((bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0)
|| (num == 2 && values[0] != bytes))
return _("value conflicts with instruction length");
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -71,5 +71,9 @@ Disassembly of section .text:
[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
[^:]+:[ ]+0001[ ]+nop
[^:]+:[ ]+00000013[ ]+nop
+[^:]+:[ ]+001f 0000 0000[ ].*
+[^:]+:[ ]+0000003f 00000000[ ].*
[^:]+:[ ]+0001[ ]+nop
[^:]+:[ ]+00000013[ ]+nop
+[^:]+:[ ]+001f 0000 0000[ ].*
+[^:]+:[ ]+0000003f 00000000[ ].*
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -56,5 +56,9 @@ target:
.insn 0x0001
.insn 0x00000013
+ .insn 0x0000001f
+ .insn 0x0000003f
.insn 0x2, 0x0001
.insn 0x4, 0x00000013
+ .insn 6, 0x0000001f
+ .insn 8, 0x0000003f
next reply other threads:[~2022-02-25 11:06 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-25 11:06 Jan Beulich [this message]
2022-02-25 13:38 ` Nelson Chu
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