* [GAS][AArch64] Define TRBE system registers
@ 2020-09-24 15:09 Przemyslaw Wirkus
2020-09-28 14:39 ` Nick Clifton
0 siblings, 1 reply; 2+ messages in thread
From: Przemyslaw Wirkus @ 2020-09-24 15:09 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc, Ramana Radhakrishnan, Marcus Shawcroft
[-- Attachment #1: Type: text/plain, Size: 1634 bytes --]
Hi,
This patch introduces TRBE (Trace Buffer Extension) system registers.
If TRBE is implemented, the TRBE registers are:
- TRBIDR_EL1 a Trace Buffer ID Register read-only register.
- TRBBASER_EL1 a Trace Buffer Base Address Register.
- TRBLIMITR_EL1 a Trace Buffer Limit Address Register.
- TRBMAR_EL1 a Trace Buffer Memory Attribute Register.
- TRBPTR_EL1 a Trace Buffer Write Pointer Register.
- TRBSR_EL1 a Trace Buffer Status/syndrome Register.
- TRBTRG_EL1 a Trace Buffer Trigger Counter Register.
Above system registers are documented here:
https://developer.arm.com/docs/ddi0601/f
Note: as this is register only extension, we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
aarch64-none-linux-gnu binutils regression tests OK.
OK for master branch?
PS: I do not have write permission, can this be commited in my name if
approved please?
Kind regards,
Przemyslaw Wirkus
gas/ChangeLog:
2020-09-17 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/trbe-invalid.d: New test.
* testsuite/gas/aarch64/trbe-invalid.l: New test.
* testsuite/gas/aarch64/trbe-invalid.s: New test.
* testsuite/gas/aarch64/trbe.d: New test.
* testsuite/gas/aarch64/trbe.s: New test.
opcodes/ChangeLog:
2020-09-17 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
[-- Attachment #2: rb13474.patch --]
[-- Type: application/octet-stream, Size: 3357 bytes --]
diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.d b/gas/testsuite/gas/aarch64/trbe-invalid.d
new file mode 100644
index 0000000000000000000000000000000000000000..a14c15edf028ec16149e3d7c79b9062b602178f9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/trbe-invalid.d
@@ -0,0 +1,3 @@
+#name: Invalid TRBE System registers usage
+#source: trbe-invalid.s
+#warning_output: trbe-invalid.l
diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.l b/gas/testsuite/gas/aarch64/trbe-invalid.l
new file mode 100644
index 0000000000000000000000000000000000000000..c4865c5d9e179a45447b044f52c681b52a9eb46f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/trbe-invalid.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trbidr_el1,x0'
diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.s b/gas/testsuite/gas/aarch64/trbe-invalid.s
new file mode 100644
index 0000000000000000000000000000000000000000..a37b58517519c4baf12f695dc05ed0fba8f724a4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/trbe-invalid.s
@@ -0,0 +1,2 @@
+/* Write to R/O system register. */
+msr trbidr_el1, x0
diff --git a/gas/testsuite/gas/aarch64/trbe.d b/gas/testsuite/gas/aarch64/trbe.d
new file mode 100644
index 0000000000000000000000000000000000000000..04b83fb06393e0f8dc860ecb32a9ed15ec0807cf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/trbe.d
@@ -0,0 +1,21 @@
+#name: TRBE System registers
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d5389b40 mrs x0, trbbaser_el1
+.*: d5389be0 mrs x0, trbidr_el1
+.*: d5389b00 mrs x0, trblimitr_el1
+.*: d5389b80 mrs x0, trbmar_el1
+.*: d5389b20 mrs x0, trbptr_el1
+.*: d5389b60 mrs x0, trbsr_el1
+.*: d5389bc0 mrs x0, trbtrg_el1
+.*: d5189b40 msr trbbaser_el1, x0
+.*: d5189b00 msr trblimitr_el1, x0
+.*: d5189b80 msr trbmar_el1, x0
+.*: d5189b20 msr trbptr_el1, x0
+.*: d5189b60 msr trbsr_el1, x0
+.*: d5189bc0 msr trbtrg_el1, x0
diff --git a/gas/testsuite/gas/aarch64/trbe.s b/gas/testsuite/gas/aarch64/trbe.s
new file mode 100644
index 0000000000000000000000000000000000000000..bf48ed16a31466df22caacbeabf08d92a63f79af
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/trbe.s
@@ -0,0 +1,16 @@
+/* Read from system register. */
+mrs x0, trbbaser_el1
+mrs x0, trbidr_el1
+mrs x0, trblimitr_el1
+mrs x0, trbmar_el1
+mrs x0, trbptr_el1
+mrs x0, trbsr_el1
+mrs x0, trbtrg_el1
+
+/* Write to system register. */
+msr trbbaser_el1, x0
+msr trblimitr_el1, x0
+msr trbmar_el1, x0
+msr trbptr_el1, x0
+msr trbsr_el1, x0
+msr trbtrg_el1, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 22d69347946c4a7b37d07e632d9e57025ec26d23..1be8d21642be6cce1ecebb01e6147ea63fe209b8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4311,6 +4311,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_V8_R ("prselr_el2", CPENC (3,4,C6,C2,1), 0),
SR_V8_R ("vsctlr_el2", CPENC (3,4,C2,C0,0), 0),
+ SR_CORE("trbbaser_el1", CPENC (3,0,C9,C11,2), 0),
+ SR_CORE("trbidr_el1", CPENC (3,0,C9,C11,7), F_REG_READ),
+ SR_CORE("trblimitr_el1", CPENC (3,0,C9,C11,0), 0),
+ SR_CORE("trbmar_el1", CPENC (3,0,C9,C11,4), 0),
+ SR_CORE("trbptr_el1", CPENC (3,0,C9,C11,1), 0),
+ SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0),
+ SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0),
+
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [GAS][AArch64] Define TRBE system registers
2020-09-24 15:09 [GAS][AArch64] Define TRBE system registers Przemyslaw Wirkus
@ 2020-09-28 14:39 ` Nick Clifton
0 siblings, 0 replies; 2+ messages in thread
From: Nick Clifton @ 2020-09-28 14:39 UTC (permalink / raw)
To: Przemyslaw Wirkus, binutils
Cc: Richard Earnshaw, Ramana Radhakrishnan, Marcus Shawcroft
Hi Przemyslaw,
> OK for master branch?
Approved and applied.
Cheers
Nick
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-09-28 14:39 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-24 15:09 [GAS][AArch64] Define TRBE system registers Przemyslaw Wirkus
2020-09-28 14:39 ` Nick Clifton
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).