From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH v4 0/4] RISC-V: Combined floating point enhancements
Date: Sat, 30 Jul 2022 12:21:54 +0900 [thread overview]
Message-ID: <83a4a879-c9be-5b25-256e-eed97441688f@irq.a4lg.com> (raw)
In-Reply-To: <cover.1658689128.git.research_trasio@irq.a4lg.com>
Additional Report - Support on LLVM:
Functional differences between my patchset and the latest LLVM is
whether requirements to "fmv.[sdq]" instructions are relaxed. As I
noted earlier, supporting "fmv.[sdq]" on Zfinx environment seems more
natural.
Register pairs of RV32_Zdinx (note that LLVM does not support Zqinx) are
supported on LLVM >= 14. See GPRPF64 for register pairs on LLVM.
In fact, all zdinx-32-regpair-fail.s testcases generated errors (total:
110) and zdinx-32-regpair.s only generated one compiler error ("fmv.d"
is not supported on LLVM but this is not related to register pairs).
Recap - Existing Reviews:
Although that the patchset itself changes multiple times, its
functionality is mostly reviewed. It's nearly 6 months ago so it's not
a bad timing to remind you all.
Relaxing fmv.[sdq] requirements (PATCH 2/4):
- <https://sourceware.org/pipermail/binutils/2022-February/119677.html>
Reviewed by Palmer Dabbelt
Zfinx register pairs (PATCH 3/4):
- <https://sourceware.org/pipermail/binutils/2022-February/119679.html>
This is when I had two ideas to fix this issue but the version I
implemented in combined patchset v4 seems fine to Palmer.
Note that there's no "Reviewed-by" tag, though.
I hope they are useful to review my changes.
On 2022/07/25 3:58, Tsukasa OI wrote:
> Before combining patchsets:
> <https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2)
> <https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2)
> Combined v1:
> <https://sourceware.org/pipermail/binutils/2022-June/121138.html>
> Combined v2:
> <https://sourceware.org/pipermail/binutils/2022-June/121441.html>
> Combined v3:
> <https://sourceware.org/pipermail/binutils/2022-July/121720.html>
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined>
>
> This is a rebased and fixed version for Zfinx-related issues.
>
> First, let me recap the changes.
>
>
>
>
> 1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/4)
>
> I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
> patch. I also...
>
> - Made indentation / coding style consistent and clean
> - Started to use valid register number on Zqinx
> (as I explain below [PATCH 3-4/4])
> - Started to use different register per operand
>
>
> 2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/4)
>
> On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
> On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair.
>
> That means, single...
> fmv.d x10, x12
> is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs):
> mv x10, x12
> mv x11, x13
>
> Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx
> extensions, it's safe to implement this pseudo-instructions.
>
> This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
>
>
> 3. Validate Register pairs on Zdinx/Zqinx (PATCH 3-4/4)
>
> On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even
> (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would
> be that all registers holding a FP128 value will be required to have a multiple
> of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
>
> On RV32_Zdinx, this is valid.
> fadd.d x10, x12, x14
> On the other hand, this is not valid (on RV32_Zdinx).
> fadd.d x11, x13, x15
>
> Current Binutils can generate invalid instructions with odd register numbers
> (or register number x % 4 != 0). PATCH 3/4 makes those invalid.
>
> Testcases (PATCH 4/4) are separate only because it is quite large.
>
>
>
>
> [Changes: v3 -> v4]
>
> - Rebased
> - Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore)
> Clearly, I forgot to test the patchset.
> This time, I confirmed that it passes the test.
>
>
> [Changes: v2 -> v3]
>
> - Rebased
> - Postponed non-functional (coding style-related) changes
> for another patchset
> - Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests
> - Fixed `fcvt.q.l{,u}' instruction match values
>
>
>
>
> Tsukasa OI (4):
> RISC-V: Reorganize and enhance Zfinx tests
> RISC-V: Relax `fmv.[sdq]' requirements
> RISC-V: Validate Zdinx/Zqinx register pairs
> RISC-V: Add testcases for Z[dq]inx register pairs
>
> bfd/elfxx-riscv.c | 8 +
> gas/config/tc-riscv.c | 21 +-
> .../gas/riscv/zdinx-32-regpair-dis.d | 11 +
> .../gas/riscv/zdinx-32-regpair-dis.s | 5 +
> .../gas/riscv/zdinx-32-regpair-fail.d | 3 +
> .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++
> .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++
> gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++
> gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
> gas/testsuite/gas/riscv/zdinx.d | 27 +-
> gas/testsuite/gas/riscv/zdinx.s | 46 +-
> gas/testsuite/gas/riscv/zfinx.d | 24 +-
> gas/testsuite/gas/riscv/zfinx.s | 42 +-
> .../gas/riscv/zqinx-32-regpair-dis.d | 12 +
> .../gas/riscv/zqinx-32-regpair-dis.s | 7 +
> .../gas/riscv/zqinx-32-regpair-fail.d | 3 +
> .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++
> .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++
> gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++
> gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++
> .../gas/riscv/zqinx-64-regpair-dis.d | 11 +
> .../gas/riscv/zqinx-64-regpair-dis.s | 5 +
> .../gas/riscv/zqinx-64-regpair-fail.d | 3 +
> .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++
> .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++
> gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
> gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
> gas/testsuite/gas/riscv/zqinx.d | 84 +--
> gas/testsuite/gas/riscv/zqinx.s | 87 +--
> include/opcode/riscv.h | 10 +-
> opcodes/riscv-opc.c | 541 ++++++++++++++----
> 31 files changed, 2097 insertions(+), 209 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
>
>
> base-commit: ea892bdc4b6da5782c6ea6273aff499fb5fd5e6f
next prev parent reply other threads:[~2022-07-30 3:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 14:05 [PATCH 0/9] " Tsukasa OI
2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI
2022-06-02 14:40 ` Palmer Dabbelt
2022-06-05 3:57 ` Tsukasa OI
2022-06-02 14:05 ` [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-02 14:06 ` [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-02 14:06 ` [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-06-02 14:06 ` [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-06-02 14:06 ` [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-02 14:06 ` [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-02 14:06 ` [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-02 14:06 ` [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-30 3:21 ` Tsukasa OI [this message]
2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI
2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-09-04 7:06 ` [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements Tsukasa OI
2022-09-04 7:06 ` [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
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