From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements
Date: Sun, 4 Sep 2022 07:06:14 +0000 [thread overview]
Message-ID: <cover.1662275167.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1658689128.git.research_trasio@irq.a4lg.com>
Hello,
Combined v4:
<https://sourceware.org/pipermail/binutils/2022-July/121981.html>
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined>
This is a rebased and fixed version for Zfinx-related issues.
****************************************************************************
I consider this the most important Binutils patchset submitted by me
since the current GAS allows emitting invalid instructions.
This is almost RESEND but with commit messages and commit squashing.
****************************************************************************
Let me recap the changes (again).
1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/3)
I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
patch. I also...
- Made indentation / coding style consistent and clean
- Started to use valid register number on Zqinx
(as I explain below [PATCH 3/3])
- Started to use different register per operand
2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/3)
On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair.
That means, single...
fmv.d x10, x12
is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs):
mv x10, x12
mv x11, x13
Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx
extensions, it's safe to implement this pseudo-instructions.
This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
****************************************************************************
Note that this is consistent with Zhinx changes since fmv.h already requires
('Zfh' or 'Zhinx'), not 'Zfh' only.
****************************************************************************
3. Validate Register pairs on Zdinx/Zqinx (PATCH 3/3)
On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be
even (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx,
it would be that all registers holding a FP128 value will be required to
have a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
On RV32_Zdinx, this is valid.
fadd.d x10, x12, x14
On the other hand, this is not valid (on RV32_Zdinx).
fadd.d x11, x13, x15
Current Binutils can generate invalid instructions with odd register numbers
(or register number x % 4 != 0). PATCH 3/3 makes those invalid.
****************************************************************************
This patch fixes the problem which allows emitting invalid instructions.
****************************************************************************
[Changes: v4 -> v5]
- Rebased
- Squashed (PATCH 3-4/4 to PATCH 3/3)
- Commit messages are refined
[Changes: v3 -> v4]
- Rebased
- Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore)
Clearly, I forgot to test the patchset.
This time, I confirmed that it passes the test.
[Changes: v2 -> v3]
- Rebased
- Postponed non-functional (coding style-related) changes
for another patchset
- Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests
- Fixed `fcvt.q.l{,u}' instruction match values
Tsukasa OI (3):
RISC-V: Reorganize and enhance Zfinx tests
RISC-V: Relax fmv.[sdq] requirements
RISC-V: Validate Zdinx/Zqinx register pairs
bfd/elfxx-riscv.c | 8 +
gas/config/tc-riscv.c | 21 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 27 +-
gas/testsuite/gas/riscv/zdinx.s | 46 +-
gas/testsuite/gas/riscv/zfinx.d | 24 +-
gas/testsuite/gas/riscv/zfinx.s | 42 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 84 +--
gas/testsuite/gas/riscv/zqinx.s | 87 +--
include/opcode/riscv.h | 10 +-
opcodes/riscv-opc.c | 541 ++++++++++++++----
31 files changed, 2097 insertions(+), 209 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: 148b68a56c57d69bd97a5f40c34fc4700693596a
--
2.34.1
next prev parent reply other threads:[~2022-09-04 7:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI
2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI
2022-06-02 14:40 ` Palmer Dabbelt
2022-06-05 3:57 ` Tsukasa OI
2022-06-02 14:05 ` [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-02 14:06 ` [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-02 14:06 ` [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-06-02 14:06 ` [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-06-02 14:06 ` [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-02 14:06 ` [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-02 14:06 ` [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-02 14:06 ` [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-07-10 6:36 ` [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-07-24 18:58 ` [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-07-30 3:21 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI
2022-09-04 7:06 ` Tsukasa OI [this message]
2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-09-04 7:06 ` [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements Tsukasa OI
2022-09-04 7:06 ` [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
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