From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/3] RISC-V: Cache instruction support
Date: Sun, 20 Nov 2022 01:08:42 +0000 [thread overview]
Message-ID: <844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668906514.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Calling riscv_subset_supports repeatedly harms the performance in a
measurable way (about 3-13% in total on the most cases).
As a simple solution, this commit now caches instruction class support
(whether specific instruction class is supported) as a signed char array.
It is expected to have 5-7% performance improvements when disassembling
linked RISC-V ELF programs using objdump but this is particularly effective
with programs with many CSR instructions (up to ~42% on the author's PC).
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Add NUM_INSN_CLASSES.
opcodes/ChangeLog:
* riscv-dis.c (riscv_insn_support_cache) New.
(init_riscv_dis_state_for_arch): Clear the instruction support
cache. (riscv_disassemble_insn): Cache the instruction support.
---
include/opcode/riscv.h | 2 ++
opcodes/riscv-dis.c | 15 ++++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..6a029a1034e1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -422,6 +422,8 @@ enum riscv_insn_class
INSN_CLASS_XTHEADMEMIDX,
INSN_CLASS_XTHEADMEMPAIR,
INSN_CLASS_XTHEADSYNC,
+
+ NUM_INSN_CLASSES,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 197f6a31d439..32e7b1174436 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -107,6 +107,9 @@ static bool no_aliases = false;
/* If set, disassemble with numeric register names. */
static bool is_numeric = false;
+
+/* Instruction support cache. */
+static signed char riscv_insn_support_cache[NUM_INSN_CLASSES];
\f
/* Set current disassembler context (dis_arch_context_current).
@@ -200,6 +203,9 @@ static void
init_riscv_dis_state_for_arch (void)
{
is_arch_changed = true;
+ /* Clear instruction support cache. */
+ for (size_t i = 0; i < NUM_INSN_CLASSES; i++)
+ riscv_insn_support_cache[i] = 0;
}
/* Initialization (for arch and options). */
@@ -955,7 +961,14 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
continue;
/* Is this instruction supported by the current architecture? */
- if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
+ if (riscv_insn_support_cache[op->insn_class] == 0)
+ {
+ riscv_insn_support_cache[op->insn_class]
+ = riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)
+ ? +1
+ : -1;
+ }
+ if (riscv_insn_support_cache[op->insn_class] < 0)
continue;
matched_op = op;
--
2.38.1
next prev parent reply other threads:[~2022-11-20 1:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-20 1:08 [PATCH 0/3] RISC-V: Disassembler Core Optimization 1-1 (Hash table and Caching) Tsukasa OI
2022-11-20 1:08 ` [PATCH 1/3] RISC-V: Use faster hash table on disassembling Tsukasa OI
2022-11-20 1:08 ` [PATCH 2/3] RISC-V: Fallback on faster hash table Tsukasa OI
2022-11-20 1:08 ` Tsukasa OI [this message]
2022-11-28 4:46 ` [PATCH v2 0/3] RISC-V: Disassembler Core Optimization 1-1 (Hash table and Caching) Tsukasa OI
2022-11-28 4:46 ` [PATCH v2 1/3] RISC-V: Use faster hash table on disassembling Tsukasa OI
2022-11-28 4:46 ` [PATCH v2 2/3] RISC-V: Fallback on faster hash table Tsukasa OI
2022-11-28 4:46 ` [PATCH v2 3/3] RISC-V: Cache instruction support Tsukasa OI
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