Re: [PATCH 1/2] opcodes/mips: use .word/.short for undefined instructions

[Andrew Burgess <aburgess@redhat.com>]

"Maciej W. Rozycki" <macro@orcam.me.uk> writes:

> Hi Andrew,
>
>  In the course of reviewing outstanding upstream mailing list traffic I 
> came across this change of yours.
>
> On Thu, 3 Nov 2022, Andrew Burgess via Binutils wrote:
>
>> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
>> index faeebccfc3b..1d9875f2bb0 100644
>> --- a/opcodes/mips-dis.c
>> +++ b/opcodes/mips-dis.c
>> @@ -2515,7 +2515,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
>>  	}
>>      }
>>  
>> -  infprintf (is, "0x%x", insn);
>> +  if (length == 2)
>> +    infprintf (is, ".short\t0x%x", insn);
>> +  else
>> +    infprintf (is, ".word\t0x%x", insn);
>
>  FYI, I find this questionable as `.word' (at least with the MIPS target) 
> implies natural alignment while 32-bit microMIPS encodings, valid or not, 
> are not.  Also, given the endianness peculiarity (analogous to the MIPS16 
> extended encodings), I think this needs to be ".short\t0x%x, 0x%x" really, 
> with the instruction word split into halfwords for any reasonable meaning.  
> This is already reflected in the raw hex dump of instruction streams; the 
> numbers printed need to match it.
>
>  With the naked number previously used this obviously didn't matter as it 
> stood out without any attempt to pretend to have a meaning.  This is also 
> the reason why I chose to keep it as it used to be since forever.

Hi,

Below is an initial patch.  When I set the environment variable
DISABLE_MATCHING then the disassembler fails to match all instructions,
so prints .short for everything.

Right now I can't find anything where this doesn't work, but I don't
believe that the answer is actually this simple.  Given your deeper
knowledge of the target, could you take a look at what I have below and
point me at some tests/configurations/whatever where this isn't going to
be good enough?

Alternatively, if this is enough, then I'll write this up into a proper
patch.

Thanks,
Andrew

---

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 6a513cd8946..5c6ec9a1147 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -2554,6 +2554,9 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
   opend = micromips_opcodes + bfd_micromips_num_opcodes;
   for (op = micromips_opcodes; op < opend; op++)
     {
+      if (getenv ("DISABLE_MATCHING") != NULL)
+	break;
+
       if (op->pinfo != INSN_MACRO
 	  && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
 	  && (insn & op->mask) == op->match
@@ -2601,11 +2604,19 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
     }
 
   if (length == 2)
-    infprintf (is, dis_style_assembler_directive, ".short");
+    {
+      infprintf (is, dis_style_assembler_directive, ".short");
+      infprintf (is, dis_style_text, "\t");
+      infprintf (is, dis_style_immediate, "0x%x", insn);
+    }
   else
-    infprintf (is, dis_style_assembler_directive, ".word");
-  infprintf (is, dis_style_text, "\t");
-  infprintf (is, dis_style_immediate, "0x%x", insn);
+    {
+      infprintf (is, dis_style_assembler_directive, ".short");
+      infprintf (is, dis_style_text, "\t");
+      infprintf (is, dis_style_immediate, "0x%x", (insn >> 16) & 0xffff);
+      infprintf (is, dis_style_text, ", ");
+      infprintf (is, dis_style_immediate, "0x%x", (insn & 0xffff));
+    }
   info->insn_type = dis_noninsn;
 
   return length;