[PATCH 0/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

[PATCH 0/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

[Tsukasa OI]

Hi,

In September 2022, I raised this issue (along with a patch set):
<https://sourceware.org/pipermail/binutils/2022-September/122757.html>
<https://sourceware.org/pipermail/binutils/2022-September/122761.html>
that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.

At that time, we couldn't conclude that unprivileged extensions with CSRs
imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
withdrawn.

I recently raised issues at the repository of related specifications and at
the vector specification, it's concluded that 'Zve32x' (minimum vector
subset) implies 'Zicsr':
<https://github.com/riscv/riscv-v-spec/issues/908>
<https://github.com/riscv/riscv-v-spec/issues/909>

Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Imply 'Zicsr' from 'Zve32x'

 bfd/elfxx-riscv.c | 1 +
 1 file changed, 1 insertion(+)


base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
-- 
2.41.0

[PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Further clarification is made so that 'Zve32x' implies 'Zicsr' (the same
implication is already implemented in LLVM).

See related issue (the author raised) on the vector specification:
<https://github.com/riscv/riscv-v-spec/issues/908>
and its resolution:
<https://github.com/riscv/riscv-v-spec/issues/909>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zve32x' -> 'Zicsr'.
---
 bfd/elfxx-riscv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ba5165766b2b..2ce95d90df52 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1121,6 +1121,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zve64x", "zve32x",	check_implicit_always},
   {"zve64x", "zvl64b",	check_implicit_always},
   {"zve32x", "zvl32b",	check_implicit_always},
+  {"zve32x", "zicsr",	check_implicit_always},
   {"zvl65536b", "zvl32768b",	check_implicit_always},
   {"zvl32768b", "zvl16384b",	check_implicit_always},
   {"zvl16384b", "zvl8192b",	check_implicit_always},
-- 
2.41.0

Re: [PATCH 0/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

[Nelson Chu]

[-- Attachment #1: Type: text/plain, Size: 1293 bytes --]

On Thu, Aug 3, 2023 at 8:04 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> Hi,
>
> In September 2022, I raised this issue (along with a patch set):
> <https://sourceware.org/pipermail/binutils/2022-September/122757.html>
> <https://sourceware.org/pipermail/binutils/2022-September/122761.html>
> that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.
>
> At that time, we couldn't conclude that unprivileged extensions with CSRs
> imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
> withdrawn.
>
> I recently raised issues at the repository of related specifications and at
> the vector specification, it's concluded that 'Zve32x' (minimum vector
> subset) implies 'Zicsr':
> <https://github.com/riscv/riscv-v-spec/issues/908>
> <https://github.com/riscv/riscv-v-spec/issues/909>
>
> Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
> should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.
>

Okay, sounds reasonable.

Thanks
Nelson


> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (1):
>   RISC-V: Imply 'Zicsr' from 'Zve32x'
>
>  bfd/elfxx-riscv.c | 1 +
>  1 file changed, 1 insertion(+)
>
>
> base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
> --
> 2.41.0
>
>

Re: [PATCH 0/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

[Tsukasa OI]

On 2023/08/03 9:39, Nelson Chu wrote:
> 
> 
> On Thu, Aug 3, 2023 at 8:04 AM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
> 
>     Hi,
> 
>     In September 2022, I raised this issue (along with a patch set):
>     <https://sourceware.org/pipermail/binutils/2022-September/122757.html <https://sourceware.org/pipermail/binutils/2022-September/122757.html>>
>     <https://sourceware.org/pipermail/binutils/2022-September/122761.html <https://sourceware.org/pipermail/binutils/2022-September/122761.html>>
>     that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.
> 
>     At that time, we couldn't conclude that unprivileged extensions with
>     CSRs
>     imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
>     withdrawn.
> 
>     I recently raised issues at the repository of related specifications
>     and at
>     the vector specification, it's concluded that 'Zve32x' (minimum vector
>     subset) implies 'Zicsr':
>     <https://github.com/riscv/riscv-v-spec/issues/908
>     <https://github.com/riscv/riscv-v-spec/issues/908>>
>     <https://github.com/riscv/riscv-v-spec/issues/909
>     <https://github.com/riscv/riscv-v-spec/issues/909>>
> 
>     Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
>     should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.
> 
> 
> Okay, sounds reasonable.
> 
> Thanks
> Nelson

Committed!

Thanks,
Tsukasa

>  
> 
>     Thanks,
>     Tsukasa
> 
> 
> 
> 
>     Tsukasa OI (1):
>       RISC-V: Imply 'Zicsr' from 'Zve32x'
> 
>      bfd/elfxx-riscv.c | 1 +
>      1 file changed, 1 insertion(+)
> 
> 
>     base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
>     -- 
>     2.41.0
>