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From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: "Lu, Hongjiu" <hongjiu.lu@intel.com>,
	"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH] Support APX NF
Date: Fri, 1 Mar 2024 07:56:06 +0100	[thread overview]
Message-ID: <932bfc4c-daa3-473a-8260-9327914dd49b@suse.com> (raw)
In-Reply-To: <PH0PR11MB5593AF45F5DD158C5211ED9F9E5E2@PH0PR11MB5593.namprd11.prod.outlook.com>

On 01.03.2024 04:23, Cui, Lili wrote:
> 
> 
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Thursday, February 29, 2024 10:12 PM
>> To: Cui, Lili <lili.cui@intel.com>
>> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org
>> Subject: Re: [PATCH] Support APX NF
>>
>> On 29.02.2024 14:47, Cui, Lili wrote:
>>>>>> -----Original Message-----
>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>> Sent: Thursday, February 29, 2024 8:04 PM
>>>>>> To: Cui, Lili <lili.cui@intel.com>
>>>>>> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org
>>>>>> Subject: Re: [PATCH] Support APX NF
>>>>>>
>>>>>> On 29.02.2024 13:00, Cui, Lili wrote:
>>>>>>>> On 27.02.2024 10:01, Cui, Lili wrote:
>>>>>>>>> @@ -8860,6 +8880,9 @@ match_template (char mnem_suffix)
>>>>>>>>>  		  goto check_operands_345;
>>>>>>>>>  		}
>>>>>>>>>  	      else if (t->opcode_space != SPACE_BASE
>>>>>>>>> +		       /* Map0 and map1 are promoted to MAP4 when
>> NF is
>>>>>>>> enabled.
>>>>>>>>> +			*/
>>>>>>>>> +		       && !t->opcode_modifier.nf
>>>>>>>>>  		       && (t->opcode_space != SPACE_0F
>>>>>>>>>  			   /* MOV to/from CR/DR/TR, as an exception,
>> follow
>>>>>>>>>  			      the base opcode space encoding model.  */
>>>>>>>>
>>>>>>>> I don't understand this: How does a template permitting NF matter
>> here?
>>>>>>>> I could see the immediately preceding "else if" become something
>>>>>>>> along the lines of
>>>>>>>>
>>>>>>>> 	      else if (is_cpu (t, CpuAPX_F) && (i.operands == 3 ||
>>>>>>>> i.has_nf))
>>>>>>>>
>>>>>>>> But I admit I didn't fully think this through. It's just that the
>>>>>>>> change as is looks wrong to me.
>>>>>>>>
>>>>>>>
>>>>>>> I was also dissatisfied with this place yesterday and then modified it to:
>>>>>>>
>>>>>>>               else if (t->opcode_space != SPACE_BASE
>>>>>>>                        /* For EVEX-promoted instructions, opcode_space is
>>>>>>>                           promoted to MAP4.  */
>>>>>>>                        && (t->opcode_space != SPACE_EVEXMAP4
>>>>>>>                            || t->mnem_off == MN_movbe)
>>>>>>>                        && (t->opcode_space != SPACE_0F
>>>>>>>                            /* MOV to/from CR/DR/TR, as an exception, follow
>>>>>>>                               the base opcode space encoding model.  */
>>>>>>>                            || (t->base_opcode | 7) != 0x27))
>>>>>>>
>>>>>>> For EVEX-promoted instructions, opcode_space is promoted to MAP4.
>>>>>>> The
>>>>>> old judgment no longer fit for EVEX promoted instructions. However,
>>>>>> the logic of this place is still not good.
>>>>>>
>>>>>> So what about my suggestion?
>>>>>
>>>>> Your suggestion is better, but we need to replace i.has_nf with new
>>>> judgment, i.has_nf cannot cover instructions like adc, the testcase
>>>> will be added by another patch.
>>>>>
>>>>> +             else if (is_cpu (t, CpuAPX_F)
>>>>> +                      && (i.operands == 3 || (t->opcode_space ==
>> SPACE_EVEXMAP4
>>>>> +                                              && t->mnem_off !=
>>>>> + MN_movbe)))
>>>>
>>>> Ah yes, to cover the non-NF 2-operand forms. But then is the
>>>> "i.operands == 3"
>>>> part actually still needed?
>>>
>>> It can be removed,  great suggestion, thanks!
>>
>> Thinking of it - the is_cpu() then likely is unnecessary as well. If new
>> map4 insn appeared that have D set in the template, they would likely follow
>> the same pattern, yet be keyed to a different CPU feature. What's less clear is
>> whether instead of special-casing MOVBE it would make sense to check the
>> template's W bit here. Thoughts?
> 
> Yes, now all MAP4 instructions belong to APX, "is_cpu(t,CpuAPX_F)" is indeed redundant, 
> 
> For " else if (t->opcode_space == SPACE_EVEXMAP4 && t->opcode_modifier.w)"
> 
> Among all instructions of map2 and map3, only crc32 supports W, and it does not have "D". It can work. But when new instructions appear, these rules may be broken. I have no idea about this place. Maybe MOVBE is more intuitive? W's judgment is a high-level summary, perhaps more difficult to understand?

Only future will tell, unless internally you know of more concrete plans.
I consider using W here less adhoc compared to special-casing MOVBE.

Jan

  reply	other threads:[~2024-03-01  6:56 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-27  9:01 Cui, Lili
2024-02-28 16:11 ` H.J. Lu
2024-02-29  1:12   ` Cui, Lili
2024-02-29  6:53   ` Jan Beulich
2024-02-29  8:39     ` Cui, Lili
2024-02-29  9:06       ` Jan Beulich
2024-02-29 10:22         ` Cui, Lili
2024-02-29 12:23           ` H.J. Lu
2024-02-29 12:26             ` Cui, Lili
2024-02-29 11:21 ` Jan Beulich
2024-02-29 12:00   ` Cui, Lili
2024-02-29 12:04     ` Jan Beulich
2024-02-29 12:41       ` Cui, Lili
2024-02-29 13:17         ` Jan Beulich
2024-02-29 13:47           ` Cui, Lili
2024-02-29 14:12             ` Jan Beulich
2024-03-01  3:23               ` Cui, Lili
2024-03-01  6:56                 ` Jan Beulich [this message]
2024-03-01  8:01                   ` Cui, Lili
2024-03-01 11:36   ` Cui, Lili
2024-03-01 11:49     ` Jan Beulich
2024-03-01  7:04 ` Jan Beulich
2024-03-01 11:50   ` Cui, Lili
2024-03-19  6:41 Cui, Lili
2024-03-21 14:26 ` Jan Beulich

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