[GAS][AArch64] Define ETE system registers

[Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>]

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Hi,

This patch introduces ETE (Embedded Trace Extension) system registers.
If ETE is implemented, the ETE registers are:
- TRCEXTINSELR<0-3> an External Input Select Register <n>.
- TRCRSR            a Resources Status Register.

Above system registers are documented here:
https://developer.arm.com/docs/ddi0601/f

Note: as this is register only extension, we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).

aarch64-none-linux-gnu binutils regression tests OK.

OK for master branch?

PS: I do not have write permission, can this be commited in my name if
approved please?

Kind regards,
Przemyslaw Wirkus

gas/ChangeLog:

2020-09-17  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

              * testsuite/gas/aarch64/ete.d: New test.
              * testsuite/gas/aarch64/ete.s: New test.

opcodes/ChangeLog:

2020-09-17  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

              * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.


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diff --git a/gas/testsuite/gas/aarch64/ete.d b/gas/testsuite/gas/aarch64/ete.d
new file mode 100644
index 0000000000000000000000000000000000000000..511b4fb5343871aba144036505029891efa8d850
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ete.d
@@ -0,0 +1,18 @@
+#name: ETE System registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:	d5310880 	mrs	x0, trcextinselr0
+[^:]+:	d5310980 	mrs	x0, trcextinselr1
+[^:]+:	d5310a80 	mrs	x0, trcextinselr2
+[^:]+:	d5310b80 	mrs	x0, trcextinselr3
+[^:]+:	d5310a00 	mrs	x0, trcrsr
+[^:]+:	d5110880 	msr	trcextinselr0, x0
+[^:]+:	d5110980 	msr	trcextinselr1, x0
+[^:]+:	d5110a80 	msr	trcextinselr2, x0
+[^:]+:	d5110b80 	msr	trcextinselr3, x0
+[^:]+:	d5110a00 	msr	trcrsr, x0
diff --git a/gas/testsuite/gas/aarch64/ete.s b/gas/testsuite/gas/aarch64/ete.s
new file mode 100644
index 0000000000000000000000000000000000000000..72720eed9ee3d4e5a1c82e93def32d59cf2601b4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ete.s
@@ -0,0 +1,15 @@
+/* ETE System registers.  */
+
+/* Read from system register.  */
+mrs x0, trcextinselr0
+mrs x0, trcextinselr1
+mrs x0, trcextinselr2
+mrs x0, trcextinselr3
+mrs x0, trcrsr
+
+/* Write to system register.  */
+msr trcextinselr0, x0
+msr trcextinselr1, x0
+msr trcextinselr2, x0
+msr trcextinselr3, x0
+msr trcrsr, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1be8d21642be6cce1ecebb01e6147ea63fe209b8..83afb1f9778ab7cff8f2105c95999e83847f89d7 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4319,6 +4319,12 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE("trbsr_el1",  	CPENC (3,0,C9,C11,3),	0),
   SR_CORE("trbtrg_el1", 	CPENC (3,0,C9,C11,6),	0),
 
+  SR_CORE ("trcextinselr0",	CPENC (2,1,C0,C8,4),	0),
+  SR_CORE ("trcextinselr1",	CPENC (2,1,C0,C9,4),	0),
+  SR_CORE ("trcextinselr2",	CPENC (2,1,C0,C10,4),	0),
+  SR_CORE ("trcextinselr3",	CPENC (2,1,C0,C11,4),	0),
+  SR_CORE ("trcrsr",		CPENC (2,1,C0,C10,0),	0),
+
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };