From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Jan Beulich <jbeulich@suse.com>
Cc: Christoph Muellner <christoph.muellner@vrull.eu>,
binutils@sourceware.org, Nathan Huckleberry <nhuck@google.com>,
nhuck@pmull.org, Jeff Law <jeffreyalaw@gmail.com>,
Nelson Chu <nelson@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>
Subject: Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
Date: Mon, 17 Jul 2023 09:11:34 +0200 [thread overview]
Message-ID: <CAAeLtUDtqy-MAOihxrz76rC2827Ww6cyUdGB7GqjbMLdZYqjjA@mail.gmail.com> (raw)
In-Reply-To: <355e3b07-3111-34dc-7b0f-8be828012ae4@suse.com>
On Mon, 17 Jul 2023 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 01.07.2023 07:20, Christoph Muellner wrote:
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> > {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
> >
> > +/* Zvbc instructions. */
> > +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> > +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
>
> I realize this is more a spec question than an implementation one, but
> implementation might be affected by the answer to the question: What
> exactly are this and ...
>
> > +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> > +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
>
> ... this insn doing in RV32 mode? There are no 64 bits to take from
> the GPR, yet that's what the doc presently says. Is the value coming
> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> RV64-only insn? (Note how the doc explicitly describes the behavior
> for vandn's scalar-source form; the only thing left to be implied
> there is that truncation / sign-extension are to - I assume - element
> size, but maybe that's said somewhere in more general terms.
According to the pull-request for the SAIL model (which will in the
future be auto-generated into the specification documents and often
clarifies on parts of the specification where the English text is
ambiguous or imprecise), these are defined for RV64 only:
>
> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> + <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
Consequently, these should only be allowed for RV64.
Thanks for catching this!
Philipp.
>
> As a nit: The two vclmulh lines have one too many blanks, resulting
> in columns to not be aligned.
>
> Jan
next prev parent reply other threads:[~2023-07-17 7:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension Christoph Muellner
2023-07-17 7:02 ` Jan Beulich
2023-07-17 7:11 ` Philipp Tomsich [this message]
2023-07-17 7:26 ` Jan Beulich
2023-07-17 7:28 ` Philipp Tomsich
2023-07-17 7:20 ` Christoph Müllner
2023-07-24 21:12 ` [CAUTION - External Sender] " Ken Dockser
2023-07-01 5:20 ` [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension Christoph Muellner
2023-07-24 7:14 ` Jan Beulich
2023-07-01 5:20 ` [PATCH v6 04/15] RISC-V: Add support for the Zvkned " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions Christoph Muellner
2023-07-03 9:47 ` Nelson Chu
2023-07-03 10:10 ` Christoph Müllner
2023-07-01 5:20 ` [PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 07/15] RISC-V: Add support for the Zvksh " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 08/15] RISC-V: Add support for the Zvkn " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 09/15] RISC-V: Allow nested implications for extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 10/15] RISC-V: Add support for the Zvkng ISA extension Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 11/15] RISC-V: Add support for the Zvks " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 12/15] RISC-V: Add support for the Zvksg " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 13/15] RISC-V: Add support for the Zvknc " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 14/15] RISC-V: Add support for the Zvksc " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions Christoph Muellner
2023-07-01 13:38 ` [PATCH v6 00/15] RISC-V: Add support for " Palmer Dabbelt
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