* [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
@ 2023-11-17 6:20 Jin Ma
2023-12-13 7:00 ` Christoph Müllner
0 siblings, 1 reply; 4+ messages in thread
From: Jin Ma @ 2023-11-17 6:20 UTC (permalink / raw)
To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.
For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
* testsuite/gas/riscv/x-thead-fmv.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
(MASK_TH_FMV_HW_X): Likewise.
(MATCH_TH_FMV_X_HW): Likewise.
(MASK_TH_FMV_X_HW): Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Correct operands.
---
gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +-
include/opcode/riscv-opc.h | 8 ++++----
opcodes/riscv-opc.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
index af8ce0c8ee0..50ccc62413f 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.d
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
-[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
+[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0
+[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s
index 250ba8358ae..8ca2ec2f093 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.s
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
@@ -1,3 +1,3 @@
target:
- th.fmv.hw.x a0, fa1
+ th.fmv.hw.x fa1, a0
th.fmv.x.hw a1, fa0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..061e35d8603 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2515,10 +2515,10 @@
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-#define MATCH_TH_FMV_HW_X 0x5000100b
-#define MASK_TH_FMV_HW_X 0xfff0707f
-#define MATCH_TH_FMV_X_HW 0x6000100b
-#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_X_HW 0xc000100b
+#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_HW_X 0xa000100b
+#define MASK_TH_FMV_HW_X 0xfff0707f
/* Vendor-specific (T-Head) XTheadInt instructions. */
#define MATCH_TH_IPOP 0x0050000b
#define MASK_TH_IPOP 0xffffffff
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 72d727cd77e..3a4ab62d274 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
+{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadInt instructions. */
base-commit: 0da4f405f8d9d15b9381075debce788251e31815
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
2023-11-17 6:20 [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension Jin Ma
@ 2023-12-13 7:00 ` Christoph Müllner
2023-12-14 3:05 ` Nelson Chu
0 siblings, 1 reply; 4+ messages in thread
From: Christoph Müllner @ 2023-12-13 7:00 UTC (permalink / raw)
To: Jin Ma; +Cc: binutils, nelson, lifang_xia, jinma.contrib
On Fri, Nov 17, 2023 at 7:21 AM Jin Ma <jinma@linux.alibaba.com> wrote:
>
> The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
> XTheadFmv extension in T-Head specific is incorrect, and it also has
> some impact on the implementation of the binutils, so this patch
> corrects this.
This changes two things:
1) Fix swapped operand register types of th.fmv.hw.x
2) Revert of 767e2daed4da3245350d1e45e4eee42964d656f6
The swapped operands were likely caused by unclear description in the spec.
This got cleaned up in
https://github.com/T-head-Semi/thead-extension-spec/pull/34.
The encoding change back then was triggered by
https://github.com/T-head-Semi/thead-extension-spec/pull/11.
I assume that this spec change was a mistake (I don't have HW so I
cannot double-check).
To make sure we are consistent with other projects I checked the following:
* QEMU: we never updated QEMU to follow PR#11, therefore no change needed now
* GCC: we always emitted the operands in the correct order and correct
type, therefore no change needed now
* Specification: the mnemonics matches Binutils/GCC and the encoding
matches QEMU/Binutils
After reviewing all relevant pieces, this patch looks good to me.
I've also tested this patch on current master and all tests pass.
Reviewed-by: Christoph Muellner <christoph.muellner@vrull.eu>
Tested-by: Christoph Muellner <christoph.muellner@vrull.eu>
>
> For details see:
> https://github.com/T-head-Semi/thead-extension-spec/pull/34
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/x-thead-fmv.d: Correct test.
> * testsuite/gas/riscv/x-thead-fmv.s: Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
> (MASK_TH_FMV_HW_X): Likewise.
> (MATCH_TH_FMV_X_HW): Likewise.
> (MASK_TH_FMV_X_HW): Likewise.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c: Correct operands.
> ---
> gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +-
> include/opcode/riscv-opc.h | 8 ++++----
> opcodes/riscv-opc.c | 2 +-
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
> index af8ce0c8ee0..50ccc62413f 100644
> --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> @@ -7,5 +7,5 @@
> Disassembly of section .text:
>
> 0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> -[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> +[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0
> +[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s
> index 250ba8358ae..8ca2ec2f093 100644
> --- a/gas/testsuite/gas/riscv/x-thead-fmv.s
> +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
> @@ -1,3 +1,3 @@
> target:
> - th.fmv.hw.x a0, fa1
> + th.fmv.hw.x fa1, a0
> th.fmv.x.hw a1, fa0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 24217062edc..061e35d8603 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2515,10 +2515,10 @@
> #define MATCH_TH_FSURW 0x5000700b
> #define MASK_TH_FSURW 0xf800707f
> /* Vendor-specific (T-Head) XTheadFmv instructions. */
> -#define MATCH_TH_FMV_HW_X 0x5000100b
> -#define MASK_TH_FMV_HW_X 0xfff0707f
> -#define MATCH_TH_FMV_X_HW 0x6000100b
> -#define MASK_TH_FMV_X_HW 0xfff0707f
> +#define MATCH_TH_FMV_X_HW 0xc000100b
> +#define MASK_TH_FMV_X_HW 0xfff0707f
> +#define MATCH_TH_FMV_HW_X 0xa000100b
> +#define MASK_TH_FMV_HW_X 0xfff0707f
> /* Vendor-specific (T-Head) XTheadInt instructions. */
> #define MATCH_TH_IPOP 0x0050000b
> #define MASK_TH_IPOP 0xffffffff
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 72d727cd77e..3a4ab62d274 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
> {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
>
> /* Vendor-specific (T-Head) XTheadFmv instructions. */
> -{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
> +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
> {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
>
> /* Vendor-specific (T-Head) XTheadInt instructions. */
>
> base-commit: 0da4f405f8d9d15b9381075debce788251e31815
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
2023-12-13 7:00 ` Christoph Müllner
@ 2023-12-14 3:05 ` Nelson Chu
2023-12-14 8:57 ` Christoph Müllner
0 siblings, 1 reply; 4+ messages in thread
From: Nelson Chu @ 2023-12-14 3:05 UTC (permalink / raw)
To: Christoph Müllner; +Cc: Jin Ma, binutils, lifang_xia, jinma.contrib
[-- Attachment #1: Type: text/plain, Size: 5261 bytes --]
Thanks for testing the correctness, please commit.
Nelson
On Wed, Dec 13, 2023 at 3:00 PM Christoph Müllner <
christoph.muellner@vrull.eu> wrote:
> On Fri, Nov 17, 2023 at 7:21 AM Jin Ma <jinma@linux.alibaba.com> wrote:
> >
> > The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
> > XTheadFmv extension in T-Head specific is incorrect, and it also has
> > some impact on the implementation of the binutils, so this patch
> > corrects this.
>
> This changes two things:
> 1) Fix swapped operand register types of th.fmv.hw.x
> 2) Revert of 767e2daed4da3245350d1e45e4eee42964d656f6
>
> The swapped operands were likely caused by unclear description in the spec.
> This got cleaned up in
> https://github.com/T-head-Semi/thead-extension-spec/pull/34.
>
> The encoding change back then was triggered by
> https://github.com/T-head-Semi/thead-extension-spec/pull/11.
> I assume that this spec change was a mistake (I don't have HW so I
> cannot double-check).
>
> To make sure we are consistent with other projects I checked the following:
> * QEMU: we never updated QEMU to follow PR#11, therefore no change needed
> now
> * GCC: we always emitted the operands in the correct order and correct
> type, therefore no change needed now
> * Specification: the mnemonics matches Binutils/GCC and the encoding
> matches QEMU/Binutils
>
> After reviewing all relevant pieces, this patch looks good to me.
> I've also tested this patch on current master and all tests pass.
>
> Reviewed-by: Christoph Muellner <christoph.muellner@vrull.eu>
> Tested-by: Christoph Muellner <christoph.muellner@vrull.eu>
>
>
> >
> > For details see:
> > https://github.com/T-head-Semi/thead-extension-spec/pull/34
> >
> > gas/ChangeLog:
> >
> > * testsuite/gas/riscv/x-thead-fmv.d: Correct test.
> > * testsuite/gas/riscv/x-thead-fmv.s: Likewise.
> >
> > include/ChangeLog:
> >
> > * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
> > (MASK_TH_FMV_HW_X): Likewise.
> > (MATCH_TH_FMV_X_HW): Likewise.
> > (MASK_TH_FMV_X_HW): Likewise.
> >
> > opcodes/ChangeLog:
> >
> > * riscv-opc.c: Correct operands.
> > ---
> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
> > gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +-
> > include/opcode/riscv-opc.h | 8 ++++----
> > opcodes/riscv-opc.c | 2 +-
> > 4 files changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d
> b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > index af8ce0c8ee0..50ccc62413f 100644
> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
> > @@ -7,5 +7,5 @@
> > Disassembly of section .text:
> >
> > 0+000 <target>:
> > -[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
> > -[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > +[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0
> > +[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s
> b/gas/testsuite/gas/riscv/x-thead-fmv.s
> > index 250ba8358ae..8ca2ec2f093 100644
> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.s
> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
> > @@ -1,3 +1,3 @@
> > target:
> > - th.fmv.hw.x a0, fa1
> > + th.fmv.hw.x fa1, a0
> > th.fmv.x.hw a1, fa0
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 24217062edc..061e35d8603 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -2515,10 +2515,10 @@
> > #define MATCH_TH_FSURW 0x5000700b
> > #define MASK_TH_FSURW 0xf800707f
> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
> > -#define MATCH_TH_FMV_HW_X 0x5000100b
> > -#define MASK_TH_FMV_HW_X 0xfff0707f
> > -#define MATCH_TH_FMV_X_HW 0x6000100b
> > -#define MASK_TH_FMV_X_HW 0xfff0707f
> > +#define MATCH_TH_FMV_X_HW 0xc000100b
> > +#define MASK_TH_FMV_X_HW 0xfff0707f
> > +#define MATCH_TH_FMV_HW_X 0xa000100b
> > +#define MASK_TH_FMV_HW_X 0xfff0707f
> > /* Vendor-specific (T-Head) XTheadInt instructions. */
> > #define MATCH_TH_IPOP 0x0050000b
> > #define MASK_TH_IPOP 0xffffffff
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index 72d727cd77e..3a4ab62d274 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25",
> MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
> >
> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
> > -{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X,
> MASK_TH_FMV_HW_X, match_opcode, 0},
> > +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X,
> MASK_TH_FMV_HW_X, match_opcode, 0},
> > {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW,
> MASK_TH_FMV_X_HW, match_opcode, 0},
> >
> > /* Vendor-specific (T-Head) XTheadInt instructions. */
> >
> > base-commit: 0da4f405f8d9d15b9381075debce788251e31815
> > --
> > 2.17.1
> >
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
2023-12-14 3:05 ` Nelson Chu
@ 2023-12-14 8:57 ` Christoph Müllner
0 siblings, 0 replies; 4+ messages in thread
From: Christoph Müllner @ 2023-12-14 8:57 UTC (permalink / raw)
To: Nelson Chu; +Cc: Jin Ma, binutils, lifang_xia, jinma.contrib
On Thu, Dec 14, 2023 at 4:05 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
> Thanks for testing the correctness, please commit.
Committed.
Thanks!
>
> Nelson
>
> On Wed, Dec 13, 2023 at 3:00 PM Christoph Müllner <christoph.muellner@vrull.eu> wrote:
>>
>> On Fri, Nov 17, 2023 at 7:21 AM Jin Ma <jinma@linux.alibaba.com> wrote:
>> >
>> > The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
>> > XTheadFmv extension in T-Head specific is incorrect, and it also has
>> > some impact on the implementation of the binutils, so this patch
>> > corrects this.
>>
>> This changes two things:
>> 1) Fix swapped operand register types of th.fmv.hw.x
>> 2) Revert of 767e2daed4da3245350d1e45e4eee42964d656f6
>>
>> The swapped operands were likely caused by unclear description in the spec.
>> This got cleaned up in
>> https://github.com/T-head-Semi/thead-extension-spec/pull/34.
>>
>> The encoding change back then was triggered by
>> https://github.com/T-head-Semi/thead-extension-spec/pull/11.
>> I assume that this spec change was a mistake (I don't have HW so I
>> cannot double-check).
>>
>> To make sure we are consistent with other projects I checked the following:
>> * QEMU: we never updated QEMU to follow PR#11, therefore no change needed now
>> * GCC: we always emitted the operands in the correct order and correct
>> type, therefore no change needed now
>> * Specification: the mnemonics matches Binutils/GCC and the encoding
>> matches QEMU/Binutils
>>
>> After reviewing all relevant pieces, this patch looks good to me.
>> I've also tested this patch on current master and all tests pass.
>>
>> Reviewed-by: Christoph Muellner <christoph.muellner@vrull.eu>
>> Tested-by: Christoph Muellner <christoph.muellner@vrull.eu>
>>
>>
>> >
>> > For details see:
>> > https://github.com/T-head-Semi/thead-extension-spec/pull/34
>> >
>> > gas/ChangeLog:
>> >
>> > * testsuite/gas/riscv/x-thead-fmv.d: Correct test.
>> > * testsuite/gas/riscv/x-thead-fmv.s: Likewise.
>> >
>> > include/ChangeLog:
>> >
>> > * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
>> > (MASK_TH_FMV_HW_X): Likewise.
>> > (MATCH_TH_FMV_X_HW): Likewise.
>> > (MASK_TH_FMV_X_HW): Likewise.
>> >
>> > opcodes/ChangeLog:
>> >
>> > * riscv-opc.c: Correct operands.
>> > ---
>> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
>> > gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +-
>> > include/opcode/riscv-opc.h | 8 ++++----
>> > opcodes/riscv-opc.c | 2 +-
>> > 4 files changed, 8 insertions(+), 8 deletions(-)
>> >
>> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > index af8ce0c8ee0..50ccc62413f 100644
>> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
>> > @@ -7,5 +7,5 @@
>> > Disassembly of section .text:
>> >
>> > 0+000 <target>:
>> > -[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
>> > -[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > +[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0
>> > +[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
>> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s
>> > index 250ba8358ae..8ca2ec2f093 100644
>> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.s
>> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
>> > @@ -1,3 +1,3 @@
>> > target:
>> > - th.fmv.hw.x a0, fa1
>> > + th.fmv.hw.x fa1, a0
>> > th.fmv.x.hw a1, fa0
>> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> > index 24217062edc..061e35d8603 100644
>> > --- a/include/opcode/riscv-opc.h
>> > +++ b/include/opcode/riscv-opc.h
>> > @@ -2515,10 +2515,10 @@
>> > #define MATCH_TH_FSURW 0x5000700b
>> > #define MASK_TH_FSURW 0xf800707f
>> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
>> > -#define MATCH_TH_FMV_HW_X 0x5000100b
>> > -#define MASK_TH_FMV_HW_X 0xfff0707f
>> > -#define MATCH_TH_FMV_X_HW 0x6000100b
>> > -#define MASK_TH_FMV_X_HW 0xfff0707f
>> > +#define MATCH_TH_FMV_X_HW 0xc000100b
>> > +#define MASK_TH_FMV_X_HW 0xfff0707f
>> > +#define MATCH_TH_FMV_HW_X 0xa000100b
>> > +#define MASK_TH_FMV_HW_X 0xfff0707f
>> > /* Vendor-specific (T-Head) XTheadInt instructions. */
>> > #define MATCH_TH_IPOP 0x0050000b
>> > #define MASK_TH_IPOP 0xffffffff
>> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> > index 72d727cd77e..3a4ab62d274 100644
>> > --- a/opcodes/riscv-opc.c
>> > +++ b/opcodes/riscv-opc.c
>> > @@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
>> > {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
>> >
>> > /* Vendor-specific (T-Head) XTheadFmv instructions. */
>> > -{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
>> > +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
>> > {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
>> >
>> > /* Vendor-specific (T-Head) XTheadInt instructions. */
>> >
>> > base-commit: 0da4f405f8d9d15b9381075debce788251e31815
>> > --
>> > 2.17.1
>> >
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-12-14 8:57 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2023-11-17 6:20 [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension Jin Ma
2023-12-13 7:00 ` Christoph Müllner
2023-12-14 3:05 ` Nelson Chu
2023-12-14 8:57 ` Christoph Müllner
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