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From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
	 Andrew Waterman <andrew@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Jim Wilson <jim.wilson.gcc@gmail.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	 Aaron Durbin <adurbin@rivosinc.com>,
	Andrew de los Reyes <adlr@rivosinc.com>,
	 Eric Gouriou <ego@rivosinc.com>,
	Barna Ibrahim <barna@rivosinc.com>
Subject: Re: [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support
Date: Thu, 22 Dec 2022 15:17:43 +0100	[thread overview]
Message-ID: <CAEg0e7ic7gRXxvg8NTVC_50cyJGQOexunQ86hf2Qx6k-Ov6C6A@mail.gmail.com> (raw)
In-Reply-To: <be46ac8d-bfdb-91c7-3044-15a26d40aa97@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 1591 bytes --]

On Wed, Dec 21, 2022 at 10:24 PM Jeff Law <jeffreyalaw@gmail.com> wrote:

>
>
> On 12/21/22 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> > of the vector crypto extensions.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   bfd/elfxx-riscv.c                     | 13 +++++++++++++
> >   gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
> >   gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
> >   gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
> >   include/opcode/riscv-opc.h            | 11 +++++++++++
> >   include/opcode/riscv.h                |  3 +++
> >   opcodes/riscv-opc.c                   |  5 +++++
> >   7 files changed, 59 insertions(+)
> >   create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> >   create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> >   create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
> Looks reasonable to me.  Just one comment nit below...
>
>
>
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index bb716c8c9d0..35d3e653147 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
> >   /* Zvkg instructions.  */
> >   {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV,
> MASK_VGHMACVV, match_opcode, 0},
> >
> > +/* Xvkh[a,b] instructions.  */
> Are these X or Z?
>

Thanks for spotting this!



>
> Jeff
>

  reply	other threads:[~2022-12-22 14:17 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
2022-12-21 17:07 ` [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
2022-12-21 20:50   ` Jeff Law
2022-12-22 14:23     ` Christoph Müllner
2023-01-20 19:04   ` Philipp Tomsich
2023-01-20 19:21     ` Christoph Müllner
2022-12-21 17:07 ` [RFC PATCH 2/6] RISC-V: Add Zvkg " Christoph Muellner
2022-12-21 21:16   ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] " Christoph Muellner
2022-12-21 21:24   ` Jeff Law
2022-12-22 14:17     ` Christoph Müllner [this message]
2023-01-03 22:00   ` Philipp Tomsich
2022-12-21 17:07 ` [RFC PATCH 4/6] RISC-V: Add Zvkn " Christoph Muellner
2022-12-21 21:26   ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 5/6] RISC-V: Add Zvksed " Christoph Muellner
2022-12-21 21:30   ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 6/6] RISC-V: Add Zvksh " Christoph Muellner
2022-12-21 21:33   ` Jeff Law
2022-12-22  2:46 ` [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Kito Cheng

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