* [PATCH v2 1/5] RISC-V: Add mininal support for Zicbo[mpz]
2022-01-11 10:23 [PATCH v2 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
@ 2022-01-11 10:23 ` Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 2/5] RISC-V: Cache management instructions Tsukasa OI
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
Minimal support for 'Zicbom', 'Zicboz' and 'Zicbop' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbom',
'Zicbop' and 'Zicboz' standard 'Z' extensions.
---
bfd/elfxx-riscv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9f52bb545ac..3761811d4fd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1179,6 +1179,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 2/5] RISC-V: Cache management instructions
2022-01-11 10:23 [PATCH v2 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
@ 2022-01-11 10:23 ` Tsukasa OI
2022-02-09 1:24 ` Christoph Müllner
2022-01-11 10:23 ` [PATCH v2 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 4 ++++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
4 files changed, 21 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3761811d4fd..a7cd9320655 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0b8cc6c7ddb..b24e8a47c87 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2029,6 +2029,15 @@
#define MASK_HSV_W 0xfe007fff
#define MATCH_HSV_D 0x6e004073
#define MASK_HSV_D 0xfe007fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..1d74f0e521a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,8 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..07835ddd071 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/5] RISC-V: Cache management instructions
2022-01-11 10:23 ` [PATCH v2 2/5] RISC-V: Cache management instructions Tsukasa OI
@ 2022-02-09 1:24 ` Christoph Müllner
2022-02-09 2:37 ` Tsukasa OI
0 siblings, 1 reply; 8+ messages in thread
From: Christoph Müllner @ 2022-02-09 1:24 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils
On Tue, Jan 11, 2022 at 11:26 AM Tsukasa OI via Binutils <
binutils@sourceware.org> wrote:
> This commit adds 'Zicbom' / 'Zicboz' instructions.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
> new instruction classes.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
> MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
> MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
> classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c (riscv_opcodes): Add cache-block management
> instructions.
> ---
> bfd/elfxx-riscv.c | 4 ++++
> include/opcode/riscv-opc.h | 9 +++++++++
> include/opcode/riscv.h | 2 ++
> opcodes/riscv-opc.c | 6 ++++++
> 4 files changed, 21 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 3761811d4fd..a7cd9320655 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> {
> case INSN_CLASS_I:
> return riscv_subset_supports (rps, "i");
> + case INSN_CLASS_ZICBOM:
> + return riscv_subset_supports (rps, "zicbom");
> + case INSN_CLASS_ZICBOZ:
> + return riscv_subset_supports (rps, "zicboz");
> case INSN_CLASS_ZICSR:
> return riscv_subset_supports (rps, "zicsr");
> case INSN_CLASS_ZIFENCEI:
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 0b8cc6c7ddb..b24e8a47c87 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2029,6 +2029,15 @@
> #define MASK_HSV_W 0xfe007fff
> #define MATCH_HSV_D 0x6e004073
> #define MASK_HSV_D 0xfe007fff
> +/* Zicbom/Zicboz instructions. */
> +#define MATCH_CBO_CLEAN 0x10200f
> +#define MASK_CBO_CLEAN 0xfff07fff
> +#define MATCH_CBO_FLUSH 0x20200f
> +#define MASK_CBO_FLUSH 0xfff07fff
> +#define MATCH_CBO_INVAL 0x200f
> +#define MASK_CBO_INVAL 0xfff07fff
> +#define MATCH_CBO_ZERO 0x40200f
> +#define MASK_CBO_ZERO 0xfff07fff
> /* Privileged CSR addresses. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 048ab0a5d68..1d74f0e521a 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -388,6 +388,8 @@ enum riscv_insn_class
> INSN_CLASS_V,
> INSN_CLASS_ZVEF,
> INSN_CLASS_SVINVAL,
> + INSN_CLASS_ZICBOM,
> + INSN_CLASS_ZICBOZ,
> };
>
> /* This structure holds information for a particular instruction. */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 2da0f7cf0a4..07835ddd071 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA,
> MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI,
> match_opcode, 0 },
>
> +/* Zicbom and Zicboz instructions. */
> +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN,
> MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH,
> MASK_CBO_FLUSH, match_opcode, 0 },
> +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL,
> MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO,
> match_opcode, 0 },
> +
>
Hi Tsukasa,
There has been a discussion ([1]) about using "0(a0)"/"(a0)" vs "a0" as
operand format for these instructions.
Following that discussion, I'd suggest using the AMO (zero-)displacement
format ("0(s)") here (and adjusting the tests accordingly).
BR
Christoph
[1] https://github.com/riscv/riscv-CMOs/issues/47
> /* Zbb or zbkb instructions. */
> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ,
> match_opcode, 0 },
> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ,
> match_opcode, 0 },
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/5] RISC-V: Cache management instructions
2022-02-09 1:24 ` Christoph Müllner
@ 2022-02-09 2:37 ` Tsukasa OI
0 siblings, 0 replies; 8+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:37 UTC (permalink / raw)
To: Binutils
(I forgot to add Cc:binutils@sourceware.org to my response to Chris)
On 2022/02/09 10:24, Christoph Müllner wrote:
>
>
> On Tue, Jan 11, 2022 at 11:26 AM Tsukasa OI via Binutils <binutils@sourceware.org <mailto:binutils@sourceware.org>> wrote:
>
> This commit adds 'Zicbom' / 'Zicboz' instructions.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
> new instruction classes.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
> MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
> MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
> classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c (riscv_opcodes): Add cache-block management
> instructions.
> ---
> bfd/elfxx-riscv.c | 4 ++++
> include/opcode/riscv-opc.h | 9 +++++++++
> include/opcode/riscv.h | 2 ++
> opcodes/riscv-opc.c | 6 ++++++
> 4 files changed, 21 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 3761811d4fd..a7cd9320655 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> {
> case INSN_CLASS_I:
> return riscv_subset_supports (rps, "i");
> + case INSN_CLASS_ZICBOM:
> + return riscv_subset_supports (rps, "zicbom");
> + case INSN_CLASS_ZICBOZ:
> + return riscv_subset_supports (rps, "zicboz");
> case INSN_CLASS_ZICSR:
> return riscv_subset_supports (rps, "zicsr");
> case INSN_CLASS_ZIFENCEI:
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 0b8cc6c7ddb..b24e8a47c87 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2029,6 +2029,15 @@
> #define MASK_HSV_W 0xfe007fff
> #define MATCH_HSV_D 0x6e004073
> #define MASK_HSV_D 0xfe007fff
> +/* Zicbom/Zicboz instructions. */
> +#define MATCH_CBO_CLEAN 0x10200f
> +#define MASK_CBO_CLEAN 0xfff07fff
> +#define MATCH_CBO_FLUSH 0x20200f
> +#define MASK_CBO_FLUSH 0xfff07fff
> +#define MATCH_CBO_INVAL 0x200f
> +#define MASK_CBO_INVAL 0xfff07fff
> +#define MATCH_CBO_ZERO 0x40200f
> +#define MASK_CBO_ZERO 0xfff07fff
> /* Privileged CSR addresses. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 048ab0a5d68..1d74f0e521a 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -388,6 +388,8 @@ enum riscv_insn_class
> INSN_CLASS_V,
> INSN_CLASS_ZVEF,
> INSN_CLASS_SVINVAL,
> + INSN_CLASS_ZICBOM,
> + INSN_CLASS_ZICBOZ,
> };
>
> /* This structure holds information for a particular instruction. */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 2da0f7cf0a4..07835ddd071 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
>
> +/* Zicbom and Zicboz instructions. */
> +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
> +
>
>
> Hi Tsukasa,
>
> There has been a discussion ([1]) about using "0(a0)"/"(a0)" vs "a0" as operand format for these instructions.
> Following that discussion, I'd suggest using the AMO (zero-)displacement format ("0(s)") here (and adjusting the tests accordingly).
>
> BR
> Christoph
I'm not sure that `cbo.zero 0(a0)' (for example) is right (I will just
follow the conclusion of the discussion). Still, it's not bad to have
an option.
So, I made one (mutually exclusive to old patchset):
<https://sourceware.org/pipermail/binutils/2022-February/119708.html>
Thanks,
Tsukasa
>
> [1] https://github.com/riscv/riscv-CMOs/issues/47 <https://github.com/riscv/riscv-CMOs/issues/47>
>
>
>
> /* Zbb or zbkb instructions. */
> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/5] RISC-V: Cache management instruction testcases
2022-01-11 10:23 [PATCH v2 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 2/5] RISC-V: Cache management instructions Tsukasa OI
@ 2022-01-11 10:23 ` Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
4 siblings, 0 replies; 8+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds testcases for 'Zicbom' / 'Zicboz' instructions.
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
---
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
gas/testsuite/gas/riscv/zicboz.s | 3 +++
4 files changed, 36 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..3a194cf6edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+ra
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+ra
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..778a61e76f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean x1
+ cbo.clean x30
+ cbo.flush x1
+ cbo.flush x30
+ cbo.inval x1
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7686edbe677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,11 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+ra
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ba75b787b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero x30
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/5] RISC-V: Prefetch hint instructions and operand set
2022-01-11 10:23 [PATCH v2 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
` (2 preceding siblings ...)
2022-01-11 10:23 ` [PATCH v2 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
@ 2022-01-11 10:23 ` Tsukasa OI
2022-01-11 10:23 ` [PATCH v2 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
4 siblings, 0 replies; 8+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
---
bfd/elfxx-riscv.c | 2 ++
gas/config/tc-riscv.c | 18 ++++++++++++++++++
include/opcode/riscv-opc.h | 7 +++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 3 +++
6 files changed, 35 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a7cd9320655..2bd45a0bf17 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2336,6 +2336,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "i");
case INSN_CLASS_ZICBOM:
return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 390aaf1710b..773907bfa61 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break; /* Zero immediate. */
case '[': break; /* Unused operand. */
@@ -3163,6 +3164,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
continue;
+ case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
+ if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
+ continue;
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, false);
+ if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
+ || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
+ || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
+ as_bad (_("improper prefetch offset (%ld)"),
+ (long) imm_expr->X_add_number);
+ ip->insn_opcode |=
+ ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
+ ~ 0x1fU);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b24e8a47c87..203bcdb9212 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2038,6 +2038,13 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zicbop hint instructions. */
+#define MATCH_PREFETCH_I 0x6013
+#define MASK_PREFETCH_I 0x1f07fff
+#define MATCH_PREFETCH_R 0x106013
+#define MASK_PREFETCH_R 0x1f07fff
+#define MATCH_PREFETCH_W 0x306013
+#define MASK_PREFETCH_W 0x1f07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1d74f0e521a..b769769b4ec 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -389,6 +389,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
};
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 34724d4aec5..57b798d8e14 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
break;
+ case 'f':
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
case 'a':
info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 07835ddd071..c472c6d3252 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
+{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
+{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
+{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 5/5] RISC-V: Prefetch hint instruction testcases
2022-01-11 10:23 [PATCH v2 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
` (3 preceding siblings ...)
2022-01-11 10:23 ` [PATCH v2 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
@ 2022-01-11 10:23 ` Tsukasa OI
4 siblings, 0 replies; 8+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds testcases for 'Zicbop' hint instructions.
gas/ChangeLog:
* testsuite/gas/riscv/zicbop-fail.d: New testcase for invalid
prefetch hint instructions.
* testsuite/gas/riscv/zicbop-fail.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Likewise.
* testsuite/gas/riscv/zicbop.d: New testcase for prefetch hint
instructions.
* testsuite/gas/riscv/zicbop.s: Likewise.
---
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
5 files changed, 27 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
new file mode 100644
index 00000000000..d734c7d4d15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbop
+#source: zicbop-fail.s
+#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l
new file mode 100644
index 00000000000..4b5d5fc84fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: improper prefetch offset \(2048\)
+.*: Error: improper prefetch offset \(-2080\)
+.*: Error: improper prefetch offset \(255\)
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s
new file mode 100644
index 00000000000..0353c5ff80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 2048(x1)
+ prefetch.r -0x820(x16)
+ prefetch.w +0xff(x31)
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
new file mode 100644
index 00000000000..056a8a501ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicbop
+#source: zicbop.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
new file mode 100644
index 00000000000..ffe2014be6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 0x20(x1)
+ prefetch.r -2048(x16)
+ prefetch.w +0x7e0(x31)
--
2.32.0
^ permalink raw reply [flat|nested] 8+ messages in thread