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From: Nelson Chu <nelson.chu@sifive.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V
Date: Mon, 7 Feb 2022 14:47:05 +0800	[thread overview]
Message-ID: <CAJYME4HeKH+pTHNod4OyS2rqOYtRJpRhpWXLicUqs455PqmwuQ@mail.gmail.com> (raw)
In-Reply-To: <cover.1644113385.git.research_trasio@irq.a4lg.com>

On Sun, Feb 6, 2022 at 10:11 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> *** NOTE ***
> PATCH 1 contains non-RISC-V (GDB-related) changes.
>
>
> This patchset adds support for isa=ISA diassembler option to RISC-V.
>
> -   objdump: -M isa=rv[32|64]...

Not sure why we need it, but it would be better to discuss with the
community (gcc and llvm) for something new like this first.  You could
try to create new issues on riscv psabi
(https://github.com/riscv-non-isa/riscv-elf-psabi-doc) or riscv asm
manual (https://github.com/riscv-non-isa/riscv-asm-manual).   If the
issues should be discussed elsewhere, I believe someone will tell you
there.

> -   gdb: set disassembler-options isa=rv[32|64]...

You should also send the gdb patch to gdb-patches@sourceware.org.
There will be more gdb experts over there.

> This patchset is version 2.  Version 1 is here:
> <https://sourceware.org/pipermail/binutils/2022-February/119639.html>
> <https://github.com/a4lg/binutils-gdb/tree/a4lg/snapshots/2022-02-05/riscv-dis-isa>
>
> My development branch on GitHub:
> <https://github.com/a4lg/binutils-gdb/tree/riscv-dis-isa>
>
>
> [Changes between RFC PATCH v1 and RFC PATCH v2]
>
> The only functional change in the RFC PATCH v2 is that we reset `xlen'
> variable to `0' before parsing ISA string.  It has no effect on objdump
> but on GDB, it stops preserving last XLEN value before setting invalid
> ISA string (not starting with "rv32" or "rv64").
>
> Rest of the changes are editorial.  My language got broken while writing
> v1 but I think most of them are fixed in v2.  Also, most "-M isa"
> (objdump-only) references are replaced with just "isa" to indicate
> both objdump and GDB options.
>
> Renamed `xlen_set_by_option' to `xlen_by_isa' for clarity (meaning XLEN
> set by "ISA string" option).
>
>
>
>
> Tsukasa OI (2):
>   gdb, opcodes: Add non-enum disassembler options
>   RISC-V: Add isa disassembler option
>
>  gdb/disasm.c        |  4 ++++
>  include/dis-asm.h   |  3 ++-
>  opcodes/arc-dis.c   |  2 ++
>  opcodes/mips-dis.c  |  2 ++
>  opcodes/riscv-dis.c | 35 ++++++++++++++++++++++++++++-------
>  5 files changed, 38 insertions(+), 8 deletions(-)
>
>
> base-commit: 94e57f287f96af6af97dd086e4a04ddf55b7cf60
> --
> 2.32.0
>

  parent reply	other threads:[~2022-02-07  6:47 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-05 10:24 [RFC PATCH 0/2] gdb, opcodes: Add -M " Tsukasa OI
2022-02-05 10:24 ` [RFC PATCH 1/2] gdb, opcodes: Add non-enum disassembler options Tsukasa OI
2022-02-05 10:24 ` [RFC PATCH 2/2] RISC-V: Add -M isa disassembler option Tsukasa OI
2022-02-24 18:00   ` Palmer Dabbelt
2022-02-06  2:10 ` [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V Tsukasa OI
2022-02-06  2:10   ` [RFC PATCH v2 1/2] gdb, opcodes: Add non-enum disassembler options Tsukasa OI
2022-02-06  2:10   ` [RFC PATCH v2 2/2] RISC-V: Add isa disassembler option Tsukasa OI
2022-02-07  6:47   ` Nelson Chu [this message]
2022-02-07  9:58     ` [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V Tsukasa OI
2022-02-07 10:06       ` Kito Cheng
2022-02-07 10:19         ` Tsukasa OI

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