[RFC PATCH 0/2] gdb, opcodes: Add -M isa disassembler option to RISC-V

[Tsukasa OI <research_trasio@irq.a4lg.com>]

*** NOTE ***
PATCH 1 contains non-RISC-V (GDB-related) changes.


This patchset adds support for -M isa=ISA diassembler option to RISC-V.

The background is simple.  This patchset enables disassembling non-GC
instructions on binary files (without .riscv.attributes section).

However, this isn't that simple as it requires non-arch changes.



[PATCH 1: gdb, opcodes: Add non-enum disassembler options]

There is a portable mechanism for disassembler options and used on some
architectures:

-   ARC
-   Arm
-   MIPS
-   PowerPC
-   RISC-V
-   S/390

However, it only supports following forms:

-   [NAME]
-   [NAME]=[ENUM_VALUE]

Valid values for [ENUM_VALUE] must be predefined in
`disasm_option_arg_t.values'.  For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.

In PATCH 1 of this patchset, it adds following format:

-   [NAME]=[ARBITRARY_VALUE] (however cannot contain ",")

This is identified by `NULL' value of `disasm_option_arg_t.values'
(normally, this is a non-NULL pointer to a NULL-terminated list).

Note that this patch modifies following architectures (that use
similar code to print disassembler help message) for consistency:

-   ARC
-   MIPS
-   RISC-V

In the future, adding "verify" function to disasm_option_arg_t (or some)
might be an option as it may provide flexible argument validation.



[PATCH 2: RISC-V: Add -M isa disassembler option]

-M isa=ISA is very simple.  But we have multiple ways to set proper
XLEN for given situation.

In this patch, I propose following precedence rules (objdump/gdb):

1.  XLEN-specified arch (-m riscv:rv[32|64] / set arch riscv:rv[32|64])
2.  ISA option (-M isa=rv[32|64]... / set disassembler-options isa=...)
3.  ELF class in the "ELF header" (note that this must be the last
    because dummy "ELF header" exists even in binary files)

This enables XLEN switching by ISA option on architecture riscv but not
on riscv:rv32 or riscv:rv64 (architecture with fixed XLEN is preferred).

I preferred not to warn if XLEN in above three conflict because of
"dummy ELF header" described above and possible dynamic capability when
used together with GDB.  Still, adding it might be an option.




Tsukasa OI (2):
  gdb, opcodes: Add non-enum disassembler options
  RISC-V: Add -M isa disassembler option

 gdb/disasm.c        |  4 ++++
 include/dis-asm.h   |  3 ++-
 opcodes/arc-dis.c   |  2 ++
 opcodes/mips-dis.c  |  2 ++
 opcodes/riscv-dis.c | 34 +++++++++++++++++++++++++++-------
 5 files changed, 37 insertions(+), 8 deletions(-)


base-commit: eb06e60a982e3903161252edf8fb8ae0c018c467
-- 
2.32.0