* RISCV relocs .
@ 2022-05-27 9:30 umesh kalappa
2022-05-27 9:45 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: umesh kalappa @ 2022-05-27 9:30 UTC (permalink / raw)
To: binutils
Hi All ,
We build the loadable kernel module ,where we do partially link (-r) and
for riscv
we are understanding the relocs like
000000000030 001300000034 R_RISCV_SUB6 0000000000000002 <null> + 0
000000000033 001700000035 R_RISCV_SET6 0000000000000008 <null> + 0
Currently we are ignoring the above relocs ,is that ok to do so ?
~Umesh
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: RISCV relocs .
2022-05-27 9:30 RISCV relocs umesh kalappa
@ 2022-05-27 9:45 ` Kito Cheng
2022-05-27 10:07 ` umesh kalappa
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2022-05-27 9:45 UTC (permalink / raw)
To: umesh kalappa; +Cc: Binutils
Those relocations are used in EH frame and debug info IIRC.
On Fri, May 27, 2022 at 5:31 PM umesh kalappa via Binutils
<binutils@sourceware.org> wrote:
>
> Hi All ,
>
> We build the loadable kernel module ,where we do partially link (-r) and
> for riscv
>
> we are understanding the relocs like
>
> 000000000030 001300000034 R_RISCV_SUB6 0000000000000002 <null> + 0
> 000000000033 001700000035 R_RISCV_SET6 0000000000000008 <null> + 0
>
> Currently we are ignoring the above relocs ,is that ok to do so ?
>
> ~Umesh
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: RISCV relocs .
2022-05-27 9:45 ` Kito Cheng
@ 2022-05-27 10:07 ` umesh kalappa
0 siblings, 0 replies; 3+ messages in thread
From: umesh kalappa @ 2022-05-27 10:07 UTC (permalink / raw)
To: Kito Cheng; +Cc: Binutils
Thank you Kito for the quick reply.
Do we need to relocate them to enable debugging and stack unwinding.
~Umesh
On Fri, May 27, 2022 at 3:15 PM Kito Cheng <kito.cheng@gmail.com> wrote:
> Those relocations are used in EH frame and debug info IIRC.
>
>
> On Fri, May 27, 2022 at 5:31 PM umesh kalappa via Binutils
> <binutils@sourceware.org> wrote:
> >
> > Hi All ,
> >
> > We build the loadable kernel module ,where we do partially link (-r) and
> > for riscv
> >
> > we are understanding the relocs like
> >
> > 000000000030 001300000034 R_RISCV_SUB6 0000000000000002 <null> + 0
> > 000000000033 001700000035 R_RISCV_SET6 0000000000000008 <null> + 0
> >
> > Currently we are ignoring the above relocs ,is that ok to do so ?
> >
> > ~Umesh
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-05-27 9:30 RISCV relocs umesh kalappa
2022-05-27 9:45 ` Kito Cheng
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