From: "H.J. Lu" <hjl.tools@gmail.com>
To: Haochen Jiang <haochen.jiang@intel.com>
Cc: binutils@sourceware.org, jbeulich@suse.com, "Hu,
Lin1" <lin1.hu@intel.com>
Subject: Re: [PATCH 5/6] Support Intel WRMSRNS
Date: Mon, 31 Oct 2022 09:56:55 -0700 [thread overview]
Message-ID: <CAMe9rOoTL_HVMKzm3oq=FKYimoFVPMSg2v_-1ocB2BX=s9eetA@mail.gmail.com> (raw)
In-Reply-To: <20221031030507.35588-6-haochen.jiang@intel.com>
On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> From: "Hu, Lin1" <lin1.hu@intel.com>
>
> gas/ChangeLog:
>
> * NEWS: Support Intel WRMSRNS.
> * config/tc-i386.c: Add wrmsrns.
> * doc/c-i386.texi: Document .wrmsrns.
> * testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
> * testsuite/gas/i386/wrmsrns-intel.d: New test.
> * testsuite/gas/i386/wrmsrns.d: Ditto.
> * testsuite/gas/i386/wrmsrns.s: Ditto.
> * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
> * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
> (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
> (rm_table): New entry for wrmsrns.
> * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
> and CPU_ANY_WRMSRNS_FLAGS.
> (cpu_flags): Add CpuWRMSRNS.
> * i386-init.h: Regenerated.
> * i386-opc.h (CpuWRMSRNS): New.
> (i386_cpu_flags): Add cpuwrmsrns.
> * i386-opc.tbl: Add WRMSRNS instructions.
> * i386-tbl.h: Regenerated.
> ---
> gas/NEWS | 2 +
> gas/config/tc-i386.c | 1 +
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/i386.exp | 4 +
> gas/testsuite/gas/i386/wrmsrns-intel.d | 5 +
> gas/testsuite/gas/i386/wrmsrns.d | 12 +
> gas/testsuite/gas/i386/wrmsrns.s | 8 +
> gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 5 +
> gas/testsuite/gas/i386/x86-64-wrmsrns.d | 5 +
> opcodes/i386-dis.c | 7 +
> opcodes/i386-gen.c | 5 +
> opcodes/i386-init.h | 514 +-
> opcodes/i386-opc.h | 3 +
> opcodes/i386-opc.tbl | 6 +
> opcodes/i386-tbl.h | 7839 +++++++++--------
> 15 files changed, 4257 insertions(+), 4162 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d
> create mode 100644 gas/testsuite/gas/i386/wrmsrns.d
> create mode 100644 gas/testsuite/gas/i386/wrmsrns.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 7cdd429f0b..c448ec7861 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel WRMSRNS instructions.
> +
> * Add support for Intel CMPccXADD instructions.
>
> * Add support for Intel AVX-VNNI-INT8 instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index 99d1a4cfec..d387f93ea0 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
> + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
> };
>
> #undef SUBARCH
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index f98b9fbd9f..47aa02b334 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -198,6 +198,7 @@ accept various extension mnemonics. For example,
> @code{avx_ifma},
> @code{avx_vnni_int8},
> @code{cmpccxadd},
> +@code{wrmsrns},
> @code{amx_int8},
> @code{amx_bf16},
> @code{amx_fp16},
> @@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
> @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
> @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
> -@item @samp{.cmpccxadd}
> +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns}
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
> @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
> @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index e9785e64fd..d3797937a7 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -480,6 +480,8 @@ if [gas_32_check] then {
> run_dump_test "avx-vnni-int8"
> run_dump_test "avx-vnni-int8-intel"
> run_list_test "cmpccxadd-inval"
> + run_dump_test "wrmsrns"
> + run_dump_test "wrmsrns-intel"
> run_list_test "sg"
> run_dump_test "clzero"
> run_dump_test "invlpgb"
> @@ -1155,6 +1157,8 @@ if [gas_64_check] then {
> run_dump_test "x86-64-avx-vnni-int8-intel"
> run_dump_test "x86-64-cmpccxadd"
> run_dump_test "x86-64-cmpccxadd-intel"
> + run_dump_test "x86-64-wrmsrns"
> + run_dump_test "x86-64-wrmsrns-intel"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> run_list_test "x86-64-mwaitx-reg"
> diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d
> new file mode 100644
> index 0000000000..b3be2609d8
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/wrmsrns-intel.d
> @@ -0,0 +1,5 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: i386 WRMSRNS insns (Intel disassembly)
> +#source: wrmsrns.s
> +#dump: wrmsrns.d
> diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d
> new file mode 100644
> index 0000000000..e804adc501
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/wrmsrns.d
> @@ -0,0 +1,12 @@
> +#as:
> +#objdump: -dw
> +#name: i386 WRMSRNS insns
> +#source: wrmsrns.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
> +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
> diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s
> new file mode 100644
> index 0000000000..a450b0536d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/wrmsrns.s
> @@ -0,0 +1,8 @@
> +# Check WRMSRNS instructions
> +
> + .text
> +_start:
> + wrmsrns #WRMSRNS
> +
> +.intel_syntax noprefix
> + wrmsrns #WRMSRNS
> diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
> new file mode 100644
> index 0000000000..ff80e55b7c
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
> @@ -0,0 +1,5 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86_64 WRMSRNS insns (Intel disassembly)
> +#source: wrmsrns.s
> +#dump: wrmsrns.d
> diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
> new file mode 100644
> index 0000000000..047f0a1a7d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
> @@ -0,0 +1,5 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 WRMSRNS insns
> +#source: wrmsrns.s
> +#dump: wrmsrns.d
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 116450c871..fb1c14b5b5 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -985,6 +985,7 @@ enum
> enum
> {
> PREFIX_90 = 0,
> + PREFIX_0F01_REG_0_MOD_3_RM_6,
> PREFIX_0F01_REG_1_RM_4,
> PREFIX_0F01_REG_1_RM_5,
> PREFIX_0F01_REG_1_RM_6,
> @@ -2954,6 +2955,11 @@ static const struct dis386 prefix_table[][4] = {
> { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
> },
>
> + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
> + {
> + { "wrmsrns", { Skip_MODRM }, 0 },
> + },
> +
> /* PREFIX_0F01_REG_1_RM_4 */
> {
> { Bad_Opcode },
> @@ -8634,6 +8640,7 @@ static const struct dis386 rm_table[][8] = {
> { "vmresume", { Skip_MODRM }, 0 },
> { "vmxoff", { Skip_MODRM }, 0 },
> { "pconfig", { Skip_MODRM }, 0 },
> + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
> },
> {
> /* RM_0F01_REG_1 */
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index 55ed659d3d..a6dc8b904e 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
> "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
> { "CPU_CMPCCXADD_FLAGS",
> "CpuCMPCCXADD" },
> + { "CPU_WRMSRNS_FLAGS",
> + "CpuWRMSRNS" },
> { "CPU_IAMCU_FLAGS",
> "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> { "CPU_ADX_FLAGS",
> @@ -457,6 +459,8 @@ static initializer cpu_flag_init[] =
> "CpuAVX_VNNI_INT8" },
> { "CPU_ANY_CMPCCXADD_FLAGS",
> "CpuCMPCCXADD" },
> + { "CPU_ANY_WRMSRNS_FLAGS",
> + "CpuWRMSRNS" },
> };
>
> static initializer operand_type_init[] =
> @@ -662,6 +666,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuAVX_IFMA),
> BITFIELD (CpuAVX_VNNI_INT8),
> BITFIELD (CpuCMPCCXADD),
> + BITFIELD (CpuWRMSRNS),
> BITFIELD (CpuMWAITX),
> BITFIELD (CpuCLZERO),
> BITFIELD (CpuOSPKE),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 3b9572e2af..f00babfce2 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -217,6 +217,8 @@ enum
> CpuAVX_VNNI_INT8,
> /* Intel CMPccXADD instructions support required. */
> CpuCMPCCXADD,
> + /* Intel WRMSRNS Instructions support required */
> + CpuWRMSRNS,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
> @@ -402,6 +404,7 @@ typedef union i386_cpu_flags
> unsigned int cpuavx_ifma:1;
> unsigned int cpuavx_vnni_int8:1;
> unsigned int cpucmpccxadd:1;
> + unsigned int cpuwrmsrns:1;
> unsigned int cpumwaitx:1;
> unsigned int cpuclzero:1;
> unsigned int cpuospke:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 5fe9cb053f..3e947cd248 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3295,3 +3295,9 @@ prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No
> cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>
> // CMPCCXADD instructions end.
> +
> +// WRMSRNS instruction.
> +
> +wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
> +
> +// WRMSRNS instruction end.
> --
> 2.18.1
>
OK.
Thanks.
--
H.J.
next prev parent reply other threads:[~2022-10-31 16:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang
2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang
2022-10-31 16:52 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-31 16:53 ` H.J. Lu
2022-11-02 10:45 ` Jan Beulich
2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang
2022-10-31 16:54 ` H.J. Lu
2022-11-02 10:52 ` Jan Beulich
2022-11-02 16:25 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-31 16:54 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang
2022-10-31 16:56 ` H.J. Lu [this message]
2022-11-02 10:56 ` Jan Beulich
2022-11-02 14:35 ` Jan Beulich
2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang
2022-10-31 16:55 ` H.J. Lu
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