From: "H.J. Lu" <hjl.tools@gmail.com>
To: Haochen Jiang <haochen.jiang@intel.com>
Cc: binutils@sourceware.org, jbeulich@suse.com, "Hu,
Lin1" <lin1.hu@intel.com>
Subject: Re: [PATCH 6/6] Support Intel MSRLIST
Date: Mon, 31 Oct 2022 09:55:51 -0700 [thread overview]
Message-ID: <CAMe9rOqPP4g1Fv_MnuQ_8VFpprpb5-+drJsqsT6rALbJriRC5g@mail.gmail.com> (raw)
In-Reply-To: <20221031030507.35588-7-haochen.jiang@intel.com>
On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> From: "Hu, Lin1" <lin1.hu@intel.com>
>
> gas/ChangeLog:
>
> * NEWS: Support Intel MSRLIST.
> * config/tc-i386.c: Add msrlist.
> * doc/c-i386.texi: Document .msrlist.
> * testsuite/gas/i386/i386.exp: Add MSRLIST tests.
> * testsuite/gas/i386/msrlist-inval.l: New test.
> * testsuite/gas/i386/msrlist-inval.s: Ditto.
> * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
> * testsuite/gas/i386/x86-64-msrlist.d: Ditto.
> * testsuite/gas/i386/x86-64-msrlist.s: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
> (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
> (prefix_table): New entry for msrlist.
> (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
> and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
> * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
> and CPU_ANY_MSRLIST_FLAGS.
> * i386-init.h: Regenerated.
> * i386-opc.h (CpuMSRLIST): New.
> (i386_cpu_flags): Add cpumsrlist.
> * i386-opc.tbl: Add MSRLIST instructions.
> * i386-tbl.h: Regenerated.
> ---
> gas/NEWS | 2 +
> gas/config/tc-i386.c | 1 +
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/i386.exp | 3 +
> gas/testsuite/gas/i386/msrlist-inval.l | 3 +
> gas/testsuite/gas/i386/msrlist-inval.s | 7 +
> gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 5 +
> gas/testsuite/gas/i386/x86-64-msrlist.d | 14 +
> gas/testsuite/gas/i386/x86-64-msrlist.s | 10 +
> opcodes/i386-dis.c | 17 +
> opcodes/i386-gen.c | 5 +
> opcodes/i386-init.h | 516 +-
> opcodes/i386-opc.h | 3 +
> opcodes/i386-opc.tbl | 7 +
> opcodes/i386-tbl.h | 7852 +++++++++--------
> 15 files changed, 4285 insertions(+), 4163 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l
> create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s
>
> diff --git a/gas/NEWS b/gas/NEWS
> index c448ec7861..c9df5608ec 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel MSRLIST instructions.
> +
> * Add support for Intel WRMSRNS instructions.
>
> * Add support for Intel CMPccXADD instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index d387f93ea0..e1de7d9c76 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
> SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
> + SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
> };
>
> #undef SUBARCH
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index 47aa02b334..1774979a83 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -199,6 +199,7 @@ accept various extension mnemonics. For example,
> @code{avx_vnni_int8},
> @code{cmpccxadd},
> @code{wrmsrns},
> +@code{msrlist},
> @code{amx_int8},
> @code{amx_bf16},
> @code{amx_fp16},
> @@ -1493,7 +1494,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
> @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
> @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
> -@item @samp{.cmpccxadd} @tab @samp{.wrmsrns}
> +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
> @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
> @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index d3797937a7..9eaadd131d 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -482,6 +482,7 @@ if [gas_32_check] then {
> run_list_test "cmpccxadd-inval"
> run_dump_test "wrmsrns"
> run_dump_test "wrmsrns-intel"
> + run_list_test "msrlist-inval"
> run_list_test "sg"
> run_dump_test "clzero"
> run_dump_test "invlpgb"
> @@ -1159,6 +1160,8 @@ if [gas_64_check] then {
> run_dump_test "x86-64-cmpccxadd-intel"
> run_dump_test "x86-64-wrmsrns"
> run_dump_test "x86-64-wrmsrns-intel"
> + run_dump_test "x86-64-msrlist"
> + run_dump_test "x86-64-msrlist-intel"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> run_list_test "x86-64-mwaitx-reg"
> diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l
> new file mode 100644
> index 0000000000..456f41c38f
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/msrlist-inval.l
> @@ -0,0 +1,3 @@
> +.* Assembler messages:
> +.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
> +.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
> diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s
> new file mode 100644
> index 0000000000..3c3258a375
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/msrlist-inval.s
> @@ -0,0 +1,7 @@
> +# Check Illegal MSRLIST instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + rdmsrlist #MSRLIST
> + wrmsrlist #MSRLIST
> diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
> new file mode 100644
> index 0000000000..b37adb573f
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
> @@ -0,0 +1,5 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86_64 MSRLIST insns (Intel disassembly)
> +#source: x86-64-msrlist.s
> +#dump: x86-64-msrlist.d
> diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d
> new file mode 100644
> index 0000000000..64beed7aa3
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-msrlist.d
> @@ -0,0 +1,14 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 MSRLIST insns
> +#source: x86-64-msrlist.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
> +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
> +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
> +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
> diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s
> new file mode 100644
> index 0000000000..45fb45256a
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-msrlist.s
> @@ -0,0 +1,10 @@
> +# Check 64bit MSRLIST instructions
> +
> + .text
> +_start:
> + rdmsrlist #MSRLIST
> + wrmsrlist #MSRLIST
> +
> +.intel_syntax noprefix
> + rdmsrlist #MSRLIST
> + wrmsrlist #MSRLIST
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index fb1c14b5b5..ab43d0cd8e 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -1262,6 +1262,8 @@ enum
> X86_64_E9,
> X86_64_EA,
> X86_64_0F01_REG_0,
> + X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
> + X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
> X86_64_0F01_REG_1,
> X86_64_0F01_REG_1_RM_5_PREFIX_2,
> X86_64_0F01_REG_1_RM_6_PREFIX_2,
> @@ -2958,6 +2960,9 @@ static const struct dis386 prefix_table[][4] = {
> /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
> {
> { "wrmsrns", { Skip_MODRM }, 0 },
> + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
> + { Bad_Opcode },
> + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
> },
>
> /* PREFIX_0F01_REG_1_RM_4 */
> @@ -4268,6 +4273,18 @@ static const struct dis386 x86_64_table[][2] = {
> { "sgdt", { M }, 0 },
> },
>
> + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
> + {
> + { Bad_Opcode },
> + { "wrmsrlist", { Skip_MODRM }, 0 },
> + },
> +
> + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
> + {
> + { Bad_Opcode },
> + { "rdmsrlist", { Skip_MODRM }, 0 },
> + },
> +
> /* X86_64_0F01_REG_1 */
> {
> { "sidt{Q|Q}", { M }, 0 },
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index a6dc8b904e..b820104234 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
> "CpuCMPCCXADD" },
> { "CPU_WRMSRNS_FLAGS",
> "CpuWRMSRNS" },
> + { "CPU_MSRLIST_FLAGS",
> + "CpuMSRLIST" },
> { "CPU_IAMCU_FLAGS",
> "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> { "CPU_ADX_FLAGS",
> @@ -461,6 +463,8 @@ static initializer cpu_flag_init[] =
> "CpuCMPCCXADD" },
> { "CPU_ANY_WRMSRNS_FLAGS",
> "CpuWRMSRNS" },
> + { "CPU_ANY_MSRLIST_FLAGS",
> + "CpuMSRLIST" },
> };
>
> static initializer operand_type_init[] =
> @@ -667,6 +671,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuAVX_VNNI_INT8),
> BITFIELD (CpuCMPCCXADD),
> BITFIELD (CpuWRMSRNS),
> + BITFIELD (CpuMSRLIST),
> BITFIELD (CpuMWAITX),
> BITFIELD (CpuCLZERO),
> BITFIELD (CpuOSPKE),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index f00babfce2..a409b10ca1 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -219,6 +219,8 @@ enum
> CpuCMPCCXADD,
> /* Intel WRMSRNS Instructions support required */
> CpuWRMSRNS,
> + /* Intel MSRLIST Instructions support required. */
> + CpuMSRLIST,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
> @@ -405,6 +407,7 @@ typedef union i386_cpu_flags
> unsigned int cpuavx_vnni_int8:1;
> unsigned int cpucmpccxadd:1;
> unsigned int cpuwrmsrns:1;
> + unsigned int cpumsrlist:1;
> unsigned int cpumwaitx:1;
> unsigned int cpuclzero:1;
> unsigned int cpuospke:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 3e947cd248..f1d17171c3 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3301,3 +3301,10 @@ cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVV
> wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
>
> // WRMSRNS instruction end.
> +
> +// MSRLIST instructions.
> +
> +rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
> +wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
> +
> +// MSRLIST instructions end.
> --
> 2.18.1
>
OK.
Thanks.
--
H.J.
prev parent reply other threads:[~2022-10-31 16:56 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang
2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang
2022-10-31 16:52 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-31 16:53 ` H.J. Lu
2022-11-02 10:45 ` Jan Beulich
2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang
2022-10-31 16:54 ` H.J. Lu
2022-11-02 10:52 ` Jan Beulich
2022-11-02 16:25 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-31 16:54 ` H.J. Lu
2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang
2022-10-31 16:56 ` H.J. Lu
2022-11-02 10:56 ` Jan Beulich
2022-11-02 14:35 ` Jan Beulich
2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang
2022-10-31 16:55 ` H.J. Lu [this message]
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