From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>, Lili Cui <lili.cui@intel.com>
Subject: Re: [PATCH] x86: correct VMOVSH attributes
Date: Mon, 18 Jul 2022 07:44:46 -0700 [thread overview]
Message-ID: <CAMe9rOpmj7am_ktb2R2i95zVRXWZ700fac2o5=Bkov6oV4UWhg@mail.gmail.com> (raw)
In-Reply-To: <d715bb2b-644f-7049-77d3-b6c7c629b2ab@suse.com>
On Mon, Jul 18, 2022 at 2:23 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.07.2022 19:49, H.J. Lu wrote:
> > On Fri, Jul 15, 2022 at 3:01 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by
> >> suitable means, which would cause #UD). The memory operand form further
> >> was using the wrong Masking value, thus allowing zeroing-masking to be
> >> encoded for the store form (which would again cause #UD).
> >>
> >> --- a/gas/testsuite/gas/i386/evex-wig.s
> >> +++ b/gas/testsuite/gas/i386/evex-wig.s
> >> @@ -62,6 +62,18 @@ _start:
> >> {evex} vpinsrw $0, %eax, %xmm0, %xmm0
> >> {evex} vpinsrw $0, 2(%eax), %xmm0, %xmm0
> >>
> >> + vmovss %xmm0, %xmm0, %xmm0{%k7}
> >> + vmovss (%eax), %xmm0{%k7}
> >> + vmovss %xmm0, (%eax){%k7}
> >> +
> >> + vmovsd %xmm0, %xmm0, %xmm0{%k7}
> >> + vmovsd (%eax), %xmm0{%k7}
> >> + vmovsd %xmm0, (%eax){%k7}
> >> +
> >> + vmovsh %xmm0, %xmm0, %xmm0{%k7}
> >> + vmovsh (%eax), %xmm0{%k7}
> >> + vmovsh %xmm0, (%eax){%k7}
> >> +
> >> vpmovsxbd %xmm5, %zmm6{%k7} # AVX512
> >> vpmovsxbd %xmm5, %zmm6{%k7}{z} # AVX512
> >> vpmovsxbd (%ecx), %zmm6{%k7} # AVX512
> >> --- a/gas/testsuite/gas/i386/evex-wig1-intel.d
> >> +++ b/gas/testsuite/gas/i386/evex-wig1-intel.d
> >> @@ -45,6 +45,15 @@ Disassembly of section .text:
> >> [ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
> >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
> >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss xmm0\{k7\},xmm0,xmm0
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss xmm0\{k7\},DWORD PTR \[eax\]
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss DWORD PTR \[eax\]\{k7\},xmm0
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd xmm0\{k7\},xmm0,xmm0
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd xmm0\{k7\},QWORD PTR \[eax\]
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd QWORD PTR \[eax\]\{k7\},xmm0
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh xmm0\{k7\},xmm0,xmm0
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh xmm0\{k7\},WORD PTR \[eax\]
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh WORD PTR \[eax\]\{k7\},xmm0
> >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
> >> [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5
> >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
> >> --- a/gas/testsuite/gas/i386/evex-wig1.d
> >> +++ b/gas/testsuite/gas/i386/evex-wig1.d
> >> @@ -45,6 +45,15 @@ Disassembly of section .text:
> >> [ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
> >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
> >> [ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss %xmm0,%xmm0,%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss \(%eax\),%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss %xmm0,\(%eax\)\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd %xmm0,%xmm0,%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd \(%eax\),%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd %xmm0,\(%eax\)\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh %xmm0,%xmm0,%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh \(%eax\),%xmm0\{%k7\}
> >> +[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh %xmm0,\(%eax\)\{%k7\}
> >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
> >> [ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
> >> [ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\}
> >> --- a/opcodes/i386-opc.tbl
> >> +++ b/opcodes/i386-opc.tbl
> >> @@ -3684,8 +3684,8 @@ vmaxsh, 0xf35f, None, CpuAVX512_FP16, Mo
> >> vminph, 0x5d, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> >> vminsh, 0xf35d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> >>
> >> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
> >> -vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
> >> +vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|MaskingMorZ|EVexMap5|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
> >> +vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
> >>
> >> vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
> >> vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 }
> >
> > OK.
>
> Thanks. I wonder whether we don't also want this on the 2.39 branch.
>
> Jan
Please backport to 2.39.
Thanks.
--
H.J.
prev parent reply other threads:[~2022-07-18 14:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 10:01 Jan Beulich
2022-07-15 17:49 ` H.J. Lu
2022-07-18 9:23 ` Jan Beulich
2022-07-18 14:44 ` H.J. Lu [this message]
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