* [PATCH] x86: Allow integer conversion without suffix in AT&T syntax
@ 2020-03-03 14:09 H.J. Lu
2020-03-03 14:50 ` Jan Beulich
0 siblings, 1 reply; 7+ messages in thread
From: H.J. Lu @ 2020-03-03 14:09 UTC (permalink / raw)
To: binutils
I am testing this patch with GCC 8. I will check it in if it fixes
regressions in GCC 8 testsuits:
https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
H.J.
---
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
---
gas/testsuite/gas/i386/i386.exp | 2 +
gas/testsuite/gas/i386/noreg64.d | 8 -
gas/testsuite/gas/i386/noreg64.l | 8 -
gas/testsuite/gas/i386/noreg64.s | 8 -
.../gas/i386/x86-64-default-suffix-avx.d | 19 ++
.../gas/i386/x86-64-default-suffix.d | 17 ++
.../gas/i386/x86-64-default-suffix.s | 10 +
opcodes/i386-opc.tbl | 30 ++-
opcodes/i386-tbl.h | 172 +++++++++++++++++-
9 files changed, 230 insertions(+), 44 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-default-suffix-avx.d
create mode 100644 gas/testsuite/gas/i386/x86-64-default-suffix.d
create mode 100644 gas/testsuite/gas/i386/x86-64-default-suffix.s
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 685e62ea72..e78871d591 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -937,6 +937,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx512dq_vl"
run_dump_test "x86-64-suffix"
run_dump_test "x86-64-suffix-intel"
+ run_dump_test "x86-64-default-suffix"
+ run_dump_test "x86-64-default-suffix-avx"
run_dump_test "x86-64-avx512dq-rcigrd-intel"
run_dump_test "x86-64-avx512dq-rcigrd"
run_dump_test "x86-64-avx512dq-rcigrne-intel"
diff --git a/gas/testsuite/gas/i386/noreg64.d b/gas/testsuite/gas/i386/noreg64.d
index e7764f9372..f381c7591a 100644
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -32,8 +32,6 @@ Disassembly of section .text:
*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
*[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%rax\),%eax
*[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax
- *[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
- *[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
*[a-f0-9]+: ff 08 decl \(%rax\)
*[a-f0-9]+: f7 30 divl \(%rax\)
*[a-f0-9]+: d8 00 fadds \(%rax\)
@@ -155,12 +153,6 @@ Disassembly of section .text:
*[a-f0-9]+: f7 00 89 00 00 00 testl \$0x89,\(%rax\)
*[a-f0-9]+: f7 00 34 12 00 00 testl \$0x1234,\(%rax\)
*[a-f0-9]+: f7 00 78 56 34 12 testl \$0x12345678,\(%rax\)
- *[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%rax\),%xmm0,%xmm0
- *[a-f0-9]+: 62 61 7f 08 2a 38 vcvtsi2sdl \(%rax\),%xmm0,%xmm31
- *[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%rax\),%xmm0,%xmm0
- *[a-f0-9]+: 62 61 7e 08 2a 38 vcvtsi2ssl \(%rax\),%xmm0,%xmm31
- *[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%rax\),%xmm0,%xmm0
- *[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%rax\),%xmm0,%xmm0
*[a-f0-9]+: 83 30 01 xorl \$0x1,\(%rax\)
*[a-f0-9]+: 81 30 89 00 00 00 xorl \$0x89,\(%rax\)
*[a-f0-9]+: 81 30 34 12 00 00 xorl \$0x1234,\(%rax\)
diff --git a/gas/testsuite/gas/i386/noreg64.l b/gas/testsuite/gas/i386/noreg64.l
index 29dfe6200f..c4e8b05c59 100644
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -23,8 +23,6 @@
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `crc32'
-.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
-.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
.*:[1-9][0-9]*: Warning: .* `dec'
.*:[1-9][0-9]*: Warning: .* `div'
.*:[1-9][0-9]*: Warning: .* `fadd'
@@ -128,12 +126,6 @@
.*:[1-9][0-9]*: Warning: .* `test'
.*:[1-9][0-9]*: Warning: .* `test'
.*:[1-9][0-9]*: Warning: .* `test'
-.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
-.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
-.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
-.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
-.*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
-.*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
diff --git a/gas/testsuite/gas/i386/noreg64.s b/gas/testsuite/gas/i386/noreg64.s
index ab0b5585f6..1ccb8fd6ab 100644
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -25,8 +25,6 @@ noreg:
cmps %es:(%rdi), (%rsi)
crc32 (%rax), %eax
crc32 (%rax), %rax
- cvtsi2sd (%rax), %xmm0
- cvtsi2ss (%rax), %xmm0
dec (%rax)
div (%rax)
fadd (%rax)
@@ -148,12 +146,6 @@ noreg:
test $0x89, (%rax)
test $0x1234, (%rax)
test $0x12345678, (%rax)
- vcvtsi2sd (%rax), %xmm0, %xmm0
- vcvtsi2sd (%rax), %xmm0, %xmm31
- vcvtsi2ss (%rax), %xmm0, %xmm0
- vcvtsi2ss (%rax), %xmm0, %xmm31
- vcvtusi2sd (%rax), %xmm0, %xmm0
- vcvtusi2ss (%rax), %xmm0, %xmm0
xor $1, (%rax)
xor $0x89, (%rax)
xor $0x1234, (%rax)
diff --git a/gas/testsuite/gas/i386/x86-64-default-suffix-avx.d b/gas/testsuite/gas/i386/x86-64-default-suffix-avx.d
new file mode 100644
index 0000000000..c7a8aff581
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-default-suffix-avx.d
@@ -0,0 +1,19 @@
+#source: x86-64-default-suffix.s
+#as: -msse2avx
+#objdump: -dw
+#name: x86-64 default suffix (AT&T mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+ +[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 61 7f 08 2a 38 vcvtsi2sdl \(%rax\),%xmm0,%xmm31
+ +[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 61 7e 08 2a 38 vcvtsi2ssl \(%rax\),%xmm0,%xmm31
+ +[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%rax\),%xmm0,%xmm0
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-default-suffix.d b/gas/testsuite/gas/i386/x86-64-default-suffix.d
new file mode 100644
index 0000000000..8258dad11d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-default-suffix.d
@@ -0,0 +1,17 @@
+#objdump: -dw
+#name: x86-64 default suffix (AT&T mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+ +[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
+ +[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
+ +[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 61 7f 08 2a 38 vcvtsi2sdl \(%rax\),%xmm0,%xmm31
+ +[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 61 7e 08 2a 38 vcvtsi2ssl \(%rax\),%xmm0,%xmm31
+ +[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%rax\),%xmm0,%xmm0
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-default-suffix.s b/gas/testsuite/gas/i386/x86-64-default-suffix.s
new file mode 100644
index 0000000000..c949748530
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-default-suffix.s
@@ -0,0 +1,10 @@
+ .text
+foo:
+ cvtsi2sd (%rax), %xmm0
+ cvtsi2ss (%rax), %xmm0
+ vcvtsi2sd (%rax), %xmm0, %xmm0
+ vcvtsi2sd (%rax), %xmm0, %xmm31
+ vcvtsi2ss (%rax), %xmm0, %xmm0
+ vcvtsi2ss (%rax), %xmm0, %xmm31
+ vcvtusi2sd (%rax), %xmm0, %xmm0
+ vcvtusi2ss (%rax), %xmm0, %xmm0
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 13933c9e4c..69b9cf5235 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1253,9 +1253,11 @@ comiss, 2, 0xf2f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
cvtpi2ps, 2, 0xf2a, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM }
cvtps2pi, 2, 0xf2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX }
cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
cvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX }
@@ -1434,9 +1436,11 @@ comisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No
comisd, 2, 0x660f2f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
cvtpi2pd, 2, 0x660f2a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM }
cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
+cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
divpd, 2, 0x665e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
divpd, 2, 0x660f5e, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
divsd, 2, 0xf25e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2027,8 +2031,10 @@ vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_
vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vcvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
vcvtsd2ss, 3, 0xf25a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX, Modrm|VexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtss2sd, 3, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
@@ -3470,17 +3476,21 @@ vcvtsd2usi, 3, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|No_bSuf|No_
vcvtsd2ss, 3, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
-vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
-vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
-vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
-vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|VexOpcode=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e8fafbe575..700d64e751 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -12160,6 +12160,20 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "cvtsi2ss", 0xf32a, None, 1, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "cvtsi2ss", 0xf32a, None, 1, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
@@ -12169,7 +12183,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -12188,6 +12202,20 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "cvtsi2ss", 0xf30f2a, None, 2, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "cvtsi2ss", 0xf30f2a, None, 2, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -12197,7 +12225,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -14658,6 +14686,20 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "cvtsi2sd", 0xf22a, None, 1, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "cvtsi2sd", 0xf22a, None, 1, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
@@ -14667,7 +14709,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -14686,6 +14728,20 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "cvtsi2sd", 0xf20f2a, None, 2, 2,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "cvtsi2sd", 0xf20f2a, None, 2, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -14695,7 +14751,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -28006,6 +28062,22 @@ const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "vcvtsi2sd", 0xf22a, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "vcvtsi2sd", 0xf22a, None, 1, 3,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
@@ -28015,7 +28087,23 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
+ { "vcvtsi2sd", 0xF22A, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -28031,7 +28119,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -28074,6 +28162,22 @@ const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "vcvtsi2ss", 0xf32a, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "vcvtsi2ss", 0xf32a, None, 1, 3,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
@@ -28083,7 +28187,23 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
+ { "vcvtsi2ss", 0xF32A, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -28099,7 +28219,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -50546,6 +50666,22 @@ const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
0, 0, 0, 0, 0, 0 } } } },
+ { "vcvtusi2sd", 0xF27B, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "vcvtusi2sd", 0xF27B, None, 1, 3,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -50555,7 +50691,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -50598,6 +50734,22 @@ const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
+ { "vcvtusi2ss", 0xF37B, None, 1, 3,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+ 0, 0, 0, 0, 1, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } },
+ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0 } } } },
{ "vcvtusi2ss", 0xF37B, None, 1, 3,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -50607,7 +50759,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--
2.24.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86: Allow integer conversion without suffix in AT&T syntax
2020-03-03 14:09 [PATCH] x86: Allow integer conversion without suffix in AT&T syntax H.J. Lu
@ 2020-03-03 14:50 ` Jan Beulich
2020-03-03 17:15 ` [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize H.J. Lu
0 siblings, 1 reply; 7+ messages in thread
From: Jan Beulich @ 2020-03-03 14:50 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 03.03.2020 15:09, H.J. Lu wrote:
> I am testing this patch with GCC 8. I will check it in if it fixes
> regressions in GCC 8 testsuits:
>
> https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
>
> H.J.
> ---
> According to gas manual, suffix in instruction mnemonics isn't always
> required:
>
> When there is no sizing suffix and no (suitable) register operands to
> deduce the size of memory operands, with a few exceptions and where long
> operand size is possible in the first place, operand size will default
> to long in 32- and 64-bit modes.
Nothing there says that this defaulting is to happen silently. Yet
_that's_ what my earlier changes altered. The defaulting is still
the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
pointed out by the assembler. (There may be [and there is] a mode
in which this goes silently, to be enabled at the programmer's
risk.)
> This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
> vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
> must be allowed without suffix in AT&T syntax.
>
> gas/
>
> PR gas/25622
> * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
> x86-64-default-suffix-avx.
> * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
> vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
> * testsuite/gas/i386/noreg64.d: Updated.
> * testsuite/gas/i386/noreg64.l: Likewise.
> * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
> * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
> * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
>
> opcodes/
>
> PR gas/25622
> * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
> vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
Oh no. I'm trying to clean up the IgnoreSize mess and you want to
add new instances for no good reason (yes, there are cases where
this is actually missing; hopefully I'll get to send out the
series later this week).
I know I can't prevent this going in, but I'm heavily opposed.
You don't "fix" anything here, you break things.
Jan
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize
2020-03-03 14:50 ` Jan Beulich
@ 2020-03-03 17:15 ` H.J. Lu
2020-03-03 17:26 ` Jan Beulich
0 siblings, 1 reply; 7+ messages in thread
From: H.J. Lu @ 2020-03-03 17:15 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
[-- Attachment #1: Type: text/plain, Size: 2704 bytes --]
On Tue, Mar 3, 2020 at 6:50 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 03.03.2020 15:09, H.J. Lu wrote:
> > I am testing this patch with GCC 8. I will check it in if it fixes
> > regressions in GCC 8 testsuits:
> >
> > https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
> >
> > H.J.
> > ---
> > According to gas manual, suffix in instruction mnemonics isn't always
> > required:
> >
> > When there is no sizing suffix and no (suitable) register operands to
> > deduce the size of memory operands, with a few exceptions and where long
> > operand size is possible in the first place, operand size will default
> > to long in 32- and 64-bit modes.
>
> Nothing there says that this defaulting is to happen silently. Yet
> _that's_ what my earlier changes altered. The defaulting is still
> the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
> nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
> pointed out by the assembler. (There may be [and there is] a mode
> in which this goes silently, to be enabled at the programmer's
> risk.)
It is not going to happen in AT&T syntax. Gas has to support older GCC
without any warnings.
> > This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
> > vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
> > must be allowed without suffix in AT&T syntax.
> >
> > gas/
> >
> > PR gas/25622
> > * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
> > x86-64-default-suffix-avx.
> > * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
> > vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
> > * testsuite/gas/i386/noreg64.d: Updated.
> > * testsuite/gas/i386/noreg64.l: Likewise.
> > * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
> > * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
> > * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
> >
> > opcodes/
> >
> > PR gas/25622
> > * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
> > vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
>
> Oh no. I'm trying to clean up the IgnoreSize mess and you want to
> add new instances for no good reason (yes, there are cases where
> this is actually missing; hopefully I'll get to send out the
> series later this week).
Since an instruction template can't have both IgnoreSize and DefaultSize,
I am testing this patch and will check it if there are no regressions. Then
we can add one value to MnemonicSize.
> I know I can't prevent this going in, but I'm heavily opposed.
> You don't "fix" anything here, you break things.
>
I disagree.
--
H.J.
[-- Attachment #2: 0001-Replace-IgnoreSize-DefaultSize-with-MnemonicSize.patch --]
[-- Type: application/x-patch, Size: 6615 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize
2020-03-03 17:15 ` [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize H.J. Lu
@ 2020-03-03 17:26 ` Jan Beulich
2020-03-03 19:32 ` H.J. Lu
0 siblings, 1 reply; 7+ messages in thread
From: Jan Beulich @ 2020-03-03 17:26 UTC (permalink / raw)
To: H.J. Lu; +Cc: Binutils
On 03.03.2020 18:15, H.J. Lu wrote:
> On Tue, Mar 3, 2020 at 6:50 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 03.03.2020 15:09, H.J. Lu wrote:
>>> I am testing this patch with GCC 8. I will check it in if it fixes
>>> regressions in GCC 8 testsuits:
>>>
>>> https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
>>>
>>> H.J.
>>> ---
>>> According to gas manual, suffix in instruction mnemonics isn't always
>>> required:
>>>
>>> When there is no sizing suffix and no (suitable) register operands to
>>> deduce the size of memory operands, with a few exceptions and where long
>>> operand size is possible in the first place, operand size will default
>>> to long in 32- and 64-bit modes.
>>
>> Nothing there says that this defaulting is to happen silently. Yet
>> _that's_ what my earlier changes altered. The defaulting is still
>> the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
>> nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
>> pointed out by the assembler. (There may be [and there is] a mode
>> in which this goes silently, to be enabled at the programmer's
>> risk.)
>
> It is not going to happen in AT&T syntax. Gas has to support older GCC
> without any warnings.
Why? What's wrong with pointing out issues even with compiler
generated code? In fact iirc gcc used to be buggy in regard of
these conversion instructions, and the assembler change helped
spot this.
>>> This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
>>> vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
>>> must be allowed without suffix in AT&T syntax.
>>>
>>> gas/
>>>
>>> PR gas/25622
>>> * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
>>> x86-64-default-suffix-avx.
>>> * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
>>> vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
>>> * testsuite/gas/i386/noreg64.d: Updated.
>>> * testsuite/gas/i386/noreg64.l: Likewise.
>>> * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
>>> * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
>>> * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
>>>
>>> opcodes/
>>>
>>> PR gas/25622
>>> * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
>>> vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
>>
>> Oh no. I'm trying to clean up the IgnoreSize mess and you want to
>> add new instances for no good reason (yes, there are cases where
>> this is actually missing; hopefully I'll get to send out the
>> series later this week).
>
> Since an instruction template can't have both IgnoreSize and DefaultSize,
> I am testing this patch and will check it if there are no regressions. Then
> we can add one value to MnemonicSize.
It seems pretty unrelated here, but is a good change to make,
I think.
>> I know I can't prevent this going in, but I'm heavily opposed.
>> You don't "fix" anything here, you break things.
>
> I disagree.
It's pretty sad that in binutils consensus isn't required for
changes to go in. I'll enter a bug in due course in any event.
Jan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize
2020-03-03 17:26 ` Jan Beulich
@ 2020-03-03 19:32 ` H.J. Lu
2020-03-04 16:24 ` Jan Beulich
0 siblings, 1 reply; 7+ messages in thread
From: H.J. Lu @ 2020-03-03 19:32 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Tue, Mar 3, 2020 at 9:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 03.03.2020 18:15, H.J. Lu wrote:
> > On Tue, Mar 3, 2020 at 6:50 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 03.03.2020 15:09, H.J. Lu wrote:
> >>> I am testing this patch with GCC 8. I will check it in if it fixes
> >>> regressions in GCC 8 testsuits:
> >>>
> >>> https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
> >>>
> >>> H.J.
> >>> ---
> >>> According to gas manual, suffix in instruction mnemonics isn't always
> >>> required:
> >>>
> >>> When there is no sizing suffix and no (suitable) register operands to
> >>> deduce the size of memory operands, with a few exceptions and where long
> >>> operand size is possible in the first place, operand size will default
> >>> to long in 32- and 64-bit modes.
> >>
> >> Nothing there says that this defaulting is to happen silently. Yet
> >> _that's_ what my earlier changes altered. The defaulting is still
> >> the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
> >> nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
> >> pointed out by the assembler. (There may be [and there is] a mode
> >> in which this goes silently, to be enabled at the programmer's
> >> risk.)
> >
> > It is not going to happen in AT&T syntax. Gas has to support older GCC
> > without any warnings.
>
> Why? What's wrong with pointing out issues even with compiler
> generated code? In fact iirc gcc used to be buggy in regard of
> these conversion instructions, and the assembler change helped
> spot this.
I appreciate your intention. But the primary goal of gas is to serve GCC.
In this case, there are ino issues with integer conversion in GCC 8 and we
have to support existing GCC 8. Issue a warning in AT&T syntax is not
really an option here.
> >>> This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
> >>> vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
> >>> must be allowed without suffix in AT&T syntax.
> >>>
> >>> gas/
> >>>
> >>> PR gas/25622
> >>> * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
> >>> x86-64-default-suffix-avx.
> >>> * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
> >>> vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
> >>> * testsuite/gas/i386/noreg64.d: Updated.
> >>> * testsuite/gas/i386/noreg64.l: Likewise.
> >>> * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
> >>> * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
> >>> * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
> >>>
> >>> opcodes/
> >>>
> >>> PR gas/25622
> >>> * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
> >>> vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
> >>
> >> Oh no. I'm trying to clean up the IgnoreSize mess and you want to
> >> add new instances for no good reason (yes, there are cases where
> >> this is actually missing; hopefully I'll get to send out the
> >> series later this week).
> >
> > Since an instruction template can't have both IgnoreSize and DefaultSize,
> > I am testing this patch and will check it if there are no regressions. Then
> > we can add one value to MnemonicSize.
>
> It seems pretty unrelated here, but is a good change to make,
> I think.
I checked in in. Please feel free to replace IgnoreSize on integer conversions
with a new value.
> >> I know I can't prevent this going in, but I'm heavily opposed.
> >> You don't "fix" anything here, you break things.
> >
> > I disagree.
>
> It's pretty sad that in binutils consensus isn't required for
> changes to go in. I'll enter a bug in due course in any event.
>
> Jan
--
H.J.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize
2020-03-03 19:32 ` H.J. Lu
@ 2020-03-04 16:24 ` Jan Beulich
2020-03-04 17:49 ` H.J. Lu
0 siblings, 1 reply; 7+ messages in thread
From: Jan Beulich @ 2020-03-04 16:24 UTC (permalink / raw)
To: H.J. Lu; +Cc: Binutils
On 03.03.2020 20:31, H.J. Lu wrote:
> On Tue, Mar 3, 2020 at 9:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 03.03.2020 18:15, H.J. Lu wrote:
>>> On Tue, Mar 3, 2020 at 6:50 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 03.03.2020 15:09, H.J. Lu wrote:
>>>>> I am testing this patch with GCC 8. I will check it in if it fixes
>>>>> regressions in GCC 8 testsuits:
>>>>>
>>>>> https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
>>>>>
>>>>> H.J.
>>>>> ---
>>>>> According to gas manual, suffix in instruction mnemonics isn't always
>>>>> required:
>>>>>
>>>>> When there is no sizing suffix and no (suitable) register operands to
>>>>> deduce the size of memory operands, with a few exceptions and where long
>>>>> operand size is possible in the first place, operand size will default
>>>>> to long in 32- and 64-bit modes.
>>>>
>>>> Nothing there says that this defaulting is to happen silently. Yet
>>>> _that's_ what my earlier changes altered. The defaulting is still
>>>> the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
>>>> nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
>>>> pointed out by the assembler. (There may be [and there is] a mode
>>>> in which this goes silently, to be enabled at the programmer's
>>>> risk.)
>>>
>>> It is not going to happen in AT&T syntax. Gas has to support older GCC
>>> without any warnings.
>>
>> Why? What's wrong with pointing out issues even with compiler
>> generated code? In fact iirc gcc used to be buggy in regard of
>> these conversion instructions, and the assembler change helped
>> spot this.
>
> I appreciate your intention. But the primary goal of gas is to serve GCC.
> In this case, there are ino issues with integer conversion in GCC 8 and we
> have to support existing GCC 8. Issue a warning in AT&T syntax is not
> really an option here.
The initial release of gcc 8 was still buggy, and you can then
extrapolate this to older versions. If code is to be compiled
warning-free with older releases, gcc should get respective
backports. Hiding actual bugs (because of gcc shortcomings) is
not really an option here (to use your wording).
Furthermore - if you were to discover more problems with even
older gcc versions, would you then "declare" all those insns
as exceptions too? Such an approach doesn't make any sense to
me.
>>>>> This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
>>>>> vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
>>>>> must be allowed without suffix in AT&T syntax.
>>>>>
>>>>> gas/
>>>>>
>>>>> PR gas/25622
>>>>> * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
>>>>> x86-64-default-suffix-avx.
>>>>> * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
>>>>> vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
>>>>> * testsuite/gas/i386/noreg64.d: Updated.
>>>>> * testsuite/gas/i386/noreg64.l: Likewise.
>>>>> * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
>>>>> * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
>>>>> * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
>>>>>
>>>>> opcodes/
>>>>>
>>>>> PR gas/25622
>>>>> * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
>>>>> vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
>>>>
>>>> Oh no. I'm trying to clean up the IgnoreSize mess and you want to
>>>> add new instances for no good reason (yes, there are cases where
>>>> this is actually missing; hopefully I'll get to send out the
>>>> series later this week).
>>>
>>> Since an instruction template can't have both IgnoreSize and DefaultSize,
>>> I am testing this patch and will check it if there are no regressions. Then
>>> we can add one value to MnemonicSize.
>>
>> It seems pretty unrelated here, but is a good change to make,
>> I think.
>
> I checked in in. Please feel free to replace IgnoreSize on integer conversions
> with a new value.
As per the series sent earlier today - we're not quite there yet.
Jan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize
2020-03-04 16:24 ` Jan Beulich
@ 2020-03-04 17:49 ` H.J. Lu
0 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-03-04 17:49 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Wed, Mar 4, 2020 at 8:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 03.03.2020 20:31, H.J. Lu wrote:
> > On Tue, Mar 3, 2020 at 9:26 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 03.03.2020 18:15, H.J. Lu wrote:
> >>> On Tue, Mar 3, 2020 at 6:50 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 03.03.2020 15:09, H.J. Lu wrote:
> >>>>> I am testing this patch with GCC 8. I will check it in if it fixes
> >>>>> regressions in GCC 8 testsuits:
> >>>>>
> >>>>> https://gcc.gnu.org/ml/gcc-regression/2020-03/msg00008.html
> >>>>>
> >>>>> H.J.
> >>>>> ---
> >>>>> According to gas manual, suffix in instruction mnemonics isn't always
> >>>>> required:
> >>>>>
> >>>>> When there is no sizing suffix and no (suitable) register operands to
> >>>>> deduce the size of memory operands, with a few exceptions and where long
> >>>>> operand size is possible in the first place, operand size will default
> >>>>> to long in 32- and 64-bit modes.
> >>>>
> >>>> Nothing there says that this defaulting is to happen silently. Yet
> >>>> _that's_ what my earlier changes altered. The defaulting is still
> >>>> the same. And no - SUCH CASES SHOULD NOT GO SILENTLY, neither here
> >>>> nor in the MOVSX/MOVZX case. Ambiguities should _always_ be
> >>>> pointed out by the assembler. (There may be [and there is] a mode
> >>>> in which this goes silently, to be enabled at the programmer's
> >>>> risk.)
> >>>
> >>> It is not going to happen in AT&T syntax. Gas has to support older GCC
> >>> without any warnings.
> >>
> >> Why? What's wrong with pointing out issues even with compiler
> >> generated code? In fact iirc gcc used to be buggy in regard of
> >> these conversion instructions, and the assembler change helped
> >> spot this.
> >
> > I appreciate your intention. But the primary goal of gas is to serve GCC.
> > In this case, there are ino issues with integer conversion in GCC 8 and we
> > have to support existing GCC 8. Issue a warning in AT&T syntax is not
> > really an option here.
>
> The initial release of gcc 8 was still buggy, and you can then
> extrapolate this to older versions. If code is to be compiled
> warning-free with older releases, gcc should get respective
> backports. Hiding actual bugs (because of gcc shortcomings) is
> not really an option here (to use your wording).
I am testing GCC 8.4 release and there are no integer conversion
bugs.
> Furthermore - if you were to discover more problems with even
> older gcc versions, would you then "declare" all those insns
> as exceptions too? Such an approach doesn't make any sense to
> me.
>
If you find a GCC codegen bug, please open a GCC bug and I will
fix it.
--
H.J.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-03-04 17:49 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-03 14:09 [PATCH] x86: Allow integer conversion without suffix in AT&T syntax H.J. Lu
2020-03-03 14:50 ` Jan Beulich
2020-03-03 17:15 ` [PATCH] Replace IgnoreSize/DefaultSize with MnemonicSize H.J. Lu
2020-03-03 17:26 ` Jan Beulich
2020-03-03 19:32 ` H.J. Lu
2020-03-04 16:24 ` Jan Beulich
2020-03-04 17:49 ` H.J. Lu
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