* [PATCH] x86/Intel: improve diagnostics for ambiguous VCVT* operands
@ 2020-02-14 12:56 Jan Beulich
2020-02-14 13:00 ` H.J. Lu
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2020-02-14 12:56 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.
For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
gas/
2020-02-XX Jan Beulich <jbeulich@suse.com>
PR gas/6518
* config/tc-i386.c (process_suffix): Re-work Intel-syntax
[XYZ]MMWord memory operand ambiguity recognition logic (largely
re-indentation).
* testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps
cases.
* testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16.
* testsuite/gas/i386/avx512dq-inval.l,
testsuite/gas/i386/inval-avx.l,
testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
* testsuite/gas/i386/avx512vl-ambig.s,
testsuite/gas/i386/avx512vl-ambig.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
opcodes/
2020-02-XX Jan Beulich <jbeulich@suse.com>
PR gas/6518
* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
into Intel syntax instance (with Unpsecified) and AT&T one
(without).
(vcvtneps2bf16): Likewise, along with folding the two so far
separate ones.
* i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6466,53 +6466,50 @@ process_suffix (void)
/* For [XYZ]MMWORD operands inspect operand sizes. While generally
also suitable for AT&T syntax mode, it was requested that this be
restricted to just Intel syntax. */
- if (intel_syntax)
+ if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast)
{
- i386_cpu_flags cpu = cpu_flags_and (i.tm.cpu_flags, avx512);
+ unsigned int op;
- if (!cpu_flags_all_zero (&cpu) && !i.broadcast)
+ for (op = 0; op < i.tm.operands; ++op)
{
- unsigned int op;
-
- for (op = 0; op < i.tm.operands; ++op)
+ if (is_evex_encoding (&i.tm)
+ && !cpu_arch_flags.bitfield.cpuavx512vl)
{
- if (!cpu_arch_flags.bitfield.cpuavx512vl)
- {
- if (i.tm.operand_types[op].bitfield.ymmword)
- i.tm.operand_types[op].bitfield.xmmword = 0;
- if (i.tm.operand_types[op].bitfield.zmmword)
- i.tm.operand_types[op].bitfield.ymmword = 0;
- if (!i.tm.opcode_modifier.evex
- || i.tm.opcode_modifier.evex == EVEXDYN)
- i.tm.opcode_modifier.evex = EVEX512;
- }
+ if (i.tm.operand_types[op].bitfield.ymmword)
+ i.tm.operand_types[op].bitfield.xmmword = 0;
+ if (i.tm.operand_types[op].bitfield.zmmword)
+ i.tm.operand_types[op].bitfield.ymmword = 0;
+ if (!i.tm.opcode_modifier.evex
+ || i.tm.opcode_modifier.evex == EVEXDYN)
+ i.tm.opcode_modifier.evex = EVEX512;
+ }
- if (i.tm.operand_types[op].bitfield.xmmword
- + i.tm.operand_types[op].bitfield.ymmword
- + i.tm.operand_types[op].bitfield.zmmword < 2)
- continue;
+ if (i.tm.operand_types[op].bitfield.xmmword
+ + i.tm.operand_types[op].bitfield.ymmword
+ + i.tm.operand_types[op].bitfield.zmmword < 2)
+ continue;
- /* Any properly sized operand disambiguates the insn. */
- if (i.types[op].bitfield.xmmword
- || i.types[op].bitfield.ymmword
- || i.types[op].bitfield.zmmword)
- {
- suffixes &= ~(7 << 6);
- evex = 0;
- break;
- }
+ /* Any properly sized operand disambiguates the insn. */
+ if (i.types[op].bitfield.xmmword
+ || i.types[op].bitfield.ymmword
+ || i.types[op].bitfield.zmmword)
+ {
+ suffixes &= ~(7 << 6);
+ evex = 0;
+ break;
+ }
- if ((i.flags[op] & Operand_Mem)
- && i.tm.operand_types[op].bitfield.unspecified)
- {
- if (i.tm.operand_types[op].bitfield.xmmword)
- suffixes |= 1 << 6;
- if (i.tm.operand_types[op].bitfield.ymmword)
- suffixes |= 1 << 7;
- if (i.tm.operand_types[op].bitfield.zmmword)
- suffixes |= 1 << 8;
- evex = EVEX512;
- }
+ if ((i.flags[op] & Operand_Mem)
+ && i.tm.operand_types[op].bitfield.unspecified)
+ {
+ if (i.tm.operand_types[op].bitfield.xmmword)
+ suffixes |= 1 << 6;
+ if (i.tm.operand_types[op].bitfield.ymmword)
+ suffixes |= 1 << 7;
+ if (i.tm.operand_types[op].bitfield.zmmword)
+ suffixes |= 1 << 8;
+ if (is_evex_encoding (&i.tm))
+ evex = EVEX512;
}
}
}
--- a/gas/testsuite/gas/i386/avx512dq-inval.l
+++ b/gas/testsuite/gas/i386/avx512dq-inval.l
@@ -11,7 +11,11 @@
.*:[0-9]*: Error:.* `vpinsrq' .*
.*:[0-9]*: Error:.* `vpinsrq' .*
.*:[0-9]*: Error:.* `vpinsrq' .*
-.*:[0-9]*: Error:.* `vfpclasspd'
-.*:[0-9]*: Error:.* `vfpclassps'
+.*:[0-9]*: Error:.* ambiguous .* `vcvtqq2ps'
+.*:[0-9]*: Error:.* ambiguous .* `vcvtuqq2ps'
+.*:[0-9]*: Error:.* ambiguous .* `vfpclasspd'
+.*:[0-9]*: Error:.* ambiguous .* `vfpclassps'
+.*:[0-9]*: Error:.* `vcvtqq2ps'
+.*:[0-9]*: Error:.* `vcvtuqq2ps'
.*:[0-9]*: Error:.* `vfpclasspd'
.*:[0-9]*: Error:.* `vfpclassps'
--- a/gas/testsuite/gas/i386/avx512dq-inval.s
+++ b/gas/testsuite/gas/i386/avx512dq-inval.s
@@ -20,10 +20,16 @@ _start:
vpinsrq xmm0, xmm0, qword ptr [eax], 0
{evex} vpinsrq xmm0, xmm0, qword ptr [eax], 0
+ vcvtqq2ps xmm0, [rax]
+ vcvtuqq2ps xmm0, [rax]
+
vfpclasspd k0, [eax], 0
vfpclassps k0, [eax], 0
.att_syntax prefix
+ vcvtqq2ps (%eax), %xmm0
+ vcvtuqq2ps (%eax), %xmm0
+
vfpclasspd $0, (%eax), %k0
vfpclassps $0, (%eax), %k0
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl-ambig.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:[0-9]*: Error:.* ambiguous .* `vcvtneps2bf16'
+.*:[0-9]*: Error:.* ambiguous .* `vcvtpd2dq'
+.*:[0-9]*: Error:.* ambiguous .* `vcvtpd2ps'
+.*:[0-9]*: Error:.* ambiguous .* `vcvtpd2udq'
+.*:[0-9]*: Error:.* ambiguous .* `vcvttpd2dq'
+.*:[0-9]*: Error:.* ambiguous .* `vcvttpd2udq'
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl-ambig.s
@@ -0,0 +1,11 @@
+# Check AVX512VL instructions with ambiguous operands
+
+ .text
+ .intel_syntax noprefix
+_start:
+ vcvtneps2bf16 xmm0, [ecx]
+ vcvtpd2dq xmm0{k1}, [ecx]
+ vcvtpd2ps xmm0{k1}, [ecx]
+ vcvtpd2udq xmm0, [ecx]
+ vcvttpd2dq xmm0{k1}, [ecx]
+ vcvttpd2udq xmm0, [ecx]
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -478,6 +478,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_list_test "vp2intersect-inval-bcast"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
+ run_list_test "avx512vl-ambig"
run_list_test "avx512vl-plain" "-al"
run_dump_test "fpu-bad"
run_dump_test "cet"
--- a/gas/testsuite/gas/i386/inval-avx.l
+++ b/gas/testsuite/gas/i386/inval-avx.l
@@ -2,9 +2,9 @@
.*:4: Error: .*
.*:5: Error: .*
.*:6: Error: .*
-.*:9: Error: .*
-.*:10: Error: .*
-.*:11: Error: .*
+.*:9: Error:.* ambiguous .* `vcvtpd2dq'
+.*:10: Error:.* ambiguous .* `vcvtpd2ps'
+.*:11: Error:.* ambiguous .* `vcvttpd2dq'
GAS LISTING .*
--- a/gas/testsuite/gas/i386/inval-avx512f.l
+++ b/gas/testsuite/gas/i386/inval-avx512f.l
@@ -213,6 +213,11 @@
.*:306: Error: .*masking.*vscatterpf1qps.*
.*:308: Error: .*unsupported broadcast for `vdpbf16ps'
.*:309: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
+.*:311: Error: .*unsupported broadcast for `vcvtneps2bf16'
+.*:312: Error: .*unsupported broadcast for `vcvtneps2bf16'
+.*:313: Error: .*unsupported broadcast for `vcvtneps2bf16'
+.*:316: Error: .*unsupported broadcast for `vcvtneps2bf16'
+.*:319: Error: .*unsupported broadcast for `vcvtneps2bf16'
GAS LISTING .*
@@ -551,3 +556,16 @@ GAS LISTING .*
[ ]*307[ ]*
[ ]*308[ ]+vdpbf16ps 8\(%eax\)\{1to8\}, %zmm2, %zmm2
[ ]*309[ ]+vcvtne2ps2bf16 8\(%eax\)\{1to8\}, %zmm2, %zmm2
+[ ]*310[ ]*
+[ ]*311[ ]+vcvtneps2bf16 \(%eax\)\{1to2\}, %ymm1
+[ ]*312[ ]+vcvtneps2bf16 \(%eax\)\{1to4\}, %ymm1
+[ ]*313[ ]+vcvtneps2bf16 \(%eax\)\{1to8\}, %ymm1
+[ ]*314 \?\?\?\? 62F27E58[ ]+vcvtneps2bf16 \(%eax\)\{1to16\}, %ymm1
+[ ]*314[ ]+7208
+[ ]*315[ ]*
+[ ]*316[ ]+vcvtneps2bf16 \(%eax\)\{1to2\}, %xmm1
+[ ]*317 \?\?\?\? 62F27E18[ ]+vcvtneps2bf16 \(%eax\)\{1to4\}, %xmm1
+[ ]*317[ ]+7208
+[ ]*318 \?\?\?\? 62F27E38[ ]+vcvtneps2bf16 \(%eax\)\{1to8\}, %xmm1
+[ ]*318[ ]+7208
+[ ]*319[ ]+vcvtneps2bf16 \(%eax\)\{1to16\}, %xmm1
--- a/gas/testsuite/gas/i386/inval-avx512f.s
+++ b/gas/testsuite/gas/i386/inval-avx512f.s
@@ -307,3 +307,13 @@ _start:
vdpbf16ps 8(%eax){1to8}, %zmm2, %zmm2
vcvtne2ps2bf16 8(%eax){1to8}, %zmm2, %zmm2
+
+ vcvtneps2bf16 (%eax){1to2}, %ymm1
+ vcvtneps2bf16 (%eax){1to4}, %ymm1
+ vcvtneps2bf16 (%eax){1to8}, %ymm1
+ vcvtneps2bf16 (%eax){1to16}, %ymm1
+
+ vcvtneps2bf16 (%eax){1to2}, %xmm1
+ vcvtneps2bf16 (%eax){1to4}, %xmm1
+ vcvtneps2bf16 (%eax){1to8}, %xmm1
+ vcvtneps2bf16 (%eax){1to16}, %xmm1
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2013,10 +2013,12 @@ vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, M
vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|BaseIndex, RegXMM }
+vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
+vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
-vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|BaseIndex, RegXMM }
+vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
+vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2031,7 +2033,8 @@ vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX|Cp
vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtss2sd, 3, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
-vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|BaseIndex, RegXMM }
+vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
+vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
vcvttpd2dqx, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
vcvttpd2dqy, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
@@ -4103,14 +4106,18 @@ vcvtudq2pd, 2, 0xF37A, None, 1, CpuAVX51
vcvtudq2pd, 2, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex, RegXMM }
vcvtudq2pd, 2, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|XMMword|Unspecified|BaseIndex, RegYMM }
-vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvtpd2dqx, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvtpd2dqy, 2, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+
+vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvtpd2psx, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvtpd2psy, 2, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvtpd2udqx, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvtpd2udqy, 2, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
@@ -4125,11 +4132,13 @@ vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex }
vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, XMMword|Unspecified|BaseIndex }
-vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|Qword|BaseIndex, RegXMM }
+vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvttpd2dqx, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvttpd2dqy, 2, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvttpd2udqx, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvttpd2udqy, 2, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
@@ -4464,7 +4473,8 @@ vcvtuqq2pd, 3, 0xF37A, None, 1, CpuAVX51
vcvtqq2ps, 2, 0x5B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
vcvtqq2ps, 3, 0x5B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
-vcvtqq2ps, 2, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvtqq2ps, 2, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtqq2ps, 2, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvtqq2psx, 2, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvtqq2psy, 2, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
@@ -4486,7 +4496,8 @@ vcvttps2uqq, 3, 0x6678, None, 1, CpuAVX5
vcvtuqq2ps, 2, 0xF27A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
vcvtuqq2ps, 3, 0xF27A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
-vcvtuqq2ps, 2, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
+vcvtuqq2ps, 2, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtuqq2ps, 2, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
vcvtuqq2psx, 2, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vcvtuqq2psy, 2, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
@@ -4775,10 +4786,9 @@ movdir64b, 2, 0x660f38f8, None, 3, CpuMO
vcvtne2ps2bf16, 3, 0xf272, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|BaseIndex, RegXMM }
-vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|BaseIndex, RegXMM }
vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|EVex512|Masking=3|VexW0|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegYMM }
-
+vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM }
vcvtneps2bf16x, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
vcvtneps2bf16y, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] x86/Intel: improve diagnostics for ambiguous VCVT* operands
2020-02-14 12:56 [PATCH] x86/Intel: improve diagnostics for ambiguous VCVT* operands Jan Beulich
@ 2020-02-14 13:00 ` H.J. Lu
0 siblings, 0 replies; 2+ messages in thread
From: H.J. Lu @ 2020-02-14 13:00 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Feb 14, 2020 at 4:56 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Conversions which shrink element size and which have a memory source
> can't be disambiguated between their 128- and 256-bit variants by
> looking at the register operand. "operand size mismatch", however, is a
> pretty misleading diagnostic. Generalize the logic introduced for
> VFPCLASSP{S,D} such that, with suitable similar adjustments to the
> respective templates, it'll cover these cases too.
>
> For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
> templates to achieve the intended effect. This is then also accompanied
> by a respective addition to the inval-avx512f testcase.
>
> gas/
> 2020-02-XX Jan Beulich <jbeulich@suse.com>
>
> PR gas/6518
> * config/tc-i386.c (process_suffix): Re-work Intel-syntax
> [XYZ]MMWord memory operand ambiguity recognition logic (largely
> re-indentation).
> * testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps
> cases.
> * testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16.
> * testsuite/gas/i386/avx512dq-inval.l,
> testsuite/gas/i386/inval-avx.l,
> testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
> * testsuite/gas/i386/avx512vl-ambig.s,
> testsuite/gas/i386/avx512vl-ambig.l: New.
> * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2020-02-XX Jan Beulich <jbeulich@suse.com>
>
> PR gas/6518
> * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
> vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
> into Intel syntax instance (with Unpsecified) and AT&T one
> (without).
> (vcvtneps2bf16): Likewise, along with folding the two so far
> separate ones.
> * i386-tbl.h: Re-generate.
>
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2020-02-14 12:56 [PATCH] x86/Intel: improve diagnostics for ambiguous VCVT* operands Jan Beulich
2020-02-14 13:00 ` H.J. Lu
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