From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH] x86: Warn .insn instruction with length > 15 bytes
Date: Tue, 6 Feb 2024 04:26:00 -0800 [thread overview]
Message-ID: <CAMe9rOqjmMuwSFg0t9yPG8Y6vzvLbVSc00a+ekRj6wnoafQ9Yw@mail.gmail.com> (raw)
In-Reply-To: <a4f2da2d-6fde-4edd-8fff-5ca63d014f8b@suse.com>
On Tue, Feb 6, 2024 at 3:41 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 06.02.2024 12:36, H.J. Lu wrote:
> > On Tue, Feb 6, 2024 at 12:19 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 05.02.2024 21:00, H.J. Lu wrote:
> >>> Change .insn instruction with length > 15 bytes from error to warning.
> >>
> >> Thanks for doing this. FTAOD though - it addresses only half of my
> >> concern. Besides .insn (where the concern was of general nature) I
> >> also use
> >>
> >> bextr eax, fs:[eax*4], 0x11223344
> >> xacquire lock add qword ptr gs:[eax*8], 0x11223344
> >>
> >> in testing of my own disassembler library. I expect to continue to
> >> be able to avoid using .insn (and even more so .byte) when assembling
> >> this code. IOW there will still need to be a way to also override
> >> the defaulting to as_bad() when not using .insn.
> >
> > We issue a warning when something is wrong in input, but still manage
> > to generate an instruction. This is an error case.
>
> I disagree. It was a warning until you changed it (without me really
> agreeing), and some hypothetical vendor could come and lift the limit,
> on precisely the basis that there are legal encodings exceeding it. I'm
> okay if this can be forced to be an error, but I continue to think that
> it ought to be a warning only by default.
>
It is an error on both Intel and AMD processors. There is no
valid reason not to be an error at the moment. We can change
it when there is such a vendor in the future.
--
H.J.
next prev parent reply other threads:[~2024-02-06 12:26 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-05 20:00 H.J. Lu
2024-02-06 8:19 ` Jan Beulich
2024-02-06 11:36 ` H.J. Lu
2024-02-06 11:41 ` Jan Beulich
2024-02-06 12:26 ` H.J. Lu [this message]
2024-02-06 14:43 ` Michael Matz
2024-02-06 14:49 ` H.J. Lu
2024-02-06 15:04 ` Michael Matz
2024-02-06 15:34 ` H.J. Lu
2024-02-06 15:48 ` Michael Matz
2024-02-06 16:28 ` H.J. Lu
2024-02-06 17:05 ` Jan Beulich
2024-02-06 18:06 ` H.J. Lu
2024-02-07 7:51 ` Jan Beulich
2024-02-07 15:24 ` H.J. Lu
2024-02-07 15:32 ` Jan Beulich
2024-02-07 16:53 ` H.J. Lu
2024-02-07 16:59 ` Jan Beulich
2024-02-07 17:03 ` H.J. Lu
2024-02-08 4:09 ` Jiang, Haochen
2024-02-08 4:47 ` Hongyu Wang
2024-02-08 8:15 ` Jan Beulich
2024-02-08 8:23 ` Jan Beulich
2024-02-08 11:38 ` H.J. Lu
2024-02-08 6:26 ` Sunil Pandey
2024-02-08 6:41 ` Cui, Lili
2024-02-08 8:18 ` Jan Beulich
2024-02-08 11:31 ` H.J. Lu
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