From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 1/3] x86: extend FPU test coverage for AT&T / Intel mnemonic differences
Date: Tue, 29 Nov 2022 15:59:46 -0800 [thread overview]
Message-ID: <CAMe9rOqtcTFSPnznoDv+wRaTnVN=qiW_er7rOMD9VwHVpqZTig@mail.gmail.com> (raw)
In-Reply-To: <ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com>
On Thu, Nov 24, 2022 at 12:57 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Before touching the templates, let's ensure we actually cover things:
> For one FSUB{,R} and FDIV{,R} would better be tested with operands in
> both possible orders. And then -mmnemonic=intel wasn't tested at all.
>
> --- a/gas/testsuite/gas/i386/compat.d
> +++ b/gas/testsuite/gas/i386/compat.d
> @@ -8,18 +8,22 @@ Disassembly of section .text:
>
> 0+ <.text>:
> [ ]*[a-f0-9]+: dc e3 fsub %st,%st\(3\)
> +[ ]*[a-f0-9]+: d8 e3 fsub %st\(3\),%st
> [ ]*[a-f0-9]+: de e1 fsubp %st,%st\(1\)
> [ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
> [ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
> [ ]*[a-f0-9]+: dc eb fsubr %st,%st\(3\)
> +[ ]*[a-f0-9]+: d8 eb fsubr %st\(3\),%st
> [ ]*[a-f0-9]+: de e9 fsubrp %st,%st\(1\)
> [ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
> [ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
> [ ]*[a-f0-9]+: dc f3 fdiv %st,%st\(3\)
> +[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
> [ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
> [ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
> [ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
> [ ]*[a-f0-9]+: dc fb fdivr %st,%st\(3\)
> +[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
> [ ]*[a-f0-9]+: de f9 fdivrp %st,%st\(1\)
> [ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
> [ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
> --- a/gas/testsuite/gas/i386/compat.s
> +++ b/gas/testsuite/gas/i386/compat.s
> @@ -1,18 +1,22 @@
> # Check SYSV mnemonic instructions.
> .text
> fsub %st,%st(3)
> + fsub %st(3),%st
> fsubp
> fsubp %st(3)
> fsubp %st,%st(3)
> fsubr %st,%st(3)
> + fsubr %st(3),%st
> fsubrp
> fsubrp %st(3)
> fsubrp %st,%st(3)
> fdiv %st,%st(3)
> + fdiv %st(3),%st
> fdivp
> fdivp %st(3)
> fdivp %st,%st(3)
> fdivr %st,%st(3)
> + fdivr %st(3),%st
> fdivrp
> fdivrp %st(3)
> fdivrp %st,%st(3)
> --- a/gas/testsuite/gas/i386/compat-intel.d
> +++ b/gas/testsuite/gas/i386/compat-intel.d
> @@ -9,18 +9,22 @@ Disassembly of section .text:
>
> 0+ <.text>:
> [ ]*[a-f0-9]+: dc e3 fsubr st\(3\),st
> +[ ]*[a-f0-9]+: d8 e3 fsub st,st\(3\)
> [ ]*[a-f0-9]+: de e1 fsubrp st\(1\),st
> [ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
> [ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
> [ ]*[a-f0-9]+: dc eb fsub st\(3\),st
> +[ ]*[a-f0-9]+: d8 eb fsubr st,st\(3\)
> [ ]*[a-f0-9]+: de e9 fsubp st\(1\),st
> [ ]*[a-f0-9]+: de eb fsubp st\(3\),st
> [ ]*[a-f0-9]+: de eb fsubp st\(3\),st
> [ ]*[a-f0-9]+: dc f3 fdivr st\(3\),st
> +[ ]*[a-f0-9]+: d8 f3 fdiv st,st\(3\)
> [ ]*[a-f0-9]+: de f1 fdivrp st\(1\),st
> [ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
> [ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
> [ ]*[a-f0-9]+: dc fb fdiv st\(3\),st
> +[ ]*[a-f0-9]+: d8 fb fdivr st,st\(3\)
> [ ]*[a-f0-9]+: de f9 fdivp st\(1\),st
> [ ]*[a-f0-9]+: de fb fdivp st\(3\),st
> [ ]*[a-f0-9]+: de fb fdivp st\(3\),st
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/compat-intel2.d
> @@ -0,0 +1,31 @@
> +#as: -mmnemonic=intel
> +#objdump: -d -Mintel-mnemonic
> +#name: i386 float Intel mnemonic (2)
> +#source: compat.s
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <.text>:
> +[ ]*[a-f0-9]+: dc eb fsub st\(3\),st
> +[ ]*[a-f0-9]+: d8 e3 fsub st,st\(3\)
> +[ ]*[a-f0-9]+: de e9 fsubp st\(1\),st
> +[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
> +[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
> +[ ]*[a-f0-9]+: dc e3 fsubr st\(3\),st
> +[ ]*[a-f0-9]+: d8 eb fsubr st,st\(3\)
> +[ ]*[a-f0-9]+: de e1 fsubrp st\(1\),st
> +[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
> +[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
> +[ ]*[a-f0-9]+: dc fb fdiv st\(3\),st
> +[ ]*[a-f0-9]+: d8 f3 fdiv st,st\(3\)
> +[ ]*[a-f0-9]+: de f9 fdivp st\(1\),st
> +[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
> +[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
> +[ ]*[a-f0-9]+: dc f3 fdivr st\(3\),st
> +[ ]*[a-f0-9]+: d8 fb fdivr st,st\(3\)
> +[ ]*[a-f0-9]+: de f1 fdivrp st\(1\),st
> +[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
> +[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
> +#pass
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -178,6 +178,7 @@ if [gas_32_check] then {
> run_dump_test "i386-intel"
> run_dump_test "compat"
> run_dump_test "compat-intel"
> + run_dump_test "compat-intel2"
> run_dump_test "arch-1"
> run_dump_test "arch-2"
> run_dump_test "arch-3"
>
OK
Thanks.
--
H.J.
next prev parent reply other threads:[~2022-11-30 0:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 8:56 [PATCH 0/3] x86: FPU insn handling simplifications Jan Beulich
2022-11-24 8:57 ` [PATCH 1/3] x86: extend FPU test coverage for AT&T / Intel mnemonic differences Jan Beulich
2022-11-29 23:59 ` H.J. Lu [this message]
2022-11-24 8:57 ` [PATCH 2/3] x86: drop FloatR Jan Beulich
2022-11-30 0:00 ` H.J. Lu
2022-11-24 8:58 ` [PATCH 3/3] x86: clean up after removal of support for gcc <= 2.8.1 Jan Beulich
2022-11-28 23:21 ` H.J. Lu
2022-11-29 9:02 ` Jan Beulich
2022-11-30 0:00 ` H.J. Lu
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