* [PATCH] x86: make {disp16} work similarly to {disp32}
@ 2022-04-04 15:13 Jan Beulich
2022-04-13 17:07 ` H.J. Lu
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2022-04-04 15:13 UTC (permalink / raw)
To: Binutils
In a few places {disp32} was handled specially when really {disp16}
wants handling just the same.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4935,7 +4935,7 @@ md_assemble (char *line)
/* Don't optimize displacement for movabs since it only takes 64bit
displacement. */
if (i.disp_operands
- && i.disp_encoding != disp_encoding_32bit
+ && i.disp_encoding <= disp_encoding_8bit
&& (flag_code != CODE_64BIT
|| strcmp (mnemonic, "movabs") != 0))
optimize_disp ();
@@ -6302,7 +6302,7 @@ check_VecOperands (const insn_template *
/* Check vector Disp8 operand. */
if (t->opcode_modifier.disp8memshift
- && i.disp_encoding != disp_encoding_32bit)
+ && i.disp_encoding <= disp_encoding_8bit)
{
if (i.broadcast.type)
i.memshift = t->opcode_modifier.broadcast - 1;
@@ -8770,7 +8770,7 @@ output_branch (void)
}
code16 = flag_code == CODE_16BIT ? CODE16 : 0;
- size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
+ size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL;
prefix = 0;
if (i.prefix[DATA_PREFIX] != 0)
--- a/gas/testsuite/gas/i386/inval-pseudo.l
+++ b/gas/testsuite/gas/i386/inval-pseudo.l
@@ -2,6 +2,8 @@
.*:3: Error: .*
.*:5: Error: .*
.*:6: Error: .*
+.*:7: Error: .*
+.*:9: Error: .*
GAS LISTING .*
@@ -11,5 +13,7 @@ GAS LISTING .*
[ ]*4[ ]+\?\?\?\? 90 nop
[ ]*5[ ]+\{disp32\} movb \(%bp\),%al
[ ]*6[ ]+\{disp16\} movb \(%ebp\),%al
-[ ]*7[ ]+\?\?\?\? 00000000 \.p2align 4,0
+[ ]*7[ ]+\{disp16\} jmp \.
+[ ]*8[ ]+\.code16
+[ ]*9[ ]+\{disp32\} jmp \.
#...
--- a/gas/testsuite/gas/i386/inval-pseudo.s
+++ b/gas/testsuite/gas/i386/inval-pseudo.s
@@ -4,4 +4,7 @@
nop
{disp32} movb (%bp),%al
{disp16} movb (%ebp),%al
+ {disp16} jmp .
+ .code16
+ {disp32} jmp .
.p2align 4,0
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -25,6 +25,7 @@ Disassembly of section .text:
+[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
@@ -324,6 +325,7 @@ Disassembly of section .text:
+[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
@@ -354,4 +356,6 @@ Disassembly of section .text:
+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: e9 fb ff ff ff jmp [0-9a-f]* <.*>
+ +[a-f0-9]+: e9 fd ff ff ff jmp [0-9a-f]* <.*>
#pass
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -20,6 +20,7 @@ _start:
{vex} {disp8} vmovaps 128(%eax),%xmm2
{vex} {disp32} vmovaps 128(%eax),%xmm2
{evex} {disp8} vmovaps 128(%eax),%xmm2
+ {evex} {disp16} vmovaps 128(%bx),%xmm2
{evex} {disp32} vmovaps 128(%eax),%xmm2
mov %ecx, %eax
@@ -337,6 +338,7 @@ _start:
{vex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
{vex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
{evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
+ {evex} {disp16} vmovaps xmm2,XMMWORD PTR [bx+128]
{evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
mov eax,ecx
@@ -373,3 +375,8 @@ _start:
mov al, BYTE PTR [bp]
{disp8} mov al, BYTE PTR [bp]
{disp16} mov al, BYTE PTR [bp]
+
+ {disp32} jmp .
+ .code16
+ {disp16} jmp .
+ .byte -1, -1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] x86: make {disp16} work similarly to {disp32}
2022-04-04 15:13 [PATCH] x86: make {disp16} work similarly to {disp32} Jan Beulich
@ 2022-04-13 17:07 ` H.J. Lu
0 siblings, 0 replies; 2+ messages in thread
From: H.J. Lu @ 2022-04-13 17:07 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Mon, Apr 4, 2022 at 8:13 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> In a few places {disp32} was handled specially when really {disp16}
> wants handling just the same.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -4935,7 +4935,7 @@ md_assemble (char *line)
> /* Don't optimize displacement for movabs since it only takes 64bit
> displacement. */
> if (i.disp_operands
> - && i.disp_encoding != disp_encoding_32bit
> + && i.disp_encoding <= disp_encoding_8bit
> && (flag_code != CODE_64BIT
> || strcmp (mnemonic, "movabs") != 0))
> optimize_disp ();
> @@ -6302,7 +6302,7 @@ check_VecOperands (const insn_template *
>
> /* Check vector Disp8 operand. */
> if (t->opcode_modifier.disp8memshift
> - && i.disp_encoding != disp_encoding_32bit)
> + && i.disp_encoding <= disp_encoding_8bit)
> {
> if (i.broadcast.type)
> i.memshift = t->opcode_modifier.broadcast - 1;
> @@ -8770,7 +8770,7 @@ output_branch (void)
> }
>
> code16 = flag_code == CODE_16BIT ? CODE16 : 0;
> - size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
> + size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL;
>
> prefix = 0;
> if (i.prefix[DATA_PREFIX] != 0)
> --- a/gas/testsuite/gas/i386/inval-pseudo.l
> +++ b/gas/testsuite/gas/i386/inval-pseudo.l
> @@ -2,6 +2,8 @@
> .*:3: Error: .*
> .*:5: Error: .*
> .*:6: Error: .*
> +.*:7: Error: .*
> +.*:9: Error: .*
> GAS LISTING .*
>
>
> @@ -11,5 +13,7 @@ GAS LISTING .*
> [ ]*4[ ]+\?\?\?\? 90 nop
> [ ]*5[ ]+\{disp32\} movb \(%bp\),%al
> [ ]*6[ ]+\{disp16\} movb \(%ebp\),%al
> -[ ]*7[ ]+\?\?\?\? 00000000 \.p2align 4,0
> +[ ]*7[ ]+\{disp16\} jmp \.
> +[ ]*8[ ]+\.code16
> +[ ]*9[ ]+\{disp32\} jmp \.
> #...
> --- a/gas/testsuite/gas/i386/inval-pseudo.s
> +++ b/gas/testsuite/gas/i386/inval-pseudo.s
> @@ -4,4 +4,7 @@
> nop
> {disp32} movb (%bp),%al
> {disp16} movb (%ebp),%al
> + {disp16} jmp .
> + .code16
> + {disp32} jmp .
> .p2align 4,0
> --- a/gas/testsuite/gas/i386/pseudos.d
> +++ b/gas/testsuite/gas/i386/pseudos.d
> @@ -25,6 +25,7 @@ Disassembly of section .text:
> +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
> + +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
> +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: 89 c8 mov %ecx,%eax
> +[a-f0-9]+: 8b c1 mov %ecx,%eax
> @@ -324,6 +325,7 @@ Disassembly of section .text:
> +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
> + +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
> +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
> +[a-f0-9]+: 89 c8 mov %ecx,%eax
> +[a-f0-9]+: 8b c1 mov %ecx,%eax
> @@ -354,4 +356,6 @@ Disassembly of section .text:
> +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
> +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
> +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
> + +[a-f0-9]+: e9 fb ff ff ff jmp [0-9a-f]* <.*>
> + +[a-f0-9]+: e9 fd ff ff ff jmp [0-9a-f]* <.*>
> #pass
> --- a/gas/testsuite/gas/i386/pseudos.s
> +++ b/gas/testsuite/gas/i386/pseudos.s
> @@ -20,6 +20,7 @@ _start:
> {vex} {disp8} vmovaps 128(%eax),%xmm2
> {vex} {disp32} vmovaps 128(%eax),%xmm2
> {evex} {disp8} vmovaps 128(%eax),%xmm2
> + {evex} {disp16} vmovaps 128(%bx),%xmm2
> {evex} {disp32} vmovaps 128(%eax),%xmm2
>
> mov %ecx, %eax
> @@ -337,6 +338,7 @@ _start:
> {vex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
> {vex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
> {evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
> + {evex} {disp16} vmovaps xmm2,XMMWORD PTR [bx+128]
> {evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
>
> mov eax,ecx
> @@ -373,3 +375,8 @@ _start:
> mov al, BYTE PTR [bp]
> {disp8} mov al, BYTE PTR [bp]
> {disp16} mov al, BYTE PTR [bp]
> +
> + {disp32} jmp .
> + .code16
> + {disp16} jmp .
> + .byte -1, -1
>
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-04-04 15:13 [PATCH] x86: make {disp16} work similarly to {disp32} Jan Beulich
2022-04-13 17:07 ` H.J. Lu
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