* Re: [PATCH] PowerPC VLE changes
@ 2017-03-24 15:32 Александр Федотов
2017-03-27 14:32 ` Andrew Jenner
0 siblings, 1 reply; 20+ messages in thread
From: Александр Федотов @ 2017-03-24 15:32 UTC (permalink / raw)
To: binutils
Hi all
I have question in continuation of
https://sourceware.org/ml/binutils/2016-07/msg00342.html
Why do you need to have "e_cmpwi" etc in vle_opcodes table ? It seems
they are just alias names because of the same opcodes and objdump
never show them.
Why don't to use powerpc_macros instead ?
And it seems that following instructions must be marked as E200Z4 also
respectively to MPC5748G Reference Manual:
lbdx
lhdx
lwdx
stbdx
sthdx
stwdx
Alexander
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-03-24 15:32 [PATCH] PowerPC VLE changes Александр Федотов
@ 2017-03-27 14:32 ` Andrew Jenner
2017-03-28 14:14 ` Александр Федотов
2017-03-28 23:33 ` Alan Modra
0 siblings, 2 replies; 20+ messages in thread
From: Andrew Jenner @ 2017-03-27 14:32 UTC (permalink / raw)
To: Александр
Федотов,
binutils
Hi Alexander,
On 24/03/2017 15:32, ÐлекÑандр Федотов wrote:
> I have question in continuation of
> https://sourceware.org/ml/binutils/2016-07/msg00342.html
>
> Why do you need to have "e_cmpwi" etc in vle_opcodes table ? It seems
> they are just alias names because of the same opcodes and objdump
> never show them.
> Why don't to use powerpc_macros instead ?
>
> And it seems that following instructions must be marked as E200Z4 also
> respectively to MPC5748G Reference Manual:
>
> lbdx
> lhdx
> lwdx
> stbdx
> sthdx
> stwdx
You may very well be right, on both counts. If you'd like to propose a
patch, I'll take a look and run tests on it. Otherwise, I'll look into
making these changes next time I'm doing some VLE work.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-03-27 14:32 ` Andrew Jenner
@ 2017-03-28 14:14 ` Александр Федотов
2017-03-28 23:33 ` Alan Modra
1 sibling, 0 replies; 20+ messages in thread
From: Александр Федотов @ 2017-03-28 14:14 UTC (permalink / raw)
To: Andrew Jenner; +Cc: binutils
Hello Andrew
Here is the patch:
diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
--- binutils-2.28-orig/opcodes/ppc-opc.c 2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28/opcodes/ppc-opc.c 2017-03-28 16:51:08.000000000 +0300
@@ -5762,7 +5762,7 @@
{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
@@ -5813,7 +5813,7 @@
{"maskir.", XRC(31,541,1), X_MASK, M601, 0,
{RA, RS, RB}},
{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD,
RA0, RB}},
@@ -5837,7 +5837,7 @@
{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD,
RA0, RB}},
@@ -5888,7 +5888,7 @@
{"lfdux", X(31,631), X_MASK, COM, PPCEFS,
{FRT, RAS, RB}},
{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0,
{FCRT, RA, RB}},
@@ -5926,7 +5926,7 @@
{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0,
{VS, RA0, RB}},
@@ -5944,7 +5944,7 @@
{"sriq.", XRC(31,696,1), X_MASK, M601, 0,
{RA, RS, SH}},
{"stwdcbx", X(31,706), X_MASK, E200Z4, 0,
{RS, RA, RB}},
-{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvflx", X(31,709), X_MASK, PPCVEC2, 0,
{VS, RA0, RB}},
@@ -7020,9 +7020,7 @@
{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0,
{CRD32, RA, SCLSCI8}},
-{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0,
{CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0,
{CRD32, RA, SCLSCI8}},
-{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0,
{CRD32, RA, SCLSCI8}},
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT,
RA, SCLSCI8}},
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT,
RA, SCLSCI8N}},
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT,
RA, SCLSCI8}},
@@ -7273,6 +7271,8 @@
{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
+{"e_cmpwi", 3, PPCVLE, "e_cmpi %0,%1,%2"},
+{"e_cmplwi", 3, PPCVLE, "e_cmpli %0,%1,%2"},
{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
{"e_extrwi", 4, PPCVLE, "e_rlwinm
%0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
{"e_inslwi", 4, PPCVLE, "e_rlwimi
%0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
Alex
2017-03-27 17:32 GMT+03:00 Andrew Jenner <andrew@codesourcery.com>:
> Hi Alexander,
>
> On 24/03/2017 15:32, Александр Федотов wrote:
>>
>> I have question in continuation of
>> https://sourceware.org/ml/binutils/2016-07/msg00342.html
>>
>> Why do you need to have "e_cmpwi" etc in vle_opcodes table ? It seems
>> they are just alias names because of the same opcodes and objdump
>> never show them.
>> Why don't to use powerpc_macros instead ?
>>
>> And it seems that following instructions must be marked as E200Z4 also
>> respectively to MPC5748G Reference Manual:
>>
>> lbdx
>> lhdx
>> lwdx
>> stbdx
>> sthdx
>> stwdx
>
>
> You may very well be right, on both counts. If you'd like to propose a
> patch, I'll take a look and run tests on it. Otherwise, I'll look into
> making these changes next time I'm doing some VLE work.
>
> Thanks,
>
> Andrew
--
Best regards,
AF
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-03-27 14:32 ` Andrew Jenner
2017-03-28 14:14 ` Александр Федотов
@ 2017-03-28 23:33 ` Alan Modra
2017-03-29 19:36 ` Alexander Fedotov
1 sibling, 1 reply; 20+ messages in thread
From: Alan Modra @ 2017-03-28 23:33 UTC (permalink / raw)
To: Andrew Jenner
Cc: Александр
Федотов,
binutils
On Mon, Mar 27, 2017 at 03:32:23PM +0100, Andrew Jenner wrote:
> Hi Alexander,
>
> On 24/03/2017 15:32, ÐлекÑандр Федотов wrote:
> >I have question in continuation of
> >https://sourceware.org/ml/binutils/2016-07/msg00342.html
> >
> >Why do you need to have "e_cmpwi" etc in vle_opcodes table ? It seems
> >they are just alias names because of the same opcodes and objdump
> >never show them.
> >Why don't to use powerpc_macros instead ?
It is the other way around. If there is something in the macro table
that could go in the main opcode table then it should be moved there.
Mnemonic lookup in the main opcode table happens first. Macro lookup
is later. So putting something in the macro table unnecessarily, just
slows does the assembler a litte. The macro table should really only
be used where some manipulation of arguments is needed.
Hmm, looking at the macros, that means e_rotlwi and e_clrlwi probably
ought to be moved since the macros just provide a default argument to
the underlying machine insn rather than some arithmetic manipulation.
Fixing this isn't at all important though, so don't see these comments
as a request for someone to tidy the VLE support. Note that moving
those insns to the main table would also allow the disassembler to
produce e_rotlwi or e_clrlwi rather than e_rlwinm, depending on
whether you place them before e_rlwinm or after. I recognize that
some people (more hardware oriented) would prefer to see rlwinm rather
than rotlwi (likely prefered by those more software oriented). I've
just been working on a patch that will add -Mraw to the powerpc
disassembler to maybe satisfy both camps.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-03-28 23:33 ` Alan Modra
@ 2017-03-29 19:36 ` Alexander Fedotov
2017-04-04 1:29 ` Alan Modra
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Fedotov @ 2017-03-29 19:36 UTC (permalink / raw)
To: Alan Modra; +Cc: Andrew Jenner, binutils
Well, I think while such aliases are not in PowerISA and may be
changed in any moment - better to move such ones to macros table.
Performance should not harm dramatically if at all.
Anyway, don't miss decorated storage instruction for e200z4 from my patch.
On Wed, Mar 29, 2017 at 2:33 AM, Alan Modra <amodra@gmail.com> wrote:
> On Mon, Mar 27, 2017 at 03:32:23PM +0100, Andrew Jenner wrote:
>> Hi Alexander,
>>
>> On 24/03/2017 15:32, Александр Федотов wrote:
>> >I have question in continuation of
>> >https://sourceware.org/ml/binutils/2016-07/msg00342.html
>> >
>> >Why do you need to have "e_cmpwi" etc in vle_opcodes table ? It seems
>> >they are just alias names because of the same opcodes and objdump
>> >never show them.
>> >Why don't to use powerpc_macros instead ?
>
> It is the other way around. If there is something in the macro table
> that could go in the main opcode table then it should be moved there.
>
> Mnemonic lookup in the main opcode table happens first. Macro lookup
> is later. So putting something in the macro table unnecessarily, just
> slows does the assembler a litte. The macro table should really only
> be used where some manipulation of arguments is needed.
>
> Hmm, looking at the macros, that means e_rotlwi and e_clrlwi probably
> ought to be moved since the macros just provide a default argument to
> the underlying machine insn rather than some arithmetic manipulation.
> Fixing this isn't at all important though, so don't see these comments
> as a request for someone to tidy the VLE support. Note that moving
> those insns to the main table would also allow the disassembler to
> produce e_rotlwi or e_clrlwi rather than e_rlwinm, depending on
> whether you place them before e_rlwinm or after. I recognize that
> some people (more hardware oriented) would prefer to see rlwinm rather
> than rotlwi (likely prefered by those more software oriented). I've
> just been working on a patch that will add -Mraw to the powerpc
> disassembler to maybe satisfy both camps.
>
> --
> Alan Modra
> Australia Development Lab, IBM
--
Best regards,
AF
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-03-29 19:36 ` Alexander Fedotov
@ 2017-04-04 1:29 ` Alan Modra
2017-04-04 10:23 ` Alexander Fedotov
0 siblings, 1 reply; 20+ messages in thread
From: Alan Modra @ 2017-04-04 1:29 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: Andrew Jenner, binutils
On Wed, Mar 29, 2017 at 10:36:36PM +0300, Alexander Fedotov wrote:
> Well, I think while such aliases are not in PowerISA and may be
> changed in any moment - better to move such ones to macros table.
> Performance should not harm dramatically if at all.
>
> Anyway, don't miss decorated storage instruction for e200z4 from my patch.
I don't like being a dictator since that tends to drive away
contributors, but let me make it absolutely clear. I will not accept
a patch that moves insns to the powerpc macro table. Since your patch
at https://sourceware.org/ml/binutils/2017-03/msg00348.html does that,
and lacks a ChangeLog entry, it is currently blocked.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-04-04 1:29 ` Alan Modra
@ 2017-04-04 10:23 ` Alexander Fedotov
2017-04-04 10:33 ` Alexander Fedotov
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Fedotov @ 2017-04-04 10:23 UTC (permalink / raw)
To: Alan Modra; +Cc: Andrew Jenner, binutils
Okay. Removed change about macro from patch. Kept only e200z4 instructions.
diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
--- binutils-2.28-orig/opcodes/ppc-opc.c 2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28/opcodes/ppc-opc.c 2017-04-04 13:21:36.789164587 +0300
@@ -5762,7 +5762,7 @@
{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
@@ -5813,7 +5813,7 @@
{"maskir.", XRC(31,541,1), X_MASK, M601, 0,
{RA, RS, RB}},
{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD,
RA0, RB}},
@@ -5837,7 +5837,7 @@
{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0,
{RT, RA, RB}},
{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD,
RA0, RB}},
@@ -5888,7 +5888,7 @@
{"lfdux", X(31,631), X_MASK, COM, PPCEFS,
{FRT, RAS, RB}},
{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0,
{FCRT, RA, RB}},
@@ -5926,7 +5926,7 @@
{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0,
{VS, RA0, RB}},
@@ -5944,7 +5944,7 @@
{"sriq.", XRC(31,696,1), X_MASK, M601, 0,
{RA, RS, SH}},
{"stwdcbx", X(31,706), X_MASK, E200Z4, 0,
{RS, RA, RB}},
-{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0,
{RS, RA, RB}},
{"stvflx", X(31,709), X_MASK, PPCVEC2, 0,
{VS, RA0, RB}},
On Tue, Apr 4, 2017 at 4:28 AM, Alan Modra <amodra@gmail.com> wrote:
> On Wed, Mar 29, 2017 at 10:36:36PM +0300, Alexander Fedotov wrote:
>> Well, I think while such aliases are not in PowerISA and may be
>> changed in any moment - better to move such ones to macros table.
>> Performance should not harm dramatically if at all.
>>
>> Anyway, don't miss decorated storage instruction for e200z4 from my patch.
>
> I don't like being a dictator since that tends to drive away
> contributors, but let me make it absolutely clear. I will not accept
> a patch that moves insns to the powerpc macro table. Since your patch
> at https://sourceware.org/ml/binutils/2017-03/msg00348.html does that,
> and lacks a ChangeLog entry, it is currently blocked.
>
> --
> Alan Modra
> Australia Development Lab, IBM
--
Best regards,
AF
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-04-04 10:23 ` Alexander Fedotov
@ 2017-04-04 10:33 ` Alexander Fedotov
2017-04-22 8:51 ` Alan Modra
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Fedotov @ 2017-04-04 10:33 UTC (permalink / raw)
To: Alan Modra; +Cc: Andrew Jenner, binutils
Another one is related to VLE also:
diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
--- binutils-2.28-orig/opcodes/ppc-opc.c 2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28/opcodes/ppc-opc.c 2017-04-04 13:27:48.125164587 +0300
@@ -6997,6 +6997,7 @@
{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
+{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
@@ -7154,6 +7155,7 @@
{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
+{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
On Tue, Apr 4, 2017 at 1:23 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> Okay. Removed change about macro from patch. Kept only e200z4 instructions.
>
> diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
> --- binutils-2.28-orig/opcodes/ppc-opc.c 2017-03-02 11:23:54.000000000 +0300
> +++ binutils-2.28/opcodes/ppc-opc.c 2017-04-04 13:21:36.789164587 +0300
> @@ -5762,7 +5762,7 @@
> {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
>
> {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
> -{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
> +{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0,
> {RT, RA, RB}},
>
> {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
>
> @@ -5813,7 +5813,7 @@
> {"maskir.", XRC(31,541,1), X_MASK, M601, 0,
> {RA, RS, RB}},
>
> {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
> -{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
> +{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0,
> {RT, RA, RB}},
>
> {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD,
> RA0, RB}},
>
> @@ -5837,7 +5837,7 @@
> {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
>
> {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
> -{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
> +{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0,
> {RT, RA, RB}},
>
> {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD,
> RA0, RB}},
>
> @@ -5888,7 +5888,7 @@
> {"lfdux", X(31,631), X_MASK, COM, PPCEFS,
> {FRT, RAS, RB}},
>
> {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
> -{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
> +{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0,
> {RS, RA, RB}},
>
> {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
> {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0,
> {FCRT, RA, RB}},
> @@ -5926,7 +5926,7 @@
> {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
>
> {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
> -{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
> +{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0,
> {RS, RA, RB}},
>
> {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0,
> {VS, RA0, RB}},
>
> @@ -5944,7 +5944,7 @@
> {"sriq.", XRC(31,696,1), X_MASK, M601, 0,
> {RA, RS, SH}},
>
> {"stwdcbx", X(31,706), X_MASK, E200Z4, 0,
> {RS, RA, RB}},
> -{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
> +{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0,
> {RS, RA, RB}},
>
> {"stvflx", X(31,709), X_MASK, PPCVEC2, 0,
> {VS, RA0, RB}},
>
> On Tue, Apr 4, 2017 at 4:28 AM, Alan Modra <amodra@gmail.com> wrote:
>> On Wed, Mar 29, 2017 at 10:36:36PM +0300, Alexander Fedotov wrote:
>>> Well, I think while such aliases are not in PowerISA and may be
>>> changed in any moment - better to move such ones to macros table.
>>> Performance should not harm dramatically if at all.
>>>
>>> Anyway, don't miss decorated storage instruction for e200z4 from my patch.
>>
>> I don't like being a dictator since that tends to drive away
>> contributors, but let me make it absolutely clear. I will not accept
>> a patch that moves insns to the powerpc macro table. Since your patch
>> at https://sourceware.org/ml/binutils/2017-03/msg00348.html does that,
>> and lacks a ChangeLog entry, it is currently blocked.
>>
>> --
>> Alan Modra
>> Australia Development Lab, IBM
>
>
>
> --
> Best regards,
> AF
--
Best regards,
AF
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-04-04 10:33 ` Alexander Fedotov
@ 2017-04-22 8:51 ` Alan Modra
0 siblings, 0 replies; 20+ messages in thread
From: Alan Modra @ 2017-04-22 8:51 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: Andrew Jenner, binutils
On Tue, Apr 04, 2017 at 01:33:44PM +0300, Alexander Fedotov wrote:
> Another one is related to VLE also:
Neither of these patches applied, because your mail client wrapped
lines and converted tabs to spaces. The second didn't compile,
lacking a definition for ELEV, and ChangeLog entries were missing.
I've fixed these problems and added to the VLE gas testsuite.
Committed.
opcodes/
* ppc-opc.c (ELEV): Define.
(vle_opcodes): Add se_rfgi and e_sc.
(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
for E200Z4.
gas/
* testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
* testsuite/gas/ppc/vle.d: Update.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a31c799..c5531a7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-22 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
+ * testsuite/gas/ppc/vle.d: Update.
+
2017-04-21 Nick Clifton <nickc@redhat.com>
PR binutils/21380
diff --git a/gas/testsuite/gas/ppc/vle.d b/gas/testsuite/gas/ppc/vle.d
index ea75658..dcc2cc3 100644
--- a/gas/testsuite/gas/ppc/vle.d
+++ b/gas/testsuite/gas/ppc/vle.d
@@ -148,3 +148,7 @@ Disassembly of section \.text:
194: e9 c2 se_bl 118 <middle_label>
196: 79 ff ff 82 e_b 118 <middle_label>
19a: 79 ff fe 67 e_bl 0 <start_label>
+ 19e: 00 0c se_rfgi
+ 1a0: 7c 00 00 48 e_sc
+ 1a4: 7c 00 00 48 e_sc
+ 1a8: 7c 00 08 48 e_sc 1
diff --git a/gas/testsuite/gas/ppc/vle.s b/gas/testsuite/gas/ppc/vle.s
index cab6120..4354c1f 100644
--- a/gas/testsuite/gas/ppc/vle.s
+++ b/gas/testsuite/gas/ppc/vle.s
@@ -41,144 +41,148 @@
.equ r31,31
.equ r32,32
.equ rsp,r1
-
-start_label:
+
+start_label:
e_add16i r4,r3,27
- e_add2i. r0,0x3456
- e_add2is r1,0x4321
- e_addi. r2,r6,SCI0
- e_addi r3,r5,SCI1
- e_addic. r4,r4,SCI2
- e_addic r7,r8,SCI3
- e_and2i. r9,0xfeed
- e_and2is. r10,5
- e_andi. r11,r13,0x39
- e_andi r12,r15,SCI2
- e_b middle_label
- e_bl extern_subr
- e_bc 0,3,start_label
- e_bcl 1,15,extern_subr
+ e_add2i. r0,0x3456
+ e_add2is r1,0x4321
+ e_addi. r2,r6,SCI0
+ e_addi r3,r5,SCI1
+ e_addic. r4,r4,SCI2
+ e_addic r7,r8,SCI3
+ e_and2i. r9,0xfeed
+ e_and2is. r10,5
+ e_andi. r11,r13,0x39
+ e_andi r12,r15,SCI2
+ e_b middle_label
+ e_bl extern_subr
+ e_bc 0,3,start_label
+ e_bcl 1,15,extern_subr
e_cmp16i r2,0x3333
e_cmpi 2,r6,SCI1
e_cmph 1,r7,r11
e_cmph16i r12,0xfdef
e_cmphl 0,r6,r8
e_cmphl16i r13,0x1234
- e_cmpl16i r1, 0xfee0
- e_cmpli 1,r3,SCI3
- e_crand 0x1d,3,0
- e_crandc 0,2,0x1d
- e_creqv 15,16,17
- e_crnand 0xf,0,3
- e_crnor 0xf,0,3
- e_cror 12,13,14
- e_crorc 19,18,17
- e_crxor 0,0,0
- e_lbz r7,0xffffcc0d(r3)
- e_lbzu r7,-52(r5)
- e_lha r8,0x1ff(r10)
- e_lhau r8,-1(r1)
+ e_cmpl16i r1, 0xfee0
+ e_cmpli 1,r3,SCI3
+ e_crand 0x1d,3,0
+ e_crandc 0,2,0x1d
+ e_creqv 15,16,17
+ e_crnand 0xf,0,3
+ e_crnor 0xf,0,3
+ e_cror 12,13,14
+ e_crorc 19,18,17
+ e_crxor 0,0,0
+ e_lbz r7,0xffffcc0d(r3)
+ e_lbzu r7,-52(r5)
+ e_lha r8,0x1ff(r10)
+ e_lhau r8,-1(r1)
e_lhz r7,6200(r0)
e_lhzu r7,62(r0)
- e_li r0,0x33333
- e_lis r1,0x3333
- e_lmw r5,24(r3)
- e_lwz r5,10024(r3)
- e_lwzu r6,0x72(r2)
- e_mcrf 1,6
- e_mulli r9,r10,SCI0
- e_mull2i r1,0x668
- e_or2i r5,0x2345
- e_or2is r5,0xa345
- e_ori. r7,r9,SCI0
- e_ori r7,r8,SCI1
- e_rlw r18, r22,r0
- e_rlw. r8, r2,r0
- e_rlwi r20,r3,21
- e_rlwi. r2,r3,21
- e_rlwimi r4,r19,13,8,15
- e_rlwinm r4,r1,13,1,17
- e_slwi r12,r19,6
- e_slwi. r12,r10,20
- e_srwi r0,r1,16
- e_srwi. r0,r1,11
- e_stb r3,22000(r1)
- e_stbu r19,-4(r22)
- e_sth r0,666(r21)
- e_sthu r1,-1(r23)
- e_stmw r0,4(r3)
- e_stw r3,16161(r0)
- e_stwu r22,0xffffffee(r4)
- e_subfic r0,r21,SCI2
- e_subfic. r22,r0,SCI3
- e_xori r21,r3,SCI1
- e_xori. r0,r20,SCI0
-middle_label:
- se_add r31,r7
- se_addi r28,0x1f
- se_and r0,r1
- se_and. r1,r0
- se_andc r2, r3
- se_andi r4,0x11
- se_b middle_label
- se_bl extern_subr
- se_bc 1,3,not_end_label
- se_bclri r27,0x12
- se_bctr
- se_bctrl
- se_bgeni r7,17
- se_blr
- se_blrl
- se_bmaski r6,0
- se_bseti r0,1
- se_btsti r4,7
- se_cmp r0,r1
- se_cmph r31,r28
- se_cmphl r1,r25
- se_cmpi r3,22
- se_cmpl r6,r7
- se_cmpli r28,0xc
- se_extsb r1
- se_extsh r2
- se_extzb r30
- se_extzh r24
+ e_li r0,0x33333
+ e_lis r1,0x3333
+ e_lmw r5,24(r3)
+ e_lwz r5,10024(r3)
+ e_lwzu r6,0x72(r2)
+ e_mcrf 1,6
+ e_mulli r9,r10,SCI0
+ e_mull2i r1,0x668
+ e_or2i r5,0x2345
+ e_or2is r5,0xa345
+ e_ori. r7,r9,SCI0
+ e_ori r7,r8,SCI1
+ e_rlw r18, r22,r0
+ e_rlw. r8, r2,r0
+ e_rlwi r20,r3,21
+ e_rlwi. r2,r3,21
+ e_rlwimi r4,r19,13,8,15
+ e_rlwinm r4,r1,13,1,17
+ e_slwi r12,r19,6
+ e_slwi. r12,r10,20
+ e_srwi r0,r1,16
+ e_srwi. r0,r1,11
+ e_stb r3,22000(r1)
+ e_stbu r19,-4(r22)
+ e_sth r0,666(r21)
+ e_sthu r1,-1(r23)
+ e_stmw r0,4(r3)
+ e_stw r3,16161(r0)
+ e_stwu r22,0xffffffee(r4)
+ e_subfic r0,r21,SCI2
+ e_subfic. r22,r0,SCI3
+ e_xori r21,r3,SCI1
+ e_xori. r0,r20,SCI0
+middle_label:
+ se_add r31,r7
+ se_addi r28,0x1f
+ se_and r0,r1
+ se_and. r1,r0
+ se_andc r2, r3
+ se_andi r4,0x11
+ se_b middle_label
+ se_bl extern_subr
+ se_bc 1,3,not_end_label
+ se_bclri r27,0x12
+ se_bctr
+ se_bctrl
+ se_bgeni r7,17
+ se_blr
+ se_blrl
+ se_bmaski r6,0
+ se_bseti r0,1
+ se_btsti r4,7
+ se_cmp r0,r1
+ se_cmph r31,r28
+ se_cmphl r1,r25
+ se_cmpi r3,22
+ se_cmpl r6,r7
+ se_cmpli r28,0xc
+ se_extsb r1
+ se_extsh r2
+ se_extzb r30
+ se_extzh r24
not_end_label:
- se_illegal
- se_isync
- se_lbz r1,8(r24)
- se_lhz r24,18(r4)
+ se_illegal
+ se_isync
+ se_lbz r1,8(r24)
+ se_lhz r24,18(r4)
se_li r4,0x4f
- se_lwz r6,60(r0)
- se_mfar r7,r8
- se_mfctr r3
- se_mflr r4
- se_mr r31,r0
- se_mtar r23,r2
- se_mtctr r6
- se_mtlr r31
+ se_lwz r6,60(r0)
+ se_mfar r7,r8
+ se_mfctr r3
+ se_mflr r4
+ se_mr r31,r0
+ se_mtar r23,r2
+ se_mtctr r6
+ se_mtlr r31
se_mullw r3,r4
- se_neg r24
- se_not r25
- se_or r0,r1
- se_rfci
- se_rfdi
- se_rfi
- se_sc
- se_slw r5,r6
- se_slwi r7,7
- se_sraw r6,r30
- se_srawi r25,8
- se_srw r30,r0
- se_srwi r29,25
- se_stb r0,10(r2)
- se_sth r1,12(r30)
- se_stw r7,0(r29)
- se_sub r1,r2
- se_subf r29,r26
- se_subi r7,24
+ se_neg r24
+ se_not r25
+ se_or r0,r1
+ se_rfci
+ se_rfdi
+ se_rfi
+ se_sc
+ se_slw r5,r6
+ se_slwi r7,7
+ se_sraw r6,r30
+ se_srawi r25,8
+ se_srw r30,r0
+ se_srwi r29,25
+ se_stb r0,10(r2)
+ se_sth r1,12(r30)
+ se_stw r7,0(r29)
+ se_sub r1,r2
+ se_subf r29,r26
+ se_subi r7,24
end_label:
- se_subi. r25,19
- se_bl middle_label
- e_b middle_label
- e_bl start_label
+ se_subi. r25,19
+ se_bl middle_label
+ e_b middle_label
+ e_bl start_label
+ se_rfgi
+ e_sc
+ e_sc 0
+ e_sc 1
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8595f2d..53ebe54 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (ELEV): Define.
+ (vle_opcodes): Add se_rfgi and e_sc.
+ (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
+ for E200Z4.
+
2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 55e6bed..426261a 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -652,8 +652,10 @@ const struct powerpc_operand powerpc_operands[] =
#define SH6_MASK ((0x1f << 11) | (1 << 1))
{ 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
- /* The SH field of the tlbwe instruction, which is optional. */
+ /* The SH field of some variants of the tlbre and tlbwe
+ instructions, and the ELEV field of the e_sc instruction. */
#define SHO SH6 + 1
+#define ELEV SHO
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The SI field in a D form instruction. */
@@ -5874,7 +5876,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
@@ -5925,7 +5927,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
@@ -5949,7 +5951,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
-{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
+{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
@@ -6000,7 +6002,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
@@ -6038,7 +6040,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
@@ -6056,7 +6058,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
-{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
+{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
@@ -7109,6 +7111,7 @@ const struct powerpc_opcode vle_opcodes[] = {
{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
+{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
@@ -7266,6 +7269,7 @@ const struct powerpc_opcode vle_opcodes[] = {
{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
+{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 21:34 ` Alexander Fedotov
@ 2017-06-24 13:22 ` Alan Modra
0 siblings, 0 replies; 20+ messages in thread
From: Alan Modra @ 2017-06-24 13:22 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: binutils, Edmar Wienskoski
On Sat, Jun 24, 2017 at 12:34:51AM +0300, Alexander Fedotov wrote:
> This patch separates EFS2 instructions from SPE2
Like the others, needs a Changelog entry.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:56 ` Alexander Fedotov
2017-06-23 21:34 ` Alexander Fedotov
@ 2017-06-24 13:21 ` Alan Modra
1 sibling, 0 replies; 20+ messages in thread
From: Alan Modra @ 2017-06-24 13:21 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: binutils, Edmar Wienskoski
On Fri, Jun 23, 2017 at 11:56:24PM +0300, Alexander Fedotov wrote:
> This patch for SPE2 instructions support
Missing Changelog.
> +static unsigned long insert_evuimm1_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_evuimm_lt8 (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
> static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_off_spe2 (unsigned long, long, ppc_cpu_t, const char **);
Overlong lines, missing extract functions.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:55 ` Alexander Fedotov
2017-06-23 20:56 ` Alexander Fedotov
@ 2017-06-24 13:18 ` Alan Modra
1 sibling, 0 replies; 20+ messages in thread
From: Alan Modra @ 2017-06-24 13:18 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: binutils, Edmar Wienskoski
On Fri, Jun 23, 2017 at 11:54:47PM +0300, Alexander Fedotov wrote:
> This patch for LSP instructions support
Missing Changelog.
> +static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
> +static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
If you need an insert function, then you also need an extract
function to disassemble correctly. Also, overlong lines.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:52 Alexander Fedotov
2017-06-23 20:55 ` Alexander Fedotov
@ 2017-06-24 13:11 ` Alan Modra
1 sibling, 0 replies; 20+ messages in thread
From: Alan Modra @ 2017-06-24 13:11 UTC (permalink / raw)
To: Alexander Fedotov; +Cc: binutils, Edmar Wienskoski
On Fri, Jun 23, 2017 at 11:51:57PM +0300, Alexander Fedotov wrote:
> Hello Alan
>
> We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
> All of them are based on 2.28 release.
Please rebase against current master, and provide Changelog entries.
> - if (symaddr - reladdr + max_branch_offset
> - < 2 * max_branch_offset)
> - continue;
> +
> + /* I don't trust the relocation check using ' ... < (2 * max_branch_offset)'
I do trust it. This change is silly.
> - stub_rtype = R_PPC_RELAX;
> + stub_rtype = (target_stub_type == stub_entry_type_vle) ? R_PPC_VLE_RELAX : R_PPC_RELAX;
Overlong lines. Wrap to 80 chars or less.
> @@ -7385,10 +7503,21 @@
> case R_PPC_REL24:
> case R_PPC_LOCAL24PC:
> case R_PPC_PLTREL24:
> - t0 = bfd_get_32 (abfd, hit_addr);
> - t0 &= ~0x3fffffc;
> - t0 |= val & 0x3fffffc;
> - bfd_put_32 (abfd, t0, hit_addr);
> + if (r_type == R_PPC_PLTREL24
> + && (elf_section_flags (isec) & SHF_PPC_VLE) != 0)
Something is fishy here. Why is PLTREL24 treated differently when
VLE? You haven't changed the insn here!
> @@ -9063,8 +9214,8 @@
> }
> else
> {
> - stub = stub_entry;
> - size = ARRAY_SIZE (stub_entry);
> + stub = (r_type == R_PPC_VLE_RELAX) ? stub_entry_vle : stub_entry;
> + size = ARRAY_SIZE (stub_entry); /* stub_entry and stub_entry_vle must be same size */
Overlong line again. An assert would be better than a comment.
> --- binutils-2.28/binutils/objdump.c 2017-03-02 11:23:53.000000000 +0300
> +++ binutils-2.28-vle/binutils/objdump.c 2017-06-23 17:25:21.641299056 +0300
> @@ -481,6 +481,10 @@
> PF (SEC_NEVER_LOAD, "NEVER_LOAD");
> PF (SEC_EXCLUDE, "EXCLUDE");
> PF (SEC_SORT_ENTRIES, "SORT_ENTRIES");
> + if (bfd_get_arch(abfd) == bfd_arch_powerpc || bfd_get_arch (abfd) == bfd_mach_ppc_vle)
> + {
> + PF (SEC_TIC54X_BLOCK, "VLE"); /* hack, would have to include ppc.h */
> + }
Ick. Don't do this, define a flag in bfd/section.c.
> diff -ruN binutils-2.28/include/elf/ppc.h binutils-2.28-vle/include/elf/ppc.h
> --- binutils-2.28/include/elf/ppc.h 2017-03-02 11:23:54.000000000 +0300
> +++ binutils-2.28-vle/include/elf/ppc.h 2017-06-23 17:34:20.838930833 +0300
> @@ -79,8 +79,10 @@
> RELOC_NUMBER (R_PPC_RELAX, 48)
> RELOC_NUMBER (R_PPC_RELAX_PLT, 49)
> RELOC_NUMBER (R_PPC_RELAX_PLTREL24, 50)
> + RELOC_NUMBER (R_PPC_VLE_RELAX, 51)
> /* Reloc only used internally by gas. As above, value is unimportant. */
> - RELOC_NUMBER (R_PPC_16DX_HA, 51)
> + RELOC_NUMBER (R_PPC_16DX_HA, 52)
> + RELOC_NUMBER (R_PPC_VLE_PLTREL24, 53)
> #endif
This seems an odd place to put R_PPC_VLE_PLTREL24. Is it just an
internal relocation? (I don't see anything that would use it, nor the
new R_PPC_VLE_ADDR20. Missing patch?)
> +/* BFD section headers flag. */
> +#define SEC_PPC_VLE SEC_TIC54X_BLOCK
No, this define is in the wrong place, and if you'd defined it in
section.c you would see why you can't reuse SEC_TIC54X_BLOCK.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:56 ` Alexander Fedotov
@ 2017-06-23 21:34 ` Alexander Fedotov
2017-06-24 13:22 ` Alan Modra
2017-06-24 13:21 ` Alan Modra
1 sibling, 1 reply; 20+ messages in thread
From: Alexander Fedotov @ 2017-06-23 21:34 UTC (permalink / raw)
To: Alan Modra, binutils; +Cc: Edmar Wienskoski
[-- Attachment #1: Type: text/plain, Size: 781 bytes --]
This patch separates EFS2 instructions from SPE2
Forgot to say about of patches apply order:
1. 2.28-vle.patch
2. 2.28-lsp.patch
3. 2.28-spe2.patch
4. 2.28-efs2.patch
Alex
On Fri, Jun 23, 2017 at 11:56 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> This patch for SPE2 instructions support
>
>
> On Fri, Jun 23, 2017 at 11:54 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
>> This patch for LSP instructions support
>>
>> On Fri, Jun 23, 2017 at 11:51 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
>>> Hello Alan
>>>
>>> We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
>>> All of them are based on 2.28 release.
>>>
>>> Best regards,
>>> Alexander
>>
>>
>>
>> --
>> Best regards,
>> AF
>
>
>
> --
> Best regards,
> AF
--
Best regards,
AF
[-- Attachment #2: 2.28-efs2.patch --]
[-- Type: text/x-patch, Size: 18892 bytes --]
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.d binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.d 2017-06-23 23:58:43.111735000 +0300
@@ -0,0 +1,19 @@
+#as: -mvle
+#objdump: -d -Mvle -Mefs2
+#name: Validate EFS2 instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 12 b0 efsmax r0,r1,r2
+ 4: 10 01 12 b1 efsmin r0,r1,r2
+ 8: 10 01 12 b8 efdmax r0,r1,r2
+ c: 10 01 12 b9 efdmin r0,r1,r2
+ 10: 10 01 02 c7 efssqrt r0,r1
+ 14: 10 04 12 d1 efscfh r0,r2
+ 18: 10 04 12 d5 efscth r0,r2
+ 1c: 10 01 02 e7 efdsqrt r0,r1
+ 20: 10 04 12 f1 efdcfh r0,r2
+ 24: 10 04 12 f5 efdcth r0,r2
\ No newline at end of file
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.s binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.s
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,18 @@
+# PA EFS2 instructions in accordance with EFP2_rev.1.4_spec
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+
+ efsmax rD, rA, rB
+ efsmin rD, rA, rB
+ efdmax rD, rA, rB
+ efdmin rD, rA, rB
+ efssqrt rD, rA
+ efscfh rD, rB
+ efscth rD, rB
+ efdsqrt rD, rA
+ efdcfh rD, rB
+ efdcth rD, rB
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.d binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.d 2017-06-23 23:58:43.111735000 +0300
@@ -0,0 +1,25 @@
+#as: -mvle
+#objdump: -d -Mefs -Mvle -Mefs2
+#name: Validate EFS instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 00 12 d1 efscfsi r0,r2
+ 4: 10 00 12 d5 efsctsi r0,r2
+ 8: 10 00 12 f1 efdcfsi r0,r2
+ c: 10 00 12 f5 efdctsi r0,r2
+ 10: 10 01 12 c2 efsmadd r0,r1,r2
+ 14: 10 01 12 c3 efsmsub r0,r1,r2
+ 18: 10 01 12 ca efsnmadd r0,r1,r2
+ 1c: 10 01 12 cb efsnmsub r0,r1,r2
+ 20: 10 01 12 e2 efdmadd r0,r1,r2
+ 24: 10 01 12 e3 efdmsub r0,r1,r2
+ 28: 10 01 12 ea efdnmadd r0,r1,r2
+ 2c: 10 01 12 eb efdnmsub r0,r1,r2
+ 30: 10 01 12 f0 efdcfuid r0,r2
+ 34: 10 01 12 f1 efdcfsid r0,r2
+ 38: 10 01 12 f8 efdctuidz r0,r2
+ 3c: 10 01 12 fa efdctsidz r0,r2
\ No newline at end of file
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.s binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.s
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,33 @@
+# PA EFS 1.0 and 1.1 instructions
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+
+;# EFS 1.0 instructions in accordance with EFP2_rev.1.4_spec
+ efscfsi rD, rB
+ efsctsi rD, rB
+ efdcfsi rD, rB
+ efdctsi rD, rB
+
+;# EFS 1.1 instructions in accordance with EFP2_rev.1.4_spec
+ efsmadd rD, rA, rB
+ efsmsub rD, rA, rB
+ efsnmadd rD, rA, rB
+ efsnmsub rD, rA, rB
+ efdmadd rD, rA, rB
+ efdmsub rD, rA, rB
+ efdnmadd rD, rA, rB
+ efdnmsub rD, rA, rB
+
+;# moved EFS opcodes in accordance with EFP2_rev.1.4_spec
+ efdcfuid rD, rB
+ efdcfsid rD, rB
+ efdctuidz rD, rB
+ efdctsidz rD, rB
+
+
+
+
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp binutils-2.28-efs2/gas/testsuite/gas/ppc/ppc.exp
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp 2017-06-23 17:54:18.847627054 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/ppc.exp 2017-06-24 00:04:26.643735001 +0300
@@ -61,6 +61,8 @@
run_dump_test "vle-simple-6"
run_dump_test "lsp"
run_dump_test "lsp-checks"
+ run_dump_test "efs"
+ run_dump_test "efs2"
run_dump_test "spe2"
run_dump_test "spe2-checks"
run_dump_test "spe"
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d binutils-2.28-efs2/gas/testsuite/gas/ppc/spe2.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d 2017-06-23 17:44:50.951717000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/spe2.d 2017-06-24 00:04:37.627735001 +0300
@@ -1,5 +1,5 @@
#as: -mvle -mspe2
-#objdump: -d -Mspe2
+#objdump: -d -Mspe2 -Mefs2
#name: Validate SPE2 instructions
.*: +file format elf.*-powerpc.*
diff -ruN binutils-2.28-spe2/include/opcode/ppc.h binutils-2.28-efs2/include/opcode/ppc.h
--- binutils-2.28-spe2/include/opcode/ppc.h 2017-06-23 17:55:36.864599055 +0300
+++ binutils-2.28-efs2/include/opcode/ppc.h 2017-06-24 00:05:19.075735001 +0300
@@ -225,6 +225,9 @@
/* Opcode is only supported by Freescale SPE2 APU. */
#define PPC_OPCODE_SPE2 0x4000000000000000ull
+/* Opcode is supported by EFS2. */
+#define PPC_OPCODE_EFS2 0x2000000000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff -ruN binutils-2.28-spe2/opcodes/ppc-dis.c binutils-2.28-efs2/opcodes/ppc-dis.c
--- binutils-2.28-spe2/opcodes/ppc-dis.c 2017-06-23 17:56:52.074975055 +0300
+++ binutils-2.28-efs2/opcodes/ppc-dis.c 2017-06-24 00:05:55.467735001 +0300
@@ -108,7 +108,8 @@
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4 | PPC_OPCODE_VLE),
+ | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4 | PPC_OPCODE_VLE
+ | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
0 },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
@@ -145,6 +146,8 @@
0 },
{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
0 },
+ { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
+ 0 },
{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
@@ -212,7 +215,7 @@
0 },
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
PPC_OPCODE_SPE },
- { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_SPE,
+ { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
PPC_OPCODE_SPE2 },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
@@ -220,7 +223,7 @@
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_LSP | PPC_OPCODE_SPE2),
+ | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
diff -ruN binutils-2.28-spe2/opcodes/ppc-opc.c binutils-2.28-efs2/opcodes/ppc-opc.c
--- binutils-2.28-spe2/opcodes/ppc-opc.c 2017-06-23 23:38:05.522746700 +0300
+++ binutils-2.28-efs2/opcodes/ppc-opc.c 2017-06-24 00:23:55.371735001 +0300
@@ -3252,6 +3252,7 @@
#define PPCSPE2 PPC_OPCODE_SPE2
#define PPCISEL PPC_OPCODE_ISEL
#define PPCEFS PPC_OPCODE_EFS
+#define PPCEFS2 PPC_OPCODE_EFS2
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCTMR PPC_OPCODE_TMR
@@ -3601,6 +3602,7 @@
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3614,10 +3616,12 @@
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
+{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
+{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
@@ -3627,19 +3631,43 @@
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
+{"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
+{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
+{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
@@ -3647,10 +3675,12 @@
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
@@ -3662,30 +3692,41 @@
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
-{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}},
+{"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}},
{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
-{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}},
+{"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}},
{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
+{"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
+{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
-{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
@@ -8672,42 +8713,6 @@
{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
-{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"evfsmax", VX (4, 672), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmin", VX (4, 673), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddsub", VX (4, 674), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubadd", VX (4, 675), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssum", VX (4, 676), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsdiff", VX (4, 677), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssumdiff", VX (4, 678), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsdiffsum", VX (4, 679), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddx", VX (4, 680), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubx", VX (4, 681), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddsubx", VX (4, 682), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubaddx", VX (4, 683), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmulx", VX (4, 684), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmule", VX (4, 686), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmulo", VX (4, 687), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmax", VX (4, 688), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmin", VX (4, 689), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efdmax", VX (4, 696), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efdmin", VX (4, 697), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmadd", VX (4, 706), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efsmsub", VX (4, 707), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"efsnmadd", VX (4, 714), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efsnmsub", VX (4, 715), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efdmadd", VX (4, 738), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdmsub", VX (4, 739), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"efdnmadd", VX (4, 746), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdnmsub", VX (4, 747), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:55 ` Alexander Fedotov
@ 2017-06-23 20:56 ` Alexander Fedotov
2017-06-23 21:34 ` Alexander Fedotov
2017-06-24 13:21 ` Alan Modra
2017-06-24 13:18 ` Alan Modra
1 sibling, 2 replies; 20+ messages in thread
From: Alexander Fedotov @ 2017-06-23 20:56 UTC (permalink / raw)
To: Alan Modra, binutils; +Cc: Edmar Wienskoski
[-- Attachment #1: Type: text/plain, Size: 470 bytes --]
This patch for SPE2 instructions support
On Fri, Jun 23, 2017 at 11:54 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> This patch for LSP instructions support
>
> On Fri, Jun 23, 2017 at 11:51 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
>> Hello Alan
>>
>> We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
>> All of them are based on 2.28 release.
>>
>> Best regards,
>> Alexander
>
>
>
> --
> Best regards,
> AF
--
Best regards,
AF
[-- Attachment #2: 2.28-spe2.patch --]
[-- Type: text/x-patch, Size: 178154 bytes --]
diff -ruN binutils-2.28-lsp/gas/config/tc-ppc.c binutils-2.28-spe2/gas/config/tc-ppc.c
--- binutils-2.28-lsp/gas/config/tc-ppc.c 2017-06-23 17:49:36.256993055 +0300
+++ binutils-2.28-spe2/gas/config/tc-ppc.c 2017-06-23 17:53:24.390869055 +0300
@@ -48,6 +48,9 @@
/* Whether or not, we've set target_big_endian. */
static int set_target_endian = 0;
+/* SPE version. Allowed values: 1 or 2 */
+int spe_version = 1;
+
/* Whether to use user friendly register names. */
#ifndef TARGET_REG_NAMES_P
#ifdef TE_PE
@@ -1215,6 +1218,15 @@
msolaris = FALSE;
ppc_comment_chars = ppc_eabi_comment_chars;
}
+ else if (strcmp (arg, "spe") == 0)
+ {
+ spe_version = 1;
+ }
+ else if (strcmp (arg, "spe2") == 0)
+ {
+ spe_version = 2;
+ ppc_cpu |= PPC_OPCODE_SPE2;
+ }
#endif
else
{
@@ -1311,6 +1323,7 @@
-me5500, generate code for Freescale e5500 core complex\n\
-me6500, generate code for Freescale e6500 core complex\n\
-mspe generate code for Motorola SPE instructions\n\
+-mspe2 generate code for Freescale SPE2 instructions\n\
-mvle generate code for Freescale VLE instructions\n\
-mtitan generate code for AppliedMicro Titan core complex\n\
-mregnames Allow symbolic names for registers\n\
@@ -1646,6 +1659,54 @@
}
}
+ /* SPE2 instructions */
+ if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2)
+ {
+ op_end = spe2_opcodes + spe2_num_opcodes;
+ for (op = spe2_opcodes; op < op_end; op++)
+ {
+ if (ENABLE_CHECKING)
+ {
+ if (op != spe2_opcodes)
+ {
+ unsigned old_seg, new_seg;
+
+ old_seg = VLE_OP (op[-1].opcode, op[-1].mask);
+ old_seg = VLE_OP_TO_SEG (old_seg);
+ new_seg = VLE_OP (op[0].opcode, op[0].mask);
+ new_seg = VLE_OP_TO_SEG (new_seg);
+
+ /* The major opcodes had better be sorted. Code in the
+ disassembler assumes the insns are sorted according to
+ major opcode. */
+ if (new_seg < old_seg)
+ {
+ as_bad (_("major opcode is not sorted for %s"), op->name);
+ bad_insn = TRUE;
+ }
+ }
+
+ bad_insn |= insn_validate (op);
+ }
+
+ if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated))
+ {
+ const char *retval;
+
+ retval = hash_insert (ppc_hash, op->name, (void *) op);
+ if (retval != NULL)
+ {
+ as_bad (_("duplicate instruction %s"),
+ op->name);
+ bad_insn = TRUE;
+ }
+ }
+ }
+
+ for (op = spe2_opcodes; op < op_end; op++)
+ hash_insert (ppc_hash, op->name, (void *) op);
+ }
+
/* Insert the macros into a hash table. */
ppc_macro_hash = hash_new ();
diff -ruN binutils-2.28-lsp/gas/doc/c-ppc.texi binutils-2.28-spe2/gas/doc/c-ppc.texi
--- binutils-2.28-lsp/gas/doc/c-ppc.texi 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-spe2/gas/doc/c-ppc.texi 2017-06-23 17:53:43.969075055 +0300
@@ -99,6 +99,9 @@
@item -mspe
Generate code for Motorola SPE instructions.
+@item -mspe2
+Generate code for Freescale SPE2 instructions.
+
@item -mtitan
Generate code for AppliedMicro Titan core complex.
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/ppc.exp binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/ppc.exp 2017-06-23 17:46:07.285531055 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp 2017-06-23 17:54:18.847627054 +0300
@@ -61,6 +61,12 @@
run_dump_test "vle-simple-6"
run_dump_test "lsp"
run_dump_test "lsp-checks"
+ run_dump_test "spe2"
+ run_dump_test "spe2-checks"
+ run_dump_test "spe"
+
+ setup_xfail "*-*-*"
+ run_dump_test "spe_ambiguous"
}
}
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.d binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.d
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.d 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,4 @@
+#as: -mvle -mspe2
+#name: Test SPE2 operands checks
+#error-output: spe2-checks.l
+
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.l binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.l
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.l 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.l 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,73 @@
+[^:]*: Assembler messages:
+.*:29: Error: operand out of range \(32 is not between 0 and 31\)
+.*:30: Error: operand out of range \(32 is not between 0 and 31\)
+.*:31: Error: operand out of range \(32 is not between 0 and 31\)
+.*:32: Error: operand out of range \(32 is not between 0 and 31\)
+.*:33: Error: operand out of range \(8 is not between 0 and 7\)
+.*:34: Error: operand out of range \(8 is not between 0 and 7\)
+.*:35: Error: operand out of range \(4 is not between 0 and 3\)
+.*:36: Error: operand out of range \(8 is not between 0 and 7\)
+.*:37: Error: operand out of range \(4 is not between 0 and 3\)
+.*:38: Error: operand out of range \(16 is not between 0 and 15\)
+.*:39: Error: operand out of range \(16 is not between 0 and 15\)
+.*:40: Error: operand out of range \(16 is not between 0 and 15\)
+.*:41: Error: operand out of range \(4 is not between 0 and 3\)
+.*:42: Error: operand out of range \(4 is not between 0 and 3\)
+.*:43: Error: invalid offset
+.*:44: Error: operand out of range \(8 is not between 0 and 7\)
+.*:44: Error: invalid offset
+.*:45: Error: UIMM values >7 are illegal
+.*:46: Error: UIMM values >7 are illegal
+.*:47: Error: UIMM values >7 are illegal
+.*:48: Error: UIMM values >7 are illegal
+.*:49: Error: UIMM values >15 are illegal
+.*:50: Error: UIMM values >15 are illegal
+.*:51: Error: UIMM values >15 are illegal
+.*:52: Error: UIMM values >15 are illegal
+.*:53: Error: operand out of range \(8 is not between 0 and 7\)
+.*:54: Error: operand out of range \(8 is not between 0 and 7\)
+.*:55: Error: operand out of range \(8 is not between 0 and 7\)
+.*:56: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:57: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:58: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:59: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:60: Error: operand out of range \(32 is not between 0 and 31\)
+.*:61: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:62: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:63: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:64: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:65: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:66: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:67: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:68: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:69: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:70: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:71: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:72: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:73: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:74: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:75: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:76: Error: operand out of domain \(1 is not a multiple of 2\)
+.*:77: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:78: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:79: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:80: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:81: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:82: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:83: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:84: Error: UIMM = 00000 is illegal
+.*:85: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:86: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:87: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:88: Error: operand out of domain \(7 is not a multiple of 8\)
+.*:89: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:90: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:91: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:92: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:93: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:94: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:95: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:96: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:97: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:98: Error: operand out of domain \(3 is not a multiple of 4\)
+.*:99: Error: operand out of domain \(1 is not a multiple of 2\)
\ No newline at end of file
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.s binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.s
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2-checks.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2-checks.s 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,99 @@
+# PA SPE2 instructions
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ UIMM_ILL, 32
+ .equ UIMM_1_ZERO, 0
+ .equ UIMM_1_ILL, 32
+ .equ UIMM_2_ILL, 1
+ .equ UIMM_4_ILL, 3
+ .equ UIMM_8_ILL, 7
+ .equ UIMM_GT7, 8
+ .equ UIMM_GT15, 16
+ .equ nnn_ILL, 8
+ .equ bbb_ILL, 8
+ .equ dd, 3
+ .equ dd_ILL, 4
+ .equ Ddd, 7
+ .equ Ddd_ILL, 8
+ .equ hh, 3
+ .equ hh_ILL, 4
+ .equ mask_ILL, 16
+ .equ offset_ILL0, 0
+ .equ offset_ILL, 8
+
+
+ evaddib rD, rB, UIMM_ILL
+ evaddih rD, rB, UIMM_ILL
+ evsubifh rD, UIMM_ILL, rB
+ evsubifb rD, UIMM_ILL, rB
+ evinsb rD, rA, Ddd, bbb_ILL
+ evxtrb rD, rA, Ddd, bbb_ILL
+ evsplath rD, rA, hh_ILL
+ evsplatb rD, rA, bbb_ILL
+ evinsh rD, rA, dd_ILL, hh
+ evclrbe rD, rA, mask_ILL
+ evclrbo rD, rA, mask_ILL
+ evclrh rD, rA, mask_ILL
+ evxtrh rD, rA, dd_ILL, hh
+ evxtrh rD, rA, dd, hh_ILL
+ evxtrd rD, rA, rB, offset_ILL0
+ evxtrd rD, rA, rB, offset_ILL
+ evsrbiu rD, rA, UIMM_GT7
+ evsrbis rD, rA, UIMM_GT7
+ evslbi rD, rA, UIMM_GT7
+ evrlbi rD, rA, UIMM_GT7
+ evsrhiu rD, rA, UIMM_GT15
+ evsrhis rD, rA, UIMM_GT15
+ evslhi rD, rA, UIMM_GT15
+ evrlhi rD, rA, UIMM_GT15
+ evsroiu rD, rA, nnn_ILL
+ evsrois rD, rA, nnn_ILL
+ evsloi rD, rA, nnn_ILL
+ evldb rD, UIMM_8_ILL (rA)
+ evlhhsplath rD, UIMM_2_ILL (rA)
+ evlwbsplatw rD, UIMM_4_ILL (rA)
+ evlwhsplatw rD, UIMM_4_ILL (rA)
+ evlbbsplatb rD, UIMM_1_ILL (rA)
+ evstdb rS, UIMM_8_ILL (rA)
+ evlwbe rD, UIMM_4_ILL (rA)
+ evlwbou rD, UIMM_4_ILL (rA)
+ evlwbos rD, UIMM_4_ILL (rA)
+ evstwbe rS, UIMM_4_ILL (rA)
+ evstwbo rS, UIMM_4_ILL (rA)
+ evstwb rS, UIMM_4_ILL (rA)
+ evsthb rS, UIMM_2_ILL (rA)
+ evlddu rD, UIMM_8_ILL (rA)
+ evldwu rD, UIMM_8_ILL (rA)
+ evldhu rD, UIMM_8_ILL (rA)
+ evldbu rD, UIMM_8_ILL (rA)
+ evlhhesplatu rD, UIMM_2_ILL (rA)
+ evlhhsplathu rD, UIMM_2_ILL (rA)
+ evlhhousplatu rD, UIMM_2_ILL (rA)
+ evlhhossplatu rD, UIMM_2_ILL (rA)
+ evlwheu rD, UIMM_4_ILL (rA)
+ evlwbsplatwu rD, UIMM_4_ILL (rA)
+ evlwhouu rD, UIMM_4_ILL (rA)
+ evlwhosu rD, UIMM_4_ILL (rA)
+ evlwwsplatu rD, UIMM_4_ILL (rA)
+ evlwhsplatwu rD, UIMM_4_ILL (rA)
+ evlwhsplatu rD, UIMM_4_ILL (rA)
+ evlbbsplatbu rD, UIMM_1_ZERO (rA)
+ evstddu rS, UIMM_8_ILL (rA)
+ evstdwu rS, UIMM_8_ILL (rA)
+ evstdhu rS, UIMM_8_ILL (rA)
+ evstdbu rS, UIMM_8_ILL (rA)
+ evlwbeu rD, UIMM_4_ILL (rA)
+ evlwbouu rD, UIMM_4_ILL (rA)
+ evlwbosu rD, UIMM_4_ILL (rA)
+ evstwheu rS, UIMM_4_ILL (rA)
+ evstwbeu rS, UIMM_4_ILL (rA)
+ evstwhou rS, UIMM_4_ILL (rA)
+ evstwbou rS, UIMM_4_ILL (rA)
+ evstwweu rS, UIMM_4_ILL (rA)
+ evstwbu rS, UIMM_4_ILL (rA)
+ evstwwou rS, UIMM_4_ILL (rA)
+ evsthbu rS, UIMM_2_ILL (rA)
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2.d binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,815 @@
+#as: -mvle -mspe2
+#objdump: -d -Mspe2
+#name: Validate SPE2 instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 10 80 evdotpwcssi r0,r1,r2
+ 4: 10 01 10 81 evdotpwcsmi r0,r1,r2
+ 8: 10 01 10 82 evdotpwcssfr r0,r1,r2
+ c: 10 01 10 83 evdotpwcssf r0,r1,r2
+ 10: 10 01 10 88 evdotpwgasmf r0,r1,r2
+ 14: 10 01 10 89 evdotpwxgasmf r0,r1,r2
+ 18: 10 01 10 8a evdotpwgasmfr r0,r1,r2
+ 1c: 10 01 10 8b evdotpwxgasmfr r0,r1,r2
+ 20: 10 01 10 8c evdotpwgssmf r0,r1,r2
+ 24: 10 01 10 8d evdotpwxgssmf r0,r1,r2
+ 28: 10 01 10 8e evdotpwgssmfr r0,r1,r2
+ 2c: 10 01 10 8f evdotpwxgssmfr r0,r1,r2
+ 30: 10 01 10 90 evdotpwcssiaaw3 r0,r1,r2
+ 34: 10 01 10 91 evdotpwcsmiaaw3 r0,r1,r2
+ 38: 10 01 10 92 evdotpwcssfraaw3 r0,r1,r2
+ 3c: 10 01 10 93 evdotpwcssfaaw3 r0,r1,r2
+ 40: 10 01 10 98 evdotpwgasmfaa3 r0,r1,r2
+ 44: 10 01 10 99 evdotpwxgasmfaa3 r0,r1,r2
+ 48: 10 01 10 9a evdotpwgasmfraa3 r0,r1,r2
+ 4c: 10 01 10 9b evdotpwxgasmfraa3 r0,r1,r2
+ 50: 10 01 10 9c evdotpwgssmfaa3 r0,r1,r2
+ 54: 10 01 10 9d evdotpwxgssmfaa3 r0,r1,r2
+ 58: 10 01 10 9e evdotpwgssmfraa3 r0,r1,r2
+ 5c: 10 01 10 9f evdotpwxgssmfraa3 r0,r1,r2
+ 60: 10 01 10 a0 evdotpwcssia r0,r1,r2
+ 64: 10 01 10 a1 evdotpwcsmia r0,r1,r2
+ 68: 10 01 10 a2 evdotpwcssfra r0,r1,r2
+ 6c: 10 01 10 a3 evdotpwcssfa r0,r1,r2
+ 70: 10 01 10 a8 evdotpwgasmfa r0,r1,r2
+ 74: 10 01 10 a9 evdotpwxgasmfa r0,r1,r2
+ 78: 10 01 10 aa evdotpwgasmfra r0,r1,r2
+ 7c: 10 01 10 ab evdotpwxgasmfra r0,r1,r2
+ 80: 10 01 10 ac evdotpwgssmfa r0,r1,r2
+ 84: 10 01 10 ad evdotpwxgssmfa r0,r1,r2
+ 88: 10 01 10 ae evdotpwgssmfra r0,r1,r2
+ 8c: 10 01 10 af evdotpwxgssmfra r0,r1,r2
+ 90: 10 01 10 b0 evdotpwcssiaaw r0,r1,r2
+ 94: 10 01 10 b1 evdotpwcsmiaaw r0,r1,r2
+ 98: 10 01 10 b2 evdotpwcssfraaw r0,r1,r2
+ 9c: 10 01 10 b3 evdotpwcssfaaw r0,r1,r2
+ a0: 10 01 10 b8 evdotpwgasmfaa r0,r1,r2
+ a4: 10 01 10 b9 evdotpwxgasmfaa r0,r1,r2
+ a8: 10 01 10 ba evdotpwgasmfraa r0,r1,r2
+ ac: 10 01 10 bb evdotpwxgasmfraa r0,r1,r2
+ b0: 10 01 10 bc evdotpwgssmfaa r0,r1,r2
+ b4: 10 01 10 bd evdotpwxgssmfaa r0,r1,r2
+ b8: 10 01 10 be evdotpwgssmfraa r0,r1,r2
+ bc: 10 01 10 bf evdotpwxgssmfraa r0,r1,r2
+ c0: 10 01 11 00 evdotphihcssi r0,r1,r2
+ c4: 10 01 11 01 evdotplohcssi r0,r1,r2
+ c8: 10 01 11 02 evdotphihcssf r0,r1,r2
+ cc: 10 01 11 03 evdotplohcssf r0,r1,r2
+ d0: 10 01 11 08 evdotphihcsmi r0,r1,r2
+ d4: 10 01 11 09 evdotplohcsmi r0,r1,r2
+ d8: 10 01 11 0a evdotphihcssfr r0,r1,r2
+ dc: 10 01 11 0b evdotplohcssfr r0,r1,r2
+ e0: 10 01 11 10 evdotphihcssiaaw3 r0,r1,r2
+ e4: 10 01 11 11 evdotplohcssiaaw3 r0,r1,r2
+ e8: 10 01 11 12 evdotphihcssfaaw3 r0,r1,r2
+ ec: 10 01 11 13 evdotplohcssfaaw3 r0,r1,r2
+ f0: 10 01 11 18 evdotphihcsmiaaw3 r0,r1,r2
+ f4: 10 01 11 19 evdotplohcsmiaaw3 r0,r1,r2
+ f8: 10 01 11 1a evdotphihcssfraaw3 r0,r1,r2
+ fc: 10 01 11 1b evdotplohcssfraaw3 r0,r1,r2
+ 100: 10 01 11 20 evdotphihcssia r0,r1,r2
+ 104: 10 01 11 21 evdotplohcssia r0,r1,r2
+ 108: 10 01 11 22 evdotphihcssfa r0,r1,r2
+ 10c: 10 01 11 23 evdotplohcssfa r0,r1,r2
+ 110: 10 01 11 28 evdotphihcsmia r0,r1,r2
+ 114: 10 01 11 29 evdotplohcsmia r0,r1,r2
+ 118: 10 01 11 2a evdotphihcssfra r0,r1,r2
+ 11c: 10 01 11 2b evdotplohcssfra r0,r1,r2
+ 120: 10 01 11 30 evdotphihcssiaaw r0,r1,r2
+ 124: 10 01 11 31 evdotplohcssiaaw r0,r1,r2
+ 128: 10 01 11 32 evdotphihcssfaaw r0,r1,r2
+ 12c: 10 01 11 33 evdotplohcssfaaw r0,r1,r2
+ 130: 10 01 11 38 evdotphihcsmiaaw r0,r1,r2
+ 134: 10 01 11 39 evdotplohcsmiaaw r0,r1,r2
+ 138: 10 01 11 3a evdotphihcssfraaw r0,r1,r2
+ 13c: 10 01 11 3b evdotplohcssfraaw r0,r1,r2
+ 140: 10 01 11 40 evdotphausi r0,r1,r2
+ 144: 10 01 11 41 evdotphassi r0,r1,r2
+ 148: 10 01 11 42 evdotphasusi r0,r1,r2
+ 14c: 10 01 11 43 evdotphassf r0,r1,r2
+ 150: 10 01 11 47 evdotphsssf r0,r1,r2
+ 154: 10 01 11 48 evdotphaumi r0,r1,r2
+ 158: 10 01 11 49 evdotphasmi r0,r1,r2
+ 15c: 10 01 11 4a evdotphasumi r0,r1,r2
+ 160: 10 01 11 4b evdotphassfr r0,r1,r2
+ 164: 10 01 11 4d evdotphssmi r0,r1,r2
+ 168: 10 01 11 4f evdotphsssfr r0,r1,r2
+ 16c: 10 01 11 50 evdotphausiaaw3 r0,r1,r2
+ 170: 10 01 11 51 evdotphassiaaw3 r0,r1,r2
+ 174: 10 01 11 52 evdotphasusiaaw3 r0,r1,r2
+ 178: 10 01 11 53 evdotphassfaaw3 r0,r1,r2
+ 17c: 10 01 11 55 evdotphsssiaaw3 r0,r1,r2
+ 180: 10 01 11 57 evdotphsssfaaw3 r0,r1,r2
+ 184: 10 01 11 58 evdotphaumiaaw3 r0,r1,r2
+ 188: 10 01 11 59 evdotphasmiaaw3 r0,r1,r2
+ 18c: 10 01 11 5a evdotphasumiaaw3 r0,r1,r2
+ 190: 10 01 11 5b evdotphassfraaw3 r0,r1,r2
+ 194: 10 01 11 5d evdotphssmiaaw3 r0,r1,r2
+ 198: 10 01 11 5f evdotphsssfraaw3 r0,r1,r2
+ 19c: 10 01 11 60 evdotphausia r0,r1,r2
+ 1a0: 10 01 11 61 evdotphassia r0,r1,r2
+ 1a4: 10 01 11 62 evdotphasusia r0,r1,r2
+ 1a8: 10 01 11 63 evdotphassfa r0,r1,r2
+ 1ac: 10 01 11 67 evdotphsssfa r0,r1,r2
+ 1b0: 10 01 11 68 evdotphaumia r0,r1,r2
+ 1b4: 10 01 11 69 evdotphasmia r0,r1,r2
+ 1b8: 10 01 11 6a evdotphasumia r0,r1,r2
+ 1bc: 10 01 11 6b evdotphassfra r0,r1,r2
+ 1c0: 10 01 11 6d evdotphssmia r0,r1,r2
+ 1c4: 10 01 11 6f evdotphsssfra r0,r1,r2
+ 1c8: 10 01 11 70 evdotphausiaaw r0,r1,r2
+ 1cc: 10 01 11 71 evdotphassiaaw r0,r1,r2
+ 1d0: 10 01 11 72 evdotphasusiaaw r0,r1,r2
+ 1d4: 10 01 11 73 evdotphassfaaw r0,r1,r2
+ 1d8: 10 01 11 75 evdotphsssiaaw r0,r1,r2
+ 1dc: 10 01 11 77 evdotphsssfaaw r0,r1,r2
+ 1e0: 10 01 11 78 evdotphaumiaaw r0,r1,r2
+ 1e4: 10 01 11 79 evdotphasmiaaw r0,r1,r2
+ 1e8: 10 01 11 7a evdotphasumiaaw r0,r1,r2
+ 1ec: 10 01 11 7b evdotphassfraaw r0,r1,r2
+ 1f0: 10 01 11 7d evdotphssmiaaw r0,r1,r2
+ 1f4: 10 01 11 7f evdotphsssfraaw r0,r1,r2
+ 1f8: 10 01 11 80 evdotp4hgaumi r0,r1,r2
+ 1fc: 10 01 11 81 evdotp4hgasmi r0,r1,r2
+ 200: 10 01 11 82 evdotp4hgasumi r0,r1,r2
+ 204: 10 01 11 83 evdotp4hgasmf r0,r1,r2
+ 208: 10 01 11 84 evdotp4hgssmi r0,r1,r2
+ 20c: 10 01 11 85 evdotp4hgssmf r0,r1,r2
+ 210: 10 01 11 86 evdotp4hxgasmi r0,r1,r2
+ 214: 10 01 11 87 evdotp4hxgasmf r0,r1,r2
+ 218: 10 01 11 88 evdotpbaumi r0,r1,r2
+ 21c: 10 01 11 89 evdotpbasmi r0,r1,r2
+ 220: 10 01 11 8a evdotpbasumi r0,r1,r2
+ 224: 10 01 11 8e evdotp4hxgssmi r0,r1,r2
+ 228: 10 01 11 8f evdotp4hxgssmf r0,r1,r2
+ 22c: 10 01 11 90 evdotp4hgaumiaa3 r0,r1,r2
+ 230: 10 01 11 91 evdotp4hgasmiaa3 r0,r1,r2
+ 234: 10 01 11 92 evdotp4hgasumiaa3 r0,r1,r2
+ 238: 10 01 11 93 evdotp4hgasmfaa3 r0,r1,r2
+ 23c: 10 01 11 94 evdotp4hgssmiaa3 r0,r1,r2
+ 240: 10 01 11 95 evdotp4hgssmfaa3 r0,r1,r2
+ 244: 10 01 11 96 evdotp4hxgasmiaa3 r0,r1,r2
+ 248: 10 01 11 97 evdotp4hxgasmfaa3 r0,r1,r2
+ 24c: 10 01 11 98 evdotpbaumiaaw3 r0,r1,r2
+ 250: 10 01 11 99 evdotpbasmiaaw3 r0,r1,r2
+ 254: 10 01 11 9a evdotpbasumiaaw3 r0,r1,r2
+ 258: 10 01 11 9e evdotp4hxgssmiaa3 r0,r1,r2
+ 25c: 10 01 11 9f evdotp4hxgssmfaa3 r0,r1,r2
+ 260: 10 01 11 a0 evdotp4hgaumia r0,r1,r2
+ 264: 10 01 11 a1 evdotp4hgasmia r0,r1,r2
+ 268: 10 01 11 a2 evdotp4hgasumia r0,r1,r2
+ 26c: 10 01 11 a3 evdotp4hgasmfa r0,r1,r2
+ 270: 10 01 11 a4 evdotp4hgssmia r0,r1,r2
+ 274: 10 01 11 a5 evdotp4hgssmfa r0,r1,r2
+ 278: 10 01 11 a6 evdotp4hxgasmia r0,r1,r2
+ 27c: 10 01 11 a7 evdotp4hxgasmfa r0,r1,r2
+ 280: 10 01 11 a8 evdotpbaumia r0,r1,r2
+ 284: 10 01 11 a9 evdotpbasmia r0,r1,r2
+ 288: 10 01 11 aa evdotpbasumia r0,r1,r2
+ 28c: 10 01 11 ae evdotp4hxgssmia r0,r1,r2
+ 290: 10 01 11 af evdotp4hxgssmfa r0,r1,r2
+ 294: 10 01 11 b0 evdotp4hgaumiaa r0,r1,r2
+ 298: 10 01 11 b1 evdotp4hgasmiaa r0,r1,r2
+ 29c: 10 01 11 b2 evdotp4hgasumiaa r0,r1,r2
+ 2a0: 10 01 11 b3 evdotp4hgasmfaa r0,r1,r2
+ 2a4: 10 01 11 b4 evdotp4hgssmiaa r0,r1,r2
+ 2a8: 10 01 11 b5 evdotp4hgssmfaa r0,r1,r2
+ 2ac: 10 01 11 b6 evdotp4hxgasmiaa r0,r1,r2
+ 2b0: 10 01 11 b7 evdotp4hxgasmfaa r0,r1,r2
+ 2b4: 10 01 11 b8 evdotpbaumiaaw r0,r1,r2
+ 2b8: 10 01 11 b9 evdotpbasmiaaw r0,r1,r2
+ 2bc: 10 01 11 ba evdotpbasumiaaw r0,r1,r2
+ 2c0: 10 01 11 be evdotp4hxgssmiaa r0,r1,r2
+ 2c4: 10 01 11 bf evdotp4hxgssmfaa r0,r1,r2
+ 2c8: 10 01 11 c0 evdotpwausi r0,r1,r2
+ 2cc: 10 01 11 c1 evdotpwassi r0,r1,r2
+ 2d0: 10 01 11 c2 evdotpwasusi r0,r1,r2
+ 2d4: 10 01 11 c8 evdotpwaumi r0,r1,r2
+ 2d8: 10 01 11 c9 evdotpwasmi r0,r1,r2
+ 2dc: 10 01 11 ca evdotpwasumi r0,r1,r2
+ 2e0: 10 01 11 cd evdotpwssmi r0,r1,r2
+ 2e4: 10 01 11 d0 evdotpwausiaa3 r0,r1,r2
+ 2e8: 10 01 11 d1 evdotpwassiaa3 r0,r1,r2
+ 2ec: 10 01 11 d2 evdotpwasusiaa3 r0,r1,r2
+ 2f0: 10 01 11 d5 evdotpwsssiaa3 r0,r1,r2
+ 2f4: 10 01 11 d8 evdotpwaumiaa3 r0,r1,r2
+ 2f8: 10 01 11 d9 evdotpwasmiaa3 r0,r1,r2
+ 2fc: 10 01 11 da evdotpwasumiaa3 r0,r1,r2
+ 300: 10 01 11 dd evdotpwssmiaa3 r0,r1,r2
+ 304: 10 01 11 e0 evdotpwausia r0,r1,r2
+ 308: 10 01 11 e1 evdotpwassia r0,r1,r2
+ 30c: 10 01 11 e2 evdotpwasusia r0,r1,r2
+ 310: 10 01 11 e8 evdotpwaumia r0,r1,r2
+ 314: 10 01 11 e9 evdotpwasmia r0,r1,r2
+ 318: 10 01 11 ea evdotpwasumia r0,r1,r2
+ 31c: 10 01 11 ed evdotpwssmia r0,r1,r2
+ 320: 10 01 11 f0 evdotpwausiaa r0,r1,r2
+ 324: 10 01 11 f1 evdotpwassiaa r0,r1,r2
+ 328: 10 01 11 f2 evdotpwasusiaa r0,r1,r2
+ 32c: 10 01 11 f5 evdotpwsssiaa r0,r1,r2
+ 330: 10 01 11 f8 evdotpwaumiaa r0,r1,r2
+ 334: 10 01 11 f9 evdotpwasmiaa r0,r1,r2
+ 338: 10 01 11 fa evdotpwasumiaa r0,r1,r2
+ 33c: 10 01 11 fd evdotpwssmiaa r0,r1,r2
+ 340: 10 1f 12 03 evaddib r0,r2,31
+ 344: 10 1f 12 01 evaddih r0,r2,31
+ 348: 10 1f 12 05 evsubifh r0,31,r2
+ 34c: 10 1f 12 07 evsubifb r0,31,r2
+ 350: 10 01 12 08 evabsb r0,r1
+ 354: 10 01 22 08 evabsh r0,r1
+ 358: 10 01 32 08 evabsd r0,r1
+ 35c: 10 01 42 08 evabss r0,r1
+ 360: 10 01 52 08 evabsbs r0,r1
+ 364: 10 01 62 08 evabshs r0,r1
+ 368: 10 01 72 08 evabsds r0,r1
+ 36c: 10 01 0a 09 evnegwo r0,r1
+ 370: 10 01 12 09 evnegb r0,r1
+ 374: 10 01 1a 09 evnegbo r0,r1
+ 378: 10 01 22 09 evnegh r0,r1
+ 37c: 10 01 2a 09 evnegho r0,r1
+ 380: 10 01 32 09 evnegd r0,r1
+ 384: 10 01 42 09 evnegs r0,r1
+ 388: 10 01 4a 09 evnegwos r0,r1
+ 38c: 10 01 52 09 evnegbs r0,r1
+ 390: 10 01 5a 09 evnegbos r0,r1
+ 394: 10 01 62 09 evneghs r0,r1
+ 398: 10 01 6a 09 evneghos r0,r1
+ 39c: 10 01 72 09 evnegds r0,r1
+ 3a0: 10 01 0a 0a evextzb r0,r1
+ 3a4: 10 01 22 0a evextsbh r0,r1
+ 3a8: 10 01 32 0b evextsw r0,r1
+ 3ac: 10 01 02 0c evrndwh r0,r1
+ 3b0: 10 01 22 0c evrndhb r0,r1
+ 3b4: 10 01 32 0c evrnddw r0,r1
+ 3b8: 10 01 42 0c evrndwhus r0,r1
+ 3bc: 10 01 4a 0c evrndwhss r0,r1
+ 3c0: 10 01 62 0c evrndhbus r0,r1
+ 3c4: 10 01 6a 0c evrndhbss r0,r1
+ 3c8: 10 01 72 0c evrnddwus r0,r1
+ 3cc: 10 01 7a 0c evrnddwss r0,r1
+ 3d0: 10 01 82 0c evrndwnh r0,r1
+ 3d4: 10 01 a2 0c evrndhnb r0,r1
+ 3d8: 10 01 b2 0c evrnddnw r0,r1
+ 3dc: 10 01 c2 0c evrndwnhus r0,r1
+ 3e0: 10 01 ca 0c evrndwnhss r0,r1
+ 3e4: 10 01 e2 0c evrndhnbus r0,r1
+ 3e8: 10 01 ea 0c evrndhnbss r0,r1
+ 3ec: 10 01 f2 0c evrnddnwus r0,r1
+ 3f0: 10 01 fa 0c evrnddnwss r0,r1
+ 3f4: 10 01 22 0d evcntlzh r0,r1
+ 3f8: 10 01 22 0e evcntlsh r0,r1
+ 3fc: 10 01 d2 0e evpopcntb r0,r1
+ 400: 10 01 12 10 circinc r0,r1,r2
+ 404: 10 01 02 1c evunpkhibui r0,r1
+ 408: 10 01 0a 1c evunpkhibsi r0,r1
+ 40c: 10 01 12 1c evunpkhihui r0,r1
+ 410: 10 01 1a 1c evunpkhihsi r0,r1
+ 414: 10 01 22 1c evunpklobui r0,r1
+ 418: 10 01 2a 1c evunpklobsi r0,r1
+ 41c: 10 01 32 1c evunpklohui r0,r1
+ 420: 10 01 3a 1c evunpklohsi r0,r1
+ 424: 10 01 42 1c evunpklohf r0,r1
+ 428: 10 01 4a 1c evunpkhihf r0,r1
+ 42c: 10 01 62 1c evunpklowgsf r0,r1
+ 430: 10 01 6a 1c evunpkhiwgsf r0,r1
+ 434: 10 01 82 1c evsatsduw r0,r1
+ 438: 10 01 8a 1c evsatsdsw r0,r1
+ 43c: 10 01 92 1c evsatshub r0,r1
+ 440: 10 01 9a 1c evsatshsb r0,r1
+ 444: 10 01 a2 1c evsatuwuh r0,r1
+ 448: 10 01 aa 1c evsatswsh r0,r1
+ 44c: 10 01 b2 1c evsatswuh r0,r1
+ 450: 10 01 ba 1c evsatuhub r0,r1
+ 454: 10 01 c2 1c evsatuduw r0,r1
+ 458: 10 01 ca 1c evsatuwsw r0,r1
+ 45c: 10 01 d2 1c evsatshuh r0,r1
+ 460: 10 01 da 1c evsatuhsh r0,r1
+ 464: 10 01 e2 1c evsatswuw r0,r1
+ 468: 10 01 ea 1c evsatswgsdf r0,r1
+ 46c: 10 01 f2 1c evsatsbub r0,r1
+ 470: 10 01 fa 1c evsatubsb r0,r1
+ 474: 10 01 02 1d evmaxhpuw r0,r1
+ 478: 10 01 0a 1d evmaxhpsw r0,r1
+ 47c: 10 01 22 1d evmaxbpuh r0,r1
+ 480: 10 01 2a 1d evmaxbpsh r0,r1
+ 484: 10 01 32 1d evmaxwpud r0,r1
+ 488: 10 01 3a 1d evmaxwpsd r0,r1
+ 48c: 10 01 42 1d evminhpuw r0,r1
+ 490: 10 01 4a 1d evminhpsw r0,r1
+ 494: 10 01 62 1d evminbpuh r0,r1
+ 498: 10 01 6a 1d evminbpsh r0,r1
+ 49c: 10 01 72 1d evminwpud r0,r1
+ 4a0: 10 01 7a 1d evminwpsd r0,r1
+ 4a4: 10 01 12 1f evmaxmagws r0,r1,r2
+ 4a8: 10 01 12 25 evsl r0,r1,r2
+ 4ac: 10 01 fa 27 evsli r0,r1,31
+ 4b0: 10 10 0a 29 evsplatie r0,-16
+ 4b4: 10 10 12 29 evsplatib r0,-16
+ 4b8: 10 10 1a 29 evsplatibe r0,-16
+ 4bc: 10 10 22 29 evsplatih r0,-16
+ 4c0: 10 10 2a 29 evsplatihe r0,-16
+ 4c4: 10 10 32 29 evsplatid r0,-16
+ 4c8: 10 10 82 29 evsplatia r0,-16
+ 4cc: 10 10 8a 29 evsplatiea r0,-16
+ 4d0: 10 10 92 29 evsplatiba r0,-16
+ 4d4: 10 10 9a 29 evsplatibea r0,-16
+ 4d8: 10 10 a2 29 evsplatiha r0,-16
+ 4dc: 10 10 aa 29 evsplatihea r0,-16
+ 4e0: 10 10 b2 29 evsplatida r0,-16
+ 4e4: 10 10 0a 2b evsplatfio r0,-16
+ 4e8: 10 10 12 2b evsplatfib r0,-16
+ 4ec: 10 10 1a 2b evsplatfibo r0,-16
+ 4f0: 10 10 22 2b evsplatfih r0,-16
+ 4f4: 10 10 2a 2b evsplatfiho r0,-16
+ 4f8: 10 10 32 2b evsplatfid r0,-16
+ 4fc: 10 10 82 2b evsplatfia r0,-16
+ 500: 10 10 8a 2b evsplatfioa r0,-16
+ 504: 10 10 92 2b evsplatfiba r0,-16
+ 508: 10 10 9a 2b evsplatfiboa r0,-16
+ 50c: 10 10 a2 2b evsplatfiha r0,-16
+ 510: 10 10 aa 2b evsplatfihoa r0,-16
+ 514: 10 10 b2 2b evsplatfida r0,-16
+ 518: 10 21 12 30 evcmpgtdu cr0,r1,r2
+ 51c: 10 21 12 31 evcmpgtds cr0,r1,r2
+ 520: 10 21 12 32 evcmpltdu cr0,r1,r2
+ 524: 10 21 12 33 evcmpltds cr0,r1,r2
+ 528: 10 21 12 34 evcmpeqd cr0,r1,r2
+ 52c: 10 01 12 38 evswapbhilo r0,r1,r2
+ 530: 10 01 12 39 evswapblohi r0,r1,r2
+ 534: 10 01 12 3a evswaphhilo r0,r1,r2
+ 538: 10 01 12 3b evswaphlohi r0,r1,r2
+ 53c: 10 01 12 3c evswaphe r0,r1,r2
+ 540: 10 01 12 3d evswaphhi r0,r1,r2
+ 544: 10 01 12 3e evswaphlo r0,r1,r2
+ 548: 10 01 12 3f evswapho r0,r1,r2
+ 54c: 10 01 fa 49 evinsb r0,r1,7,7
+ 550: 10 01 fa 4b evxtrb r0,r1,7,7
+ 554: 10 01 62 4c evsplath r0,r1,3
+ 558: 10 01 f2 4c evsplatb r0,r1,7
+ 55c: 10 01 7a 4d evinsh r0,r1,3,3
+ 560: 10 01 7a 4e evclrbe r0,r1,15
+ 564: 10 01 fa 4e evclrbo r0,r1,15
+ 568: 10 01 fa 4f evclrh r0,r1,15
+ 56c: 10 01 7a 4f evxtrh r0,r1,3,3
+ 570: 10 01 12 50 evselbitm0 r0,r1,r2
+ 574: 10 01 12 51 evselbitm1 r0,r1,r2
+ 578: 10 01 12 52 evselbit r0,r1,r2
+ 57c: 10 01 12 54 evperm r0,r1,r2
+ 580: 10 01 12 55 evperm2 r0,r1,r2
+ 584: 10 01 12 56 evperm3 r0,r1,r2
+ 588: 10 01 12 5f evxtrd r0,r1,r2,7
+ 58c: 10 01 12 60 evsrbu r0,r1,r2
+ 590: 10 01 12 61 evsrbs r0,r1,r2
+ 594: 10 01 3a 62 evsrbiu r0,r1,7
+ 598: 10 01 3a 63 evsrbis r0,r1,7
+ 59c: 10 01 12 64 evslb r0,r1,r2
+ 5a0: 10 01 12 65 evrlb r0,r1,r2
+ 5a4: 10 01 3a 66 evslbi r0,r1,7
+ 5a8: 10 01 3a 67 evrlbi r0,r1,7
+ 5ac: 10 01 12 68 evsrhu r0,r1,r2
+ 5b0: 10 01 12 69 evsrhs r0,r1,r2
+ 5b4: 10 01 7a 6a evsrhiu r0,r1,15
+ 5b8: 10 01 7a 6b evsrhis r0,r1,15
+ 5bc: 10 01 12 6c evslh r0,r1,r2
+ 5c0: 10 01 12 6d evrlh r0,r1,r2
+ 5c4: 10 01 7a 6e evslhi r0,r1,15
+ 5c8: 10 01 7a 6f evrlhi r0,r1,15
+ 5cc: 10 01 12 70 evsru r0,r1,r2
+ 5d0: 10 01 12 71 evsrs r0,r1,r2
+ 5d4: 10 01 fa 72 evsriu r0,r1,31
+ 5d8: 10 01 fa 73 evsris r0,r1,31
+ 5dc: 10 01 12 74 evlvsl r0,r1,r2
+ 5e0: 10 01 12 75 evlvsr r0,r1,r2
+ 5e4: 10 01 3a 77 evsroiu r0,r1,7
+ 5e8: 10 01 7a 77 evsrois r0,r1,7
+ 5ec: 10 01 ba 77 evsloi r0,r1,7
+ 5f0: 10 01 02 87 evfssqrt r0,r1
+ 5f4: 10 04 12 91 evfscfh r0,r2
+ 5f8: 10 04 12 95 evfscth r0,r2
+ 5fc: 10 01 12 a0 evfsmax r0,r1,r2
+ 600: 10 01 12 a1 evfsmin r0,r1,r2
+ 604: 10 01 12 a2 evfsaddsub r0,r1,r2
+ 608: 10 01 12 a3 evfssubadd r0,r1,r2
+ 60c: 10 01 12 a4 evfssum r0,r1,r2
+ 610: 10 01 12 a5 evfsdiff r0,r1,r2
+ 614: 10 01 12 a6 evfssumdiff r0,r1,r2
+ 618: 10 01 12 a7 evfsdiffsum r0,r1,r2
+ 61c: 10 01 12 a8 evfsaddx r0,r1,r2
+ 620: 10 01 12 a9 evfssubx r0,r1,r2
+ 624: 10 01 12 aa evfsaddsubx r0,r1,r2
+ 628: 10 01 12 ab evfssubaddx r0,r1,r2
+ 62c: 10 01 12 ac evfsmulx r0,r1,r2
+ 630: 10 01 12 ae evfsmule r0,r1,r2
+ 634: 10 01 12 af evfsmulo r0,r1,r2
+ 638: 10 01 13 06 evldbx r0,r1,r2
+ 63c: 10 01 0b 07 evldb r0,8\(r1\)
+ 640: 10 01 13 0a evlhhsplathx r0,r1,r2
+ 644: 10 01 0b 0b evlhhsplath r0,2\(r1\)
+ 648: 10 01 13 12 evlwbsplatwx r0,r1,r2
+ 64c: 10 01 0b 13 evlwbsplatw r0,4\(r1\)
+ 650: 10 01 13 1a evlwhsplatwx r0,r1,r2
+ 654: 10 01 0b 1b evlwhsplatw r0,4\(r1\)
+ 658: 10 01 13 1e evlbbsplatbx r0,r1,r2
+ 65c: 10 01 0b 1f evlbbsplatb r0,1\(r1\)
+ 660: 10 01 13 26 evstdbx r0,r1,r2
+ 664: 10 01 0b 27 evstdb r0,8\(r1\)
+ 668: 10 01 13 2a evlwbex r0,r1,r2
+ 66c: 10 01 0b 2b evlwbe r0,4\(r1\)
+ 670: 10 01 13 2c evlwboux r0,r1,r2
+ 674: 10 01 0b 2d evlwbou r0,4\(r1\)
+ 678: 10 01 13 2e evlwbosx r0,r1,r2
+ 67c: 10 01 0b 2f evlwbos r0,4\(r1\)
+ 680: 10 01 13 32 evstwbex r0,r1,r2
+ 684: 10 01 0b 33 evstwbe r0,4\(r1\)
+ 688: 10 01 13 36 evstwbox r0,r1,r2
+ 68c: 10 01 0b 37 evstwbo r0,4\(r1\)
+ 690: 10 01 13 3a evstwbx r0,r1,r2
+ 694: 10 01 0b 3b evstwb r0,4\(r1\)
+ 698: 10 01 13 3e evsthbx r0,r1,r2
+ 69c: 10 01 0b 3f evsthb r0,2\(r1\)
+ 6a0: 10 01 13 40 evlddmx r0,r1,r2
+ 6a4: 10 01 0b 41 evlddu r0,8\(r1\)
+ 6a8: 10 01 13 42 evldwmx r0,r1,r2
+ 6ac: 10 01 0b 43 evldwu r0,8\(r1\)
+ 6b0: 10 01 13 44 evldhmx r0,r1,r2
+ 6b4: 10 01 0b 45 evldhu r0,8\(r1\)
+ 6b8: 10 01 13 46 evldbmx r0,r1,r2
+ 6bc: 10 01 0b 47 evldbu r0,8\(r1\)
+ 6c0: 10 01 13 48 evlhhesplatmx r0,r1,r2
+ 6c4: 10 01 0b 49 evlhhesplatu r0,2\(r1\)
+ 6c8: 10 01 13 4a evlhhsplathmx r0,r1,r2
+ 6cc: 10 01 0b 4b evlhhsplathu r0,2\(r1\)
+ 6d0: 10 01 13 4c evlhhousplatmx r0,r1,r2
+ 6d4: 10 01 0b 4d evlhhousplatu r0,2\(r1\)
+ 6d8: 10 01 13 4e evlhhossplatmx r0,r1,r2
+ 6dc: 10 01 0b 4f evlhhossplatu r0,2\(r1\)
+ 6e0: 10 01 13 50 evlwhemx r0,r1,r2
+ 6e4: 10 01 0b 51 evlwheu r0,4\(r1\)
+ 6e8: 10 01 13 52 evlwbsplatwmx r0,r1,r2
+ 6ec: 10 01 0b 53 evlwbsplatwu r0,4\(r1\)
+ 6f0: 10 01 13 54 evlwhoumx r0,r1,r2
+ 6f4: 10 01 0b 55 evlwhouu r0,4\(r1\)
+ 6f8: 10 01 13 56 evlwhosmx r0,r1,r2
+ 6fc: 10 01 0b 57 evlwhosu r0,4\(r1\)
+ 700: 10 01 13 58 evlwwsplatmx r0,r1,r2
+ 704: 10 01 0b 59 evlwwsplatu r0,4\(r1\)
+ 708: 10 01 13 5a evlwhsplatwmx r0,r1,r2
+ 70c: 10 01 0b 5b evlwhsplatwu r0,4\(r1\)
+ 710: 10 01 13 5c evlwhsplatmx r0,r1,r2
+ 714: 10 01 0b 5d evlwhsplatu r0,4\(r1\)
+ 718: 10 01 13 5e evlbbsplatbmx r0,r1,r2
+ 71c: 10 01 0b 5f evlbbsplatbu r0,1\(r1\)
+ 720: 10 01 13 60 evstddmx r0,r1,r2
+ 724: 10 01 0b 61 evstddu r0,8\(r1\)
+ 728: 10 01 13 62 evstdwmx r0,r1,r2
+ 72c: 10 01 0b 63 evstdwu r0,8\(r1\)
+ 730: 10 01 13 64 evstdhmx r0,r1,r2
+ 734: 10 01 0b 65 evstdhu r0,8\(r1\)
+ 738: 10 01 13 66 evstdbmx r0,r1,r2
+ 73c: 10 01 0b 67 evstdbu r0,8\(r1\)
+ 740: 10 01 13 6a evlwbemx r0,r1,r2
+ 744: 10 01 0b 6b evlwbeu r0,4\(r1\)
+ 748: 10 01 13 6c evlwboumx r0,r1,r2
+ 74c: 10 01 0b 6d evlwbouu r0,4\(r1\)
+ 750: 10 01 13 6e evlwbosmx r0,r1,r2
+ 754: 10 01 0b 6f evlwbosu r0,4\(r1\)
+ 758: 10 01 13 70 evstwhemx r0,r1,r2
+ 75c: 10 01 0b 71 evstwheu r0,4\(r1\)
+ 760: 10 01 13 72 evstwbemx r0,r1,r2
+ 764: 10 01 0b 73 evstwbeu r0,4\(r1\)
+ 768: 10 01 13 74 evstwhomx r0,r1,r2
+ 76c: 10 01 0b 75 evstwhou r0,4\(r1\)
+ 770: 10 01 13 76 evstwbomx r0,r1,r2
+ 774: 10 01 0b 77 evstwbou r0,4\(r1\)
+ 778: 10 01 13 78 evstwwemx r0,r1,r2
+ 77c: 10 01 0b 79 evstwweu r0,4\(r1\)
+ 780: 10 01 13 7a evstwbmx r0,r1,r2
+ 784: 10 01 0b 7b evstwbu r0,4\(r1\)
+ 788: 10 01 13 7c evstwwomx r0,r1,r2
+ 78c: 10 01 0b 7d evstwwou r0,4\(r1\)
+ 790: 10 01 13 7e evsthbmx r0,r1,r2
+ 794: 10 01 0b 7f evsthbu r0,2\(r1\)
+ 798: 10 01 14 00 evmhusi r0,r1,r2
+ 79c: 10 01 14 01 evmhssi r0,r1,r2
+ 7a0: 10 01 14 02 evmhsusi r0,r1,r2
+ 7a4: 10 01 14 04 evmhssf r0,r1,r2
+ 7a8: 10 01 14 05 evmhumi r0,r1,r2
+ 7ac: 10 01 14 06 evmhssfr r0,r1,r2
+ 7b0: 10 01 14 0a evmhesumi r0,r1,r2
+ 7b4: 10 01 14 0e evmhosumi r0,r1,r2
+ 7b8: 10 01 14 18 evmbeumi r0,r1,r2
+ 7bc: 10 01 14 19 evmbesmi r0,r1,r2
+ 7c0: 10 01 14 1a evmbesumi r0,r1,r2
+ 7c4: 10 01 14 1c evmboumi r0,r1,r2
+ 7c8: 10 01 14 1d evmbosmi r0,r1,r2
+ 7cc: 10 01 14 1e evmbosumi r0,r1,r2
+ 7d0: 10 01 14 2a evmhesumia r0,r1,r2
+ 7d4: 10 01 14 2e evmhosumia r0,r1,r2
+ 7d8: 10 01 14 38 evmbeumia r0,r1,r2
+ 7dc: 10 01 14 39 evmbesmia r0,r1,r2
+ 7e0: 10 01 14 3a evmbesumia r0,r1,r2
+ 7e4: 10 01 14 3c evmboumia r0,r1,r2
+ 7e8: 10 01 14 3d evmbosmia r0,r1,r2
+ 7ec: 10 01 14 3e evmbosumia r0,r1,r2
+ 7f0: 10 01 14 40 evmwusiw r0,r1,r2
+ 7f4: 10 01 14 41 evmwssiw r0,r1,r2
+ 7f8: 10 01 14 46 evmwhssfr r0,r1,r2
+ 7fc: 10 01 14 56 evmwehgsmfr r0,r1,r2
+ 800: 10 01 14 57 evmwehgsmf r0,r1,r2
+ 804: 10 01 14 5e evmwohgsmfr r0,r1,r2
+ 808: 10 01 14 5f evmwohgsmf r0,r1,r2
+ 80c: 10 01 14 66 evmwhssfra r0,r1,r2
+ 810: 10 01 14 76 evmwehgsmfra r0,r1,r2
+ 814: 10 01 14 77 evmwehgsmfa r0,r1,r2
+ 818: 10 01 14 7e evmwohgsmfra r0,r1,r2
+ 81c: 10 01 14 7f evmwohgsmfa r0,r1,r2
+ 820: 10 01 04 80 evaddusiaa r0,r1
+ 824: 10 01 04 81 evaddssiaa r0,r1
+ 828: 10 01 04 82 evsubfusiaa r0,r1
+ 82c: 10 01 04 83 evsubfssiaa r0,r1
+ 830: 10 01 04 84 evaddsmiaa r0,r1
+ 834: 10 01 04 86 evsubfsmiaa r0,r1
+ 838: 10 01 14 88 evaddh r0,r1,r2
+ 83c: 10 01 14 89 evaddhss r0,r1,r2
+ 840: 10 01 14 8a evsubfh r0,r1,r2
+ 844: 10 01 14 8b evsubfhss r0,r1,r2
+ 848: 10 01 14 8c evaddhx r0,r1,r2
+ 84c: 10 01 14 8d evaddhxss r0,r1,r2
+ 850: 10 01 14 8e evsubfhx r0,r1,r2
+ 854: 10 01 14 8f evsubfhxss r0,r1,r2
+ 858: 10 01 14 90 evaddd r0,r1,r2
+ 85c: 10 01 14 91 evadddss r0,r1,r2
+ 860: 10 01 14 92 evsubfd r0,r1,r2
+ 864: 10 01 14 93 evsubfdss r0,r1,r2
+ 868: 10 01 14 94 evaddb r0,r1,r2
+ 86c: 10 01 14 95 evaddbss r0,r1,r2
+ 870: 10 01 14 96 evsubfb r0,r1,r2
+ 874: 10 01 14 97 evsubfbss r0,r1,r2
+ 878: 10 01 14 98 evaddsubfh r0,r1,r2
+ 87c: 10 01 14 99 evaddsubfhss r0,r1,r2
+ 880: 10 01 14 9a evsubfaddh r0,r1,r2
+ 884: 10 01 14 9b evsubfaddhss r0,r1,r2
+ 888: 10 01 14 9c evaddsubfhx r0,r1,r2
+ 88c: 10 01 14 9d evaddsubfhxss r0,r1,r2
+ 890: 10 01 14 9e evsubfaddhx r0,r1,r2
+ 894: 10 01 14 9f evsubfaddhxss r0,r1,r2
+ 898: 10 01 14 a0 evadddus r0,r1,r2
+ 89c: 10 01 14 a1 evaddbus r0,r1,r2
+ 8a0: 10 01 14 a2 evsubfdus r0,r1,r2
+ 8a4: 10 01 14 a3 evsubfbus r0,r1,r2
+ 8a8: 10 01 14 a4 evaddwus r0,r1,r2
+ 8ac: 10 01 14 a5 evaddwxus r0,r1,r2
+ 8b0: 10 01 14 a6 evsubfwus r0,r1,r2
+ 8b4: 10 01 14 a7 evsubfwxus r0,r1,r2
+ 8b8: 10 01 14 a8 evadd2subf2h r0,r1,r2
+ 8bc: 10 01 14 a9 evadd2subf2hss r0,r1,r2
+ 8c0: 10 01 14 aa evsubf2add2h r0,r1,r2
+ 8c4: 10 01 14 ab evsubf2add2hss r0,r1,r2
+ 8c8: 10 01 14 ac evaddhus r0,r1,r2
+ 8cc: 10 01 14 ad evaddhxus r0,r1,r2
+ 8d0: 10 01 14 ae evsubfhus r0,r1,r2
+ 8d4: 10 01 14 af evsubfhxus r0,r1,r2
+ 8d8: 10 01 14 b1 evaddwss r0,r1,r2
+ 8dc: 10 01 14 b3 evsubfwss r0,r1,r2
+ 8e0: 10 01 14 b4 evaddwx r0,r1,r2
+ 8e4: 10 01 14 b5 evaddwxss r0,r1,r2
+ 8e8: 10 01 14 b6 evsubfwx r0,r1,r2
+ 8ec: 10 01 14 b7 evsubfwxss r0,r1,r2
+ 8f0: 10 01 14 b8 evaddsubfw r0,r1,r2
+ 8f4: 10 01 14 b9 evaddsubfwss r0,r1,r2
+ 8f8: 10 01 14 ba evsubfaddw r0,r1,r2
+ 8fc: 10 01 14 bb evsubfaddwss r0,r1,r2
+ 900: 10 01 14 bc evaddsubfwx r0,r1,r2
+ 904: 10 01 14 bd evaddsubfwxss r0,r1,r2
+ 908: 10 01 14 be evsubfaddwx r0,r1,r2
+ 90c: 10 01 14 bf evsubfaddwxss r0,r1,r2
+ 910: 10 00 0c c4 evmar r0
+ 914: 10 01 04 c5 evsumwu r0,r1
+ 918: 10 01 0c c5 evsumws r0,r1
+ 91c: 10 01 14 c5 evsum4bu r0,r1
+ 920: 10 01 1c c5 evsum4bs r0,r1
+ 924: 10 01 24 c5 evsum2hu r0,r1
+ 928: 10 01 2c c5 evsum2hs r0,r1
+ 92c: 10 01 34 c5 evdiff2his r0,r1
+ 930: 10 01 3c c5 evsum2his r0,r1
+ 934: 10 01 84 c5 evsumwua r0,r1
+ 938: 10 01 8c c5 evsumwsa r0,r1
+ 93c: 10 01 94 c5 evsum4bua r0,r1
+ 940: 10 01 9c c5 evsum4bsa r0,r1
+ 944: 10 01 a4 c5 evsum2hua r0,r1
+ 948: 10 01 ac c5 evsum2hsa r0,r1
+ 94c: 10 01 b4 c5 evdiff2hisa r0,r1
+ 950: 10 01 bc c5 evsum2hisa r0,r1
+ 954: 10 01 c4 c5 evsumwuaa r0,r1
+ 958: 10 01 cc c5 evsumwsaa r0,r1
+ 95c: 10 01 d4 c5 evsum4buaaw r0,r1
+ 960: 10 01 dc c5 evsum4bsaaw r0,r1
+ 964: 10 01 e4 c5 evsum2huaaw r0,r1
+ 968: 10 01 ec c5 evsum2hsaaw r0,r1
+ 96c: 10 01 f4 c5 evdiff2hisaaw r0,r1
+ 970: 10 01 fc c5 evsum2hisaaw r0,r1
+ 974: 10 01 14 cc evdivwsf r0,r1,r2
+ 978: 10 01 14 cd evdivwuf r0,r1,r2
+ 97c: 10 01 14 ce evdivs r0,r1,r2
+ 980: 10 01 14 cf evdivu r0,r1,r2
+ 984: 10 01 14 d0 evaddwegsi r0,r1,r2
+ 988: 10 01 14 d1 evaddwegsf r0,r1,r2
+ 98c: 10 01 14 d2 evsubfwegsi r0,r1,r2
+ 990: 10 01 14 d3 evsubfwegsf r0,r1,r2
+ 994: 10 01 14 d4 evaddwogsi r0,r1,r2
+ 998: 10 01 14 d5 evaddwogsf r0,r1,r2
+ 99c: 10 01 14 d6 evsubfwogsi r0,r1,r2
+ 9a0: 10 01 14 d7 evsubfwogsf r0,r1,r2
+ 9a4: 10 01 14 d8 evaddhhiuw r0,r1,r2
+ 9a8: 10 01 14 d9 evaddhhisw r0,r1,r2
+ 9ac: 10 01 14 da evsubfhhiuw r0,r1,r2
+ 9b0: 10 01 14 db evsubfhhisw r0,r1,r2
+ 9b4: 10 01 14 dc evaddhlouw r0,r1,r2
+ 9b8: 10 01 14 dd evaddhlosw r0,r1,r2
+ 9bc: 10 01 14 de evsubfhlouw r0,r1,r2
+ 9c0: 10 01 14 df evsubfhlosw r0,r1,r2
+ 9c4: 10 01 15 02 evmhesusiaaw r0,r1,r2
+ 9c8: 10 01 15 06 evmhosusiaaw r0,r1,r2
+ 9cc: 10 01 15 0a evmhesumiaaw r0,r1,r2
+ 9d0: 10 01 15 0e evmhosumiaaw r0,r1,r2
+ 9d4: 10 01 15 10 evmbeusiaah r0,r1,r2
+ 9d8: 10 01 15 11 evmbessiaah r0,r1,r2
+ 9dc: 10 01 15 12 evmbesusiaah r0,r1,r2
+ 9e0: 10 01 15 14 evmbousiaah r0,r1,r2
+ 9e4: 10 01 15 15 evmbossiaah r0,r1,r2
+ 9e8: 10 01 15 16 evmbosusiaah r0,r1,r2
+ 9ec: 10 01 15 18 evmbeumiaah r0,r1,r2
+ 9f0: 10 01 15 19 evmbesmiaah r0,r1,r2
+ 9f4: 10 01 15 1a evmbesumiaah r0,r1,r2
+ 9f8: 10 01 15 1c evmboumiaah r0,r1,r2
+ 9fc: 10 01 15 1d evmbosmiaah r0,r1,r2
+ a00: 10 01 15 1e evmbosumiaah r0,r1,r2
+ a04: 10 01 15 42 evmwlusiaaw3 r0,r1,r2
+ a08: 10 01 15 43 evmwlssiaaw3 r0,r1,r2
+ a0c: 10 01 15 44 evmwhssfraaw3 r0,r1,r2
+ a10: 10 01 15 45 evmwhssfaaw3 r0,r1,r2
+ a14: 10 01 15 46 evmwhssfraaw r0,r1,r2
+ a18: 10 01 15 47 evmwhssfaaw r0,r1,r2
+ a1c: 10 01 15 4a evmwlumiaaw3 r0,r1,r2
+ a20: 10 01 15 4b evmwlsmiaaw3 r0,r1,r2
+ a24: 10 01 15 50 evmwusiaa r0,r1,r2
+ a28: 10 01 15 51 evmwssiaa r0,r1,r2
+ a2c: 10 01 15 56 evmwehgsmfraa r0,r1,r2
+ a30: 10 01 15 57 evmwehgsmfaa r0,r1,r2
+ a34: 10 01 15 5e evmwohgsmfraa r0,r1,r2
+ a38: 10 01 15 5f evmwohgsmfaa r0,r1,r2
+ a3c: 10 01 15 82 evmhesusianw r0,r1,r2
+ a40: 10 01 15 86 evmhosusianw r0,r1,r2
+ a44: 10 01 15 8a evmhesumianw r0,r1,r2
+ a48: 10 01 15 8e evmhosumianw r0,r1,r2
+ a4c: 10 01 15 90 evmbeusianh r0,r1,r2
+ a50: 10 01 15 91 evmbessianh r0,r1,r2
+ a54: 10 01 15 92 evmbesusianh r0,r1,r2
+ a58: 10 01 15 94 evmbousianh r0,r1,r2
+ a5c: 10 01 15 95 evmbossianh r0,r1,r2
+ a60: 10 01 15 96 evmbosusianh r0,r1,r2
+ a64: 10 01 15 98 evmbeumianh r0,r1,r2
+ a68: 10 01 15 99 evmbesmianh r0,r1,r2
+ a6c: 10 01 15 9a evmbesumianh r0,r1,r2
+ a70: 10 01 15 9c evmboumianh r0,r1,r2
+ a74: 10 01 15 9d evmbosmianh r0,r1,r2
+ a78: 10 01 15 9e evmbosumianh r0,r1,r2
+ a7c: 10 01 15 c2 evmwlusianw3 r0,r1,r2
+ a80: 10 01 15 c3 evmwlssianw3 r0,r1,r2
+ a84: 10 01 15 c4 evmwhssfranw3 r0,r1,r2
+ a88: 10 01 15 c5 evmwhssfanw3 r0,r1,r2
+ a8c: 10 01 15 c6 evmwhssfranw r0,r1,r2
+ a90: 10 01 15 c7 evmwhssfanw r0,r1,r2
+ a94: 10 01 15 ca evmwlumianw3 r0,r1,r2
+ a98: 10 01 15 cb evmwlsmianw3 r0,r1,r2
+ a9c: 10 01 15 d0 evmwusian r0,r1,r2
+ aa0: 10 01 15 d1 evmwssian r0,r1,r2
+ aa4: 10 01 15 d6 evmwehgsmfran r0,r1,r2
+ aa8: 10 01 15 d7 evmwehgsmfan r0,r1,r2
+ aac: 10 01 15 de evmwohgsmfran r0,r1,r2
+ ab0: 10 01 15 df evmwohgsmfan r0,r1,r2
+ ab4: 10 01 16 00 evseteqb r0,r1,r2
+ ab8: 10 01 16 01 evseteqb. r0,r1,r2
+ abc: 10 01 16 02 evseteqh r0,r1,r2
+ ac0: 10 01 16 03 evseteqh. r0,r1,r2
+ ac4: 10 01 16 04 evseteqw r0,r1,r2
+ ac8: 10 01 16 05 evseteqw. r0,r1,r2
+ acc: 10 01 16 08 evsetgthu r0,r1,r2
+ ad0: 10 01 16 09 evsetgthu. r0,r1,r2
+ ad4: 10 01 16 0a evsetgths r0,r1,r2
+ ad8: 10 01 16 0b evsetgths. r0,r1,r2
+ adc: 10 01 16 0c evsetgtwu r0,r1,r2
+ ae0: 10 01 16 0d evsetgtwu. r0,r1,r2
+ ae4: 10 01 16 0e evsetgtws r0,r1,r2
+ ae8: 10 01 16 0f evsetgtws. r0,r1,r2
+ aec: 10 01 16 10 evsetgtbu r0,r1,r2
+ af0: 10 01 16 11 evsetgtbu. r0,r1,r2
+ af4: 10 01 16 12 evsetgtbs r0,r1,r2
+ af8: 10 01 16 13 evsetgtbs. r0,r1,r2
+ afc: 10 01 16 14 evsetltbu r0,r1,r2
+ b00: 10 01 16 15 evsetltbu. r0,r1,r2
+ b04: 10 01 16 16 evsetltbs r0,r1,r2
+ b08: 10 01 16 17 evsetltbs. r0,r1,r2
+ b0c: 10 01 16 18 evsetlthu r0,r1,r2
+ b10: 10 01 16 19 evsetlthu. r0,r1,r2
+ b14: 10 01 16 1a evsetlths r0,r1,r2
+ b18: 10 01 16 1b evsetlths. r0,r1,r2
+ b1c: 10 01 16 1c evsetltwu r0,r1,r2
+ b20: 10 01 16 1d evsetltwu. r0,r1,r2
+ b24: 10 01 16 1e evsetltws r0,r1,r2
+ b28: 10 01 16 1f evsetltws. r0,r1,r2
+ b2c: 10 01 16 20 evsaduw r0,r1,r2
+ b30: 10 01 16 21 evsadsw r0,r1,r2
+ b34: 10 01 16 22 evsad4ub r0,r1,r2
+ b38: 10 01 16 23 evsad4sb r0,r1,r2
+ b3c: 10 01 16 24 evsad2uh r0,r1,r2
+ b40: 10 01 16 25 evsad2sh r0,r1,r2
+ b44: 10 01 16 28 evsaduwa r0,r1,r2
+ b48: 10 01 16 29 evsadswa r0,r1,r2
+ b4c: 10 01 16 2a evsad4uba r0,r1,r2
+ b50: 10 01 16 2b evsad4sba r0,r1,r2
+ b54: 10 01 16 2c evsad2uha r0,r1,r2
+ b58: 10 01 16 2d evsad2sha r0,r1,r2
+ b5c: 10 01 16 30 evabsdifuw r0,r1,r2
+ b60: 10 01 16 31 evabsdifsw r0,r1,r2
+ b64: 10 01 16 32 evabsdifub r0,r1,r2
+ b68: 10 01 16 33 evabsdifsb r0,r1,r2
+ b6c: 10 01 16 34 evabsdifuh r0,r1,r2
+ b70: 10 01 16 35 evabsdifsh r0,r1,r2
+ b74: 10 01 16 38 evsaduwaa r0,r1,r2
+ b78: 10 01 16 39 evsadswaa r0,r1,r2
+ b7c: 10 01 16 3a evsad4ubaaw r0,r1,r2
+ b80: 10 01 16 3b evsad4sbaaw r0,r1,r2
+ b84: 10 01 16 3c evsad2uhaaw r0,r1,r2
+ b88: 10 01 16 3d evsad2shaaw r0,r1,r2
+ b8c: 10 01 16 40 evpkshubs r0,r1,r2
+ b90: 10 01 16 41 evpkshsbs r0,r1,r2
+ b94: 10 01 16 42 evpkswuhs r0,r1,r2
+ b98: 10 01 16 43 evpkswshs r0,r1,r2
+ b9c: 10 01 16 44 evpkuhubs r0,r1,r2
+ ba0: 10 01 16 45 evpkuwuhs r0,r1,r2
+ ba4: 10 01 16 46 evpkswshilvs r0,r1,r2
+ ba8: 10 01 16 47 evpkswgshefrs r0,r1,r2
+ bac: 10 01 16 48 evpkswshfrs r0,r1,r2
+ bb0: 10 01 16 49 evpkswshilvfrs r0,r1,r2
+ bb4: 10 01 16 4a evpksdswfrs r0,r1,r2
+ bb8: 10 01 16 4b evpksdshefrs r0,r1,r2
+ bbc: 10 01 16 4c evpkuduws r0,r1,r2
+ bc0: 10 01 16 4d evpksdsws r0,r1,r2
+ bc4: 10 01 16 4e evpkswgswfrs r0,r1,r2
+ bc8: 10 01 16 50 evilveh r0,r1,r2
+ bcc: 10 01 16 51 evilveoh r0,r1,r2
+ bd0: 10 01 16 52 evilvhih r0,r1,r2
+ bd4: 10 01 16 53 evilvhiloh r0,r1,r2
+ bd8: 10 01 16 54 evilvloh r0,r1,r2
+ bdc: 10 01 16 55 evilvlohih r0,r1,r2
+ be0: 10 01 16 56 evilvoeh r0,r1,r2
+ be4: 10 01 16 57 evilvoh r0,r1,r2
+ be8: 10 01 16 58 evdlveb r0,r1,r2
+ bec: 10 01 16 59 evdlveh r0,r1,r2
+ bf0: 10 01 16 5a evdlveob r0,r1,r2
+ bf4: 10 01 16 5b evdlveoh r0,r1,r2
+ bf8: 10 01 16 5c evdlvob r0,r1,r2
+ bfc: 10 01 16 5d evdlvoh r0,r1,r2
+ c00: 10 01 16 5e evdlvoeb r0,r1,r2
+ c04: 10 01 16 5f evdlvoeh r0,r1,r2
+ c08: 10 01 16 60 evmaxbu r0,r1,r2
+ c0c: 10 01 16 61 evmaxbs r0,r1,r2
+ c10: 10 01 16 62 evmaxhu r0,r1,r2
+ c14: 10 01 16 63 evmaxhs r0,r1,r2
+ c18: 10 01 16 64 evmaxwu r0,r1,r2
+ c1c: 10 01 16 65 evmaxws r0,r1,r2
+ c20: 10 01 16 66 evmaxdu r0,r1,r2
+ c24: 10 01 16 67 evmaxds r0,r1,r2
+ c28: 10 01 16 68 evminbu r0,r1,r2
+ c2c: 10 01 16 69 evminbs r0,r1,r2
+ c30: 10 01 16 6a evminhu r0,r1,r2
+ c34: 10 01 16 6b evminhs r0,r1,r2
+ c38: 10 01 16 6c evminwu r0,r1,r2
+ c3c: 10 01 16 6d evminws r0,r1,r2
+ c40: 10 01 16 6e evmindu r0,r1,r2
+ c44: 10 01 16 6f evminds r0,r1,r2
+ c48: 10 01 16 70 evavgwu r0,r1,r2
+ c4c: 10 01 16 71 evavgws r0,r1,r2
+ c50: 10 01 16 72 evavgbu r0,r1,r2
+ c54: 10 01 16 73 evavgbs r0,r1,r2
+ c58: 10 01 16 74 evavghu r0,r1,r2
+ c5c: 10 01 16 75 evavghs r0,r1,r2
+ c60: 10 01 16 76 evavgdu r0,r1,r2
+ c64: 10 01 16 77 evavgds r0,r1,r2
+ c68: 10 01 16 78 evavgwur r0,r1,r2
+ c6c: 10 01 16 79 evavgwsr r0,r1,r2
+ c70: 10 01 16 7a evavgbur r0,r1,r2
+ c74: 10 01 16 7b evavgbsr r0,r1,r2
+ c78: 10 01 16 7c evavghur r0,r1,r2
+ c7c: 10 01 16 7d evavghsr r0,r1,r2
+ c80: 10 01 16 7e evavgdur r0,r1,r2
+ c84: 10 01 16 7f evavgdsr r0,r1,r2
+ c88: 10 01 11 4d evdotphssmi r0,r1,r2
+ c8c: 10 01 11 6d evdotphssmia r0,r1,r2
+ c90: 10 01 11 cd evdotpwssmi r0,r1,r2
+ c94: 10 01 11 ed evdotpwssmia r0,r1,r2
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2.s binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.s
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe2.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.s 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,838 @@
+# PA SPE2 instructions
+# Testcase for CMPE200GCC-5, CMPE200GCC-62
+
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ UIMM, 31
+ .equ UIMM_LT8, 7
+ .equ UIMM_LT16, 15
+ .equ UIMM_1, 1
+ .equ UIMM_2, 2
+ .equ UIMM_4, 4
+ .equ UIMM_8, 8
+ .equ SIMM, -16
+ .equ crD, 0
+ .equ nnn, 7
+ .equ bbb, 7
+ .equ dd, 3
+ .equ Ddd, 7
+ .equ hh, 3
+ .equ mask, 15
+ .equ offset, 7
+
+ evdotpwcssi rD, rA, rB
+ evdotpwcsmi rD, rA, rB
+ evdotpwcssfr rD, rA, rB
+ evdotpwcssf rD, rA, rB
+ evdotpwgasmf rD, rA, rB
+ evdotpwxgasmf rD, rA, rB
+ evdotpwgasmfr rD, rA, rB
+ evdotpwxgasmfr rD, rA, rB
+ evdotpwgssmf rD, rA, rB
+ evdotpwxgssmf rD, rA, rB
+ evdotpwgssmfr rD, rA, rB
+ evdotpwxgssmfr rD, rA, rB
+ evdotpwcssiaaw3 rD, rA, rB
+ evdotpwcsmiaaw3 rD, rA, rB
+ evdotpwcssfraaw3 rD, rA, rB
+ evdotpwcssfaaw3 rD, rA, rB
+ evdotpwgasmfaa3 rD, rA, rB
+ evdotpwxgasmfaa3 rD, rA, rB
+ evdotpwgasmfraa3 rD, rA, rB
+ evdotpwxgasmfraa3 rD, rA, rB
+ evdotpwgssmfaa3 rD, rA, rB
+ evdotpwxgssmfaa3 rD, rA, rB
+ evdotpwgssmfraa3 rD, rA, rB
+ evdotpwxgssmfraa3 rD, rA, rB
+ evdotpwcssia rD, rA, rB
+ evdotpwcsmia rD, rA, rB
+ evdotpwcssfra rD, rA, rB
+ evdotpwcssfa rD, rA, rB
+ evdotpwgasmfa rD, rA, rB
+ evdotpwxgasmfa rD, rA, rB
+ evdotpwgasmfra rD, rA, rB
+ evdotpwxgasmfra rD, rA, rB
+ evdotpwgssmfa rD, rA, rB
+ evdotpwxgssmfa rD, rA, rB
+ evdotpwgssmfra rD, rA, rB
+ evdotpwxgssmfra rD, rA, rB
+ evdotpwcssiaaw rD, rA, rB
+ evdotpwcsmiaaw rD, rA, rB
+ evdotpwcssfraaw rD, rA, rB
+ evdotpwcssfaaw rD, rA, rB
+ evdotpwgasmfaa rD, rA, rB
+ evdotpwxgasmfaa rD, rA, rB
+ evdotpwgasmfraa rD, rA, rB
+ evdotpwxgasmfraa rD, rA, rB
+ evdotpwgssmfaa rD, rA, rB
+ evdotpwxgssmfaa rD, rA, rB
+ evdotpwgssmfraa rD, rA, rB
+ evdotpwxgssmfraa rD, rA, rB
+ evdotphihcssi rD, rA, rB
+ evdotplohcssi rD, rA, rB
+ evdotphihcssf rD, rA, rB
+ evdotplohcssf rD, rA, rB
+ evdotphihcsmi rD, rA, rB
+ evdotplohcsmi rD, rA, rB
+ evdotphihcssfr rD, rA, rB
+ evdotplohcssfr rD, rA, rB
+ evdotphihcssiaaw3 rD, rA, rB
+ evdotplohcssiaaw3 rD, rA, rB
+ evdotphihcssfaaw3 rD, rA, rB
+ evdotplohcssfaaw3 rD, rA, rB
+ evdotphihcsmiaaw3 rD, rA, rB
+ evdotplohcsmiaaw3 rD, rA, rB
+ evdotphihcssfraaw3 rD, rA, rB
+ evdotplohcssfraaw3 rD, rA, rB
+ evdotphihcssia rD, rA, rB
+ evdotplohcssia rD, rA, rB
+ evdotphihcssfa rD, rA, rB
+ evdotplohcssfa rD, rA, rB
+ evdotphihcsmia rD, rA, rB
+ evdotplohcsmia rD, rA, rB
+ evdotphihcssfra rD, rA, rB
+ evdotplohcssfra rD, rA, rB
+ evdotphihcssiaaw rD, rA, rB
+ evdotplohcssiaaw rD, rA, rB
+ evdotphihcssfaaw rD, rA, rB
+ evdotplohcssfaaw rD, rA, rB
+ evdotphihcsmiaaw rD, rA, rB
+ evdotplohcsmiaaw rD, rA, rB
+ evdotphihcssfraaw rD, rA, rB
+ evdotplohcssfraaw rD, rA, rB
+ evdotphausi rD, rA, rB
+ evdotphassi rD, rA, rB
+ evdotphasusi rD, rA, rB
+ evdotphassf rD, rA, rB
+ evdotphsssf rD, rA, rB
+ evdotphaumi rD, rA, rB
+ evdotphasmi rD, rA, rB
+ evdotphasumi rD, rA, rB
+ evdotphassfr rD, rA, rB
+ evdotphssmi rD, rA, rB
+ evdotphsssfr rD, rA, rB
+ evdotphausiaaw3 rD, rA, rB
+ evdotphassiaaw3 rD, rA, rB
+ evdotphasusiaaw3 rD, rA, rB
+ evdotphassfaaw3 rD, rA, rB
+ evdotphsssiaaw3 rD, rA, rB
+ evdotphsssfaaw3 rD, rA, rB
+ evdotphaumiaaw3 rD, rA, rB
+ evdotphasmiaaw3 rD, rA, rB
+ evdotphasumiaaw3 rD, rA, rB
+ evdotphassfraaw3 rD, rA, rB
+ evdotphssmiaaw3 rD, rA, rB
+ evdotphsssfraaw3 rD, rA, rB
+ evdotphausia rD, rA, rB
+ evdotphassia rD, rA, rB
+ evdotphasusia rD, rA, rB
+ evdotphassfa rD, rA, rB
+ evdotphsssfa rD, rA, rB
+ evdotphaumia rD, rA, rB
+ evdotphasmia rD, rA, rB
+ evdotphasumia rD, rA, rB
+ evdotphassfra rD, rA, rB
+ evdotphssmia rD, rA, rB
+ evdotphsssfra rD, rA, rB
+ evdotphausiaaw rD, rA, rB
+ evdotphassiaaw rD, rA, rB
+ evdotphasusiaaw rD, rA, rB
+ evdotphassfaaw rD, rA, rB
+ evdotphsssiaaw rD, rA, rB
+ evdotphsssfaaw rD, rA, rB
+ evdotphaumiaaw rD, rA, rB
+ evdotphasmiaaw rD, rA, rB
+ evdotphasumiaaw rD, rA, rB
+ evdotphassfraaw rD, rA, rB
+ evdotphssmiaaw rD, rA, rB
+ evdotphsssfraaw rD, rA, rB
+ evdotp4hgaumi rD, rA, rB
+ evdotp4hgasmi rD, rA, rB
+ evdotp4hgasumi rD, rA, rB
+ evdotp4hgasmf rD, rA, rB
+ evdotp4hgssmi rD, rA, rB
+ evdotp4hgssmf rD, rA, rB
+ evdotp4hxgasmi rD, rA, rB
+ evdotp4hxgasmf rD, rA, rB
+ evdotpbaumi rD, rA, rB
+ evdotpbasmi rD, rA, rB
+ evdotpbasumi rD, rA, rB
+ evdotp4hxgssmi rD, rA, rB
+ evdotp4hxgssmf rD, rA, rB
+ evdotp4hgaumiaa3 rD, rA, rB
+ evdotp4hgasmiaa3 rD, rA, rB
+ evdotp4hgasumiaa3 rD, rA, rB
+ evdotp4hgasmfaa3 rD, rA, rB
+ evdotp4hgssmiaa3 rD, rA, rB
+ evdotp4hgssmfaa3 rD, rA, rB
+ evdotp4hxgasmiaa3 rD, rA, rB
+ evdotp4hxgasmfaa3 rD, rA, rB
+ evdotpbaumiaaw3 rD, rA, rB
+ evdotpbasmiaaw3 rD, rA, rB
+ evdotpbasumiaaw3 rD, rA, rB
+ evdotp4hxgssmiaa3 rD, rA, rB
+ evdotp4hxgssmfaa3 rD, rA, rB
+ evdotp4hgaumia rD, rA, rB
+ evdotp4hgasmia rD, rA, rB
+ evdotp4hgasumia rD, rA, rB
+ evdotp4hgasmfa rD, rA, rB
+ evdotp4hgssmia rD, rA, rB
+ evdotp4hgssmfa rD, rA, rB
+ evdotp4hxgasmia rD, rA, rB
+ evdotp4hxgasmfa rD, rA, rB
+ evdotpbaumia rD, rA, rB
+ evdotpbasmia rD, rA, rB
+ evdotpbasumia rD, rA, rB
+ evdotp4hxgssmia rD, rA, rB
+ evdotp4hxgssmfa rD, rA, rB
+ evdotp4hgaumiaa rD, rA, rB
+ evdotp4hgasmiaa rD, rA, rB
+ evdotp4hgasumiaa rD, rA, rB
+ evdotp4hgasmfaa rD, rA, rB
+ evdotp4hgssmiaa rD, rA, rB
+ evdotp4hgssmfaa rD, rA, rB
+ evdotp4hxgasmiaa rD, rA, rB
+ evdotp4hxgasmfaa rD, rA, rB
+ evdotpbaumiaaw rD, rA, rB
+ evdotpbasmiaaw rD, rA, rB
+ evdotpbasumiaaw rD, rA, rB
+ evdotp4hxgssmiaa rD, rA, rB
+ evdotp4hxgssmfaa rD, rA, rB
+ evdotpwausi rD, rA, rB
+ evdotpwassi rD, rA, rB
+ evdotpwasusi rD, rA, rB
+ evdotpwaumi rD, rA, rB
+ evdotpwasmi rD, rA, rB
+ evdotpwasumi rD, rA, rB
+ evdotpwssmi rD, rA, rB
+ evdotpwausiaa3 rD, rA, rB
+ evdotpwassiaa3 rD, rA, rB
+ evdotpwasusiaa3 rD, rA, rB
+ evdotpwsssiaa3 rD, rA, rB
+ evdotpwaumiaa3 rD, rA, rB
+ evdotpwasmiaa3 rD, rA, rB
+ evdotpwasumiaa3 rD, rA, rB
+ evdotpwssmiaa3 rD, rA, rB
+ evdotpwausia rD, rA, rB
+ evdotpwassia rD, rA, rB
+ evdotpwasusia rD, rA, rB
+ evdotpwaumia rD, rA, rB
+ evdotpwasmia rD, rA, rB
+ evdotpwasumia rD, rA, rB
+ evdotpwssmia rD, rA, rB
+ evdotpwausiaa rD, rA, rB
+ evdotpwassiaa rD, rA, rB
+ evdotpwasusiaa rD, rA, rB
+ evdotpwsssiaa rD, rA, rB
+ evdotpwaumiaa rD, rA, rB
+ evdotpwasmiaa rD, rA, rB
+ evdotpwasumiaa rD, rA, rB
+ evdotpwssmiaa rD, rA, rB
+ evaddib rD, rB, UIMM
+ evaddih rD, rB, UIMM
+ evsubifh rD, UIMM, rB
+ evsubifb rD, UIMM, rB
+ evabsb rD, rA
+ evabsh rD, rA
+ evabsd rD, rA
+ evabss rD, rA
+ evabsbs rD, rA
+ evabshs rD, rA
+ evabsds rD, rA
+ evnegwo rD, rA
+ evnegb rD, rA
+ evnegbo rD, rA
+ evnegh rD, rA
+ evnegho rD, rA
+ evnegd rD, rA
+ evnegs rD, rA
+ evnegwos rD, rA
+ evnegbs rD, rA
+ evnegbos rD, rA
+ evneghs rD, rA
+ evneghos rD, rA
+ evnegds rD, rA
+ evextzb rD, rA
+ evextsbh rD, rA
+ evextsw rD, rA
+ evrndwh rD, rA
+ evrndhb rD, rA
+ evrnddw rD, rA
+ evrndwhus rD, rA
+ evrndwhss rD, rA
+ evrndhbus rD, rA
+ evrndhbss rD, rA
+ evrnddwus rD, rA
+ evrnddwss rD, rA
+ evrndwnh rD, rA
+ evrndhnb rD, rA
+ evrnddnw rD, rA
+ evrndwnhus rD, rA
+ evrndwnhss rD, rA
+ evrndhnbus rD, rA
+ evrndhnbss rD, rA
+ evrnddnwus rD, rA
+ evrnddnwss rD, rA
+ evcntlzh rD, rA
+ evcntlsh rD, rA
+ evpopcntb rD, rA
+ circinc rD, rA, rB
+ evunpkhibui rD, rA
+ evunpkhibsi rD, rA
+ evunpkhihui rD, rA
+ evunpkhihsi rD, rA
+ evunpklobui rD, rA
+ evunpklobsi rD, rA
+ evunpklohui rD, rA
+ evunpklohsi rD, rA
+ evunpklohf rD, rA
+ evunpkhihf rD, rA
+ evunpklowgsf rD, rA
+ evunpkhiwgsf rD, rA
+ evsatsduw rD, rA
+ evsatsdsw rD, rA
+ evsatshub rD, rA
+ evsatshsb rD, rA
+ evsatuwuh rD, rA
+ evsatswsh rD, rA
+ evsatswuh rD, rA
+ evsatuhub rD, rA
+ evsatuduw rD, rA
+ evsatuwsw rD, rA
+ evsatshuh rD, rA
+ evsatuhsh rD, rA
+ evsatswuw rD, rA
+ evsatswgsdf rD, rA
+ evsatsbub rD, rA
+ evsatubsb rD, rA
+ evmaxhpuw rD, rA
+ evmaxhpsw rD, rA
+ evmaxbpuh rD, rA
+ evmaxbpsh rD, rA
+ evmaxwpud rD, rA
+ evmaxwpsd rD, rA
+ evminhpuw rD, rA
+ evminhpsw rD, rA
+ evminbpuh rD, rA
+ evminbpsh rD, rA
+ evminwpud rD, rA
+ evminwpsd rD, rA
+ evmaxmagws rD, rA, rB
+ evsl rD, rA, rB
+ evsli rD, rA, UIMM
+ evsplatie rD, SIMM
+ evsplatib rD, SIMM
+ evsplatibe rD, SIMM
+ evsplatih rD, SIMM
+ evsplatihe rD, SIMM
+ evsplatid rD, SIMM
+ evsplatia rD, SIMM
+ evsplatiea rD, SIMM
+ evsplatiba rD, SIMM
+ evsplatibea rD, SIMM
+ evsplatiha rD, SIMM
+ evsplatihea rD, SIMM
+ evsplatida rD, SIMM
+ evsplatfio rD, SIMM
+ evsplatfib rD, SIMM
+ evsplatfibo rD, SIMM
+ evsplatfih rD, SIMM
+ evsplatfiho rD, SIMM
+ evsplatfid rD, SIMM
+ evsplatfia rD, SIMM
+ evsplatfioa rD, SIMM
+ evsplatfiba rD, SIMM
+ evsplatfiboa rD, SIMM
+ evsplatfiha rD, SIMM
+ evsplatfihoa rD, SIMM
+ evsplatfida rD, SIMM
+ evcmpgtdu crD, rA, rB
+ evcmpgtds crD, rA, rB
+ evcmpltdu crD, rA, rB
+ evcmpltds crD, rA, rB
+ evcmpeqd crD, rA, rB
+ evswapbhilo rD, rA, rB
+ evswapblohi rD, rA, rB
+ evswaphhilo rD, rA, rB
+ evswaphlohi rD, rA, rB
+ evswaphe rD, rA, rB
+ evswaphhi rD, rA, rB
+ evswaphlo rD, rA, rB
+ evswapho rD, rA, rB
+ evinsb rD, rA, Ddd, bbb
+ evxtrb rD, rA, Ddd, bbb
+ evsplath rD, rA, hh
+ evsplatb rD, rA, bbb
+ evinsh rD, rA, dd, hh
+ evclrbe rD, rA, mask
+ evclrbo rD, rA, mask
+ evclrh rD, rA, mask
+ evxtrh rD, rA, dd, hh
+ evselbitm0 rD, rA, rB
+ evselbitm1 rD, rA, rB
+ evselbit rD, rA, rB
+ evperm rD, rA, rB
+ evperm2 rD, rA, rB
+ evperm3 rD, rA, rB
+ evxtrd rD, rA, rB, offset
+ evsrbu rD, rA, rB
+ evsrbs rD, rA, rB
+ evsrbiu rD, rA, UIMM_LT8
+ evsrbis rD, rA, UIMM_LT8
+ evslb rD, rA, rB
+ evrlb rD, rA, rB
+ evslbi rD, rA, UIMM_LT8
+ evrlbi rD, rA, UIMM_LT8
+ evsrhu rD, rA, rB
+ evsrhs rD, rA, rB
+ evsrhiu rD, rA, UIMM_LT16
+ evsrhis rD, rA, UIMM_LT16
+ evslh rD, rA, rB
+ evrlh rD, rA, rB
+ evslhi rD, rA, UIMM_LT16
+ evrlhi rD, rA, UIMM_LT16
+ evsru rD, rA, rB
+ evsrs rD, rA, rB
+ evsriu rD, rA, UIMM
+ evsris rD, rA, UIMM
+ evlvsl rD, rA, rB
+ evlvsr rD, rA, rB
+ evsroiu rD, rA, nnn
+ evsrois rD, rA, nnn
+ evsloi rD, rA, nnn
+ evfssqrt rD, rA
+ evfscfh rD, rB
+ evfscth rD, rB
+ evfsmax rD, rA, rB
+ evfsmin rD, rA, rB
+ evfsaddsub rD, rA, rB
+ evfssubadd rD, rA, rB
+ evfssum rD, rA, rB
+ evfsdiff rD, rA, rB
+ evfssumdiff rD, rA, rB
+ evfsdiffsum rD, rA, rB
+ evfsaddx rD, rA, rB
+ evfssubx rD, rA, rB
+ evfsaddsubx rD, rA, rB
+ evfssubaddx rD, rA, rB
+ evfsmulx rD, rA, rB
+ evfsmule rD, rA, rB
+ evfsmulo rD, rA, rB
+ evldbx rD, rA, rB
+ evldb rD, UIMM_8 (rA)
+ evlhhsplathx rD, rA, rB
+ evlhhsplath rD, UIMM_2 (rA)
+ evlwbsplatwx rD, rA, rB
+ evlwbsplatw rD, UIMM_4 (rA)
+ evlwhsplatwx rD, rA, rB
+ evlwhsplatw rD, UIMM_4 (rA)
+ evlbbsplatbx rD, rA, rB
+ evlbbsplatb rD, UIMM_1 (rA)
+ evstdbx rS, rA, rB
+ evstdb rS, UIMM_8 (rA)
+ evlwbex rD, rA, rB
+ evlwbe rD, UIMM_4 (rA)
+ evlwboux rD, rA, rB
+ evlwbou rD, UIMM_4 (rA)
+ evlwbosx rD, rA, rB
+ evlwbos rD, UIMM_4 (rA)
+ evstwbex rS, rA, rB
+ evstwbe rS, UIMM_4 (rA)
+ evstwbox rS, rA, rB
+ evstwbo rS, UIMM_4 (rA)
+ evstwbx rS, rA, rB
+ evstwb rS, UIMM_4 (rA)
+ evsthbx rS, rA, rB
+ evsthb rS, UIMM_2 (rA)
+ evlddmx rD, rA, rB
+ evlddu rD, UIMM_8 (rA)
+ evldwmx rD, rA, rB
+ evldwu rD, UIMM_8 (rA)
+ evldhmx rD, rA, rB
+ evldhu rD, UIMM_8 (rA)
+ evldbmx rD, rA, rB
+ evldbu rD, UIMM_8 (rA)
+ evlhhesplatmx rD, rA, rB
+ evlhhesplatu rD, UIMM_2 (rA)
+ evlhhsplathmx rD, rA, rB
+ evlhhsplathu rD, UIMM_2 (rA)
+ evlhhousplatmx rD, rA, rB
+ evlhhousplatu rD, UIMM_2 (rA)
+ evlhhossplatmx rD, rA, rB
+ evlhhossplatu rD, UIMM_2 (rA)
+ evlwhemx rD, rA, rB
+ evlwheu rD, UIMM_4 (rA)
+ evlwbsplatwmx rD, rA, rB
+ evlwbsplatwu rD, UIMM_4 (rA)
+ evlwhoumx rD, rA, rB
+ evlwhouu rD, UIMM_4 (rA)
+ evlwhosmx rD, rA, rB
+ evlwhosu rD, UIMM_4 (rA)
+ evlwwsplatmx rD, rA, rB
+ evlwwsplatu rD, UIMM_4 (rA)
+ evlwhsplatwmx rD, rA, rB
+ evlwhsplatwu rD, UIMM_4 (rA)
+ evlwhsplatmx rD, rA, rB
+ evlwhsplatu rD, UIMM_4 (rA)
+ evlbbsplatbmx rD, rA, rB
+ evlbbsplatbu rD, UIMM_1 (rA)
+ evstddmx rS, rA, rB
+ evstddu rS, UIMM_8 (rA)
+ evstdwmx rS, rA, rB
+ evstdwu rS, UIMM_8 (rA)
+ evstdhmx rS, rA, rB
+ evstdhu rS, UIMM_8 (rA)
+ evstdbmx rS, rA, rB
+ evstdbu rS, UIMM_8 (rA)
+ evlwbemx rD, rA, rB
+ evlwbeu rD, UIMM_4 (rA)
+ evlwboumx rD, rA, rB
+ evlwbouu rD, UIMM_4 (rA)
+ evlwbosmx rD, rA, rB
+ evlwbosu rD, UIMM_4 (rA)
+ evstwhemx rS, rA, rB
+ evstwheu rS, UIMM_4 (rA)
+ evstwbemx rS, rA, rB
+ evstwbeu rS, UIMM_4 (rA)
+ evstwhomx rS, rA, rB
+ evstwhou rS, UIMM_4 (rA)
+ evstwbomx rS, rA, rB
+ evstwbou rS, UIMM_4 (rA)
+ evstwwemx rS, rA, rB
+ evstwweu rS, UIMM_4 (rA)
+ evstwbmx rS, rA, rB
+ evstwbu rS, UIMM_4 (rA)
+ evstwwomx rS, rA, rB
+ evstwwou rS, UIMM_4 (rA)
+ evsthbmx rS, rA, rB
+ evsthbu rS, UIMM_2 (rA)
+ evmhusi rD, rA, rB
+ evmhssi rD, rA, rB
+ evmhsusi rD, rA, rB
+ evmhssf rD, rA, rB
+ evmhumi rD, rA, rB
+ evmhssfr rD, rA, rB
+ evmhesumi rD, rA, rB
+ evmhosumi rD, rA, rB
+ evmbeumi rD, rA, rB
+ evmbesmi rD, rA, rB
+ evmbesumi rD, rA, rB
+ evmboumi rD, rA, rB
+ evmbosmi rD, rA, rB
+ evmbosumi rD, rA, rB
+ evmhesumia rD, rA, rB
+ evmhosumia rD, rA, rB
+ evmbeumia rD, rA, rB
+ evmbesmia rD, rA, rB
+ evmbesumia rD, rA, rB
+ evmboumia rD, rA, rB
+ evmbosmia rD, rA, rB
+ evmbosumia rD, rA, rB
+ evmwusiw rD, rA, rB
+ evmwssiw rD, rA, rB
+ evmwhssfr rD, rA, rB
+ evmwehgsmfr rD, rA, rB
+ evmwehgsmf rD, rA, rB
+ evmwohgsmfr rD, rA, rB
+ evmwohgsmf rD, rA, rB
+ evmwhssfra rD, rA, rB
+ evmwehgsmfra rD, rA, rB
+ evmwehgsmfa rD, rA, rB
+ evmwohgsmfra rD, rA, rB
+ evmwohgsmfa rD, rA, rB
+ evaddusiaa rD, rA
+ evaddssiaa rD, rA
+ evsubfusiaa rD, rA
+ evsubfssiaa rD, rA
+ evaddsmiaa rD, rA
+ evsubfsmiaa rD, rA
+ evaddh rD, rA, rB
+ evaddhss rD, rA, rB
+ evsubfh rD, rA, rB
+ evsubfhss rD, rA, rB
+ evaddhx rD, rA, rB
+ evaddhxss rD, rA, rB
+ evsubfhx rD, rA, rB
+ evsubfhxss rD, rA, rB
+ evaddd rD, rA, rB
+ evadddss rD, rA, rB
+ evsubfd rD, rA, rB
+ evsubfdss rD, rA, rB
+ evaddb rD, rA, rB
+ evaddbss rD, rA, rB
+ evsubfb rD, rA, rB
+ evsubfbss rD, rA, rB
+ evaddsubfh rD, rA, rB
+ evaddsubfhss rD, rA, rB
+ evsubfaddh rD, rA, rB
+ evsubfaddhss rD, rA, rB
+ evaddsubfhx rD, rA, rB
+ evaddsubfhxss rD, rA, rB
+ evsubfaddhx rD, rA, rB
+ evsubfaddhxss rD, rA, rB
+ evadddus rD, rA, rB
+ evaddbus rD, rA, rB
+ evsubfdus rD, rA, rB
+ evsubfbus rD, rA, rB
+ evaddwus rD, rA, rB
+ evaddwxus rD, rA, rB
+ evsubfwus rD, rA, rB
+ evsubfwxus rD, rA, rB
+ evadd2subf2h rD, rA, rB
+ evadd2subf2hss rD, rA, rB
+ evsubf2add2h rD, rA, rB
+ evsubf2add2hss rD, rA, rB
+ evaddhus rD, rA, rB
+ evaddhxus rD, rA, rB
+ evsubfhus rD, rA, rB
+ evsubfhxus rD, rA, rB
+ evaddwss rD, rA, rB
+ evsubfwss rD, rA, rB
+ evaddwx rD, rA, rB
+ evaddwxss rD, rA, rB
+ evsubfwx rD, rA, rB
+ evsubfwxss rD, rA, rB
+ evaddsubfw rD, rA, rB
+ evaddsubfwss rD, rA, rB
+ evsubfaddw rD, rA, rB
+ evsubfaddwss rD, rA, rB
+ evaddsubfwx rD, rA, rB
+ evaddsubfwxss rD, rA, rB
+ evsubfaddwx rD, rA, rB
+ evsubfaddwxss rD, rA, rB
+ evmar rD
+ evsumwu rD, rA
+ evsumws rD, rA
+ evsum4bu rD, rA
+ evsum4bs rD, rA
+ evsum2hu rD, rA
+ evsum2hs rD, rA
+ evdiff2his rD, rA
+ evsum2his rD, rA
+ evsumwua rD, rA
+ evsumwsa rD, rA
+ evsum4bua rD, rA
+ evsum4bsa rD, rA
+ evsum2hua rD, rA
+ evsum2hsa rD, rA
+ evdiff2hisa rD, rA
+ evsum2hisa rD, rA
+ evsumwuaa rD, rA
+ evsumwsaa rD, rA
+ evsum4buaaw rD, rA
+ evsum4bsaaw rD, rA
+ evsum2huaaw rD, rA
+ evsum2hsaaw rD, rA
+ evdiff2hisaaw rD, rA
+ evsum2hisaaw rD, rA
+ evdivwsf rD, rA, rB
+ evdivwuf rD, rA, rB
+ evdivs rD, rA, rB
+ evdivu rD, rA, rB
+ evaddwegsi rD, rA, rB
+ evaddwegsf rD, rA, rB
+ evsubfwegsi rD, rA, rB
+ evsubfwegsf rD, rA, rB
+ evaddwogsi rD, rA, rB
+ evaddwogsf rD, rA, rB
+ evsubfwogsi rD, rA, rB
+ evsubfwogsf rD, rA, rB
+ evaddhhiuw rD, rA, rB
+ evaddhhisw rD, rA, rB
+ evsubfhhiuw rD, rA, rB
+ evsubfhhisw rD, rA, rB
+ evaddhlouw rD, rA, rB
+ evaddhlosw rD, rA, rB
+ evsubfhlouw rD, rA, rB
+ evsubfhlosw rD, rA, rB
+ evmhesusiaaw rD, rA, rB
+ evmhosusiaaw rD, rA, rB
+ evmhesumiaaw rD, rA, rB
+ evmhosumiaaw rD, rA, rB
+ evmbeusiaah rD, rA, rB
+ evmbessiaah rD, rA, rB
+ evmbesusiaah rD, rA, rB
+ evmbousiaah rD, rA, rB
+ evmbossiaah rD, rA, rB
+ evmbosusiaah rD, rA, rB
+ evmbeumiaah rD, rA, rB
+ evmbesmiaah rD, rA, rB
+ evmbesumiaah rD, rA, rB
+ evmboumiaah rD, rA, rB
+ evmbosmiaah rD, rA, rB
+ evmbosumiaah rD, rA, rB
+ evmwlusiaaw3 rD, rA, rB
+ evmwlssiaaw3 rD, rA, rB
+ evmwhssfraaw3 rD, rA, rB
+ evmwhssfaaw3 rD, rA, rB
+ evmwhssfraaw rD, rA, rB
+ evmwhssfaaw rD, rA, rB
+ evmwlumiaaw3 rD, rA, rB
+ evmwlsmiaaw3 rD, rA, rB
+ evmwusiaa rD, rA, rB
+ evmwssiaa rD, rA, rB
+ evmwehgsmfraa rD, rA, rB
+ evmwehgsmfaa rD, rA, rB
+ evmwohgsmfraa rD, rA, rB
+ evmwohgsmfaa rD, rA, rB
+ evmhesusianw rD, rA, rB
+ evmhosusianw rD, rA, rB
+ evmhesumianw rD, rA, rB
+ evmhosumianw rD, rA, rB
+ evmbeusianh rD, rA, rB
+ evmbessianh rD, rA, rB
+ evmbesusianh rD, rA, rB
+ evmbousianh rD, rA, rB
+ evmbossianh rD, rA, rB
+ evmbosusianh rD, rA, rB
+ evmbeumianh rD, rA, rB
+ evmbesmianh rD, rA, rB
+ evmbesumianh rD, rA, rB
+ evmboumianh rD, rA, rB
+ evmbosmianh rD, rA, rB
+ evmbosumianh rD, rA, rB
+ evmwlusianw3 rD, rA, rB
+ evmwlssianw3 rD, rA, rB
+ evmwhssfranw3 rD, rA, rB
+ evmwhssfanw3 rD, rA, rB
+ evmwhssfranw rD, rA, rB
+ evmwhssfanw rD, rA, rB
+ evmwlumianw3 rD, rA, rB
+ evmwlsmianw3 rD, rA, rB
+ evmwusian rD, rA, rB
+ evmwssian rD, rA, rB
+ evmwehgsmfran rD, rA, rB
+ evmwehgsmfan rD, rA, rB
+ evmwohgsmfran rD, rA, rB
+ evmwohgsmfan rD, rA, rB
+ evseteqb rD, rA, rB
+ evseteqb. rD, rA, rB
+ evseteqh rD, rA, rB
+ evseteqh. rD, rA, rB
+ evseteqw rD, rA, rB
+ evseteqw. rD, rA, rB
+ evsetgthu rD, rA, rB
+ evsetgthu. rD, rA, rB
+ evsetgths rD, rA, rB
+ evsetgths. rD, rA, rB
+ evsetgtwu rD, rA, rB
+ evsetgtwu. rD, rA, rB
+ evsetgtws rD, rA, rB
+ evsetgtws. rD, rA, rB
+ evsetgtbu rD, rA, rB
+ evsetgtbu. rD, rA, rB
+ evsetgtbs rD, rA, rB
+ evsetgtbs. rD, rA, rB
+ evsetltbu rD, rA, rB
+ evsetltbu. rD, rA, rB
+ evsetltbs rD, rA, rB
+ evsetltbs. rD, rA, rB
+ evsetlthu rD, rA, rB
+ evsetlthu. rD, rA, rB
+ evsetlths rD, rA, rB
+ evsetlths. rD, rA, rB
+ evsetltwu rD, rA, rB
+ evsetltwu. rD, rA, rB
+ evsetltws rD, rA, rB
+ evsetltws. rD, rA, rB
+ evsaduw rD, rA, rB
+ evsadsw rD, rA, rB
+ evsad4ub rD, rA, rB
+ evsad4sb rD, rA, rB
+ evsad2uh rD, rA, rB
+ evsad2sh rD, rA, rB
+ evsaduwa rD, rA, rB
+ evsadswa rD, rA, rB
+ evsad4uba rD, rA, rB
+ evsad4sba rD, rA, rB
+ evsad2uha rD, rA, rB
+ evsad2sha rD, rA, rB
+ evabsdifuw rD, rA, rB
+ evabsdifsw rD, rA, rB
+ evabsdifub rD, rA, rB
+ evabsdifsb rD, rA, rB
+ evabsdifuh rD, rA, rB
+ evabsdifsh rD, rA, rB
+ evsaduwaa rD, rA, rB
+ evsadswaa rD, rA, rB
+ evsad4ubaaw rD, rA, rB
+ evsad4sbaaw rD, rA, rB
+ evsad2uhaaw rD, rA, rB
+ evsad2shaaw rD, rA, rB
+ evpkshubs rD, rA, rB
+ evpkshsbs rD, rA, rB
+ evpkswuhs rD, rA, rB
+ evpkswshs rD, rA, rB
+ evpkuhubs rD, rA, rB
+ evpkuwuhs rD, rA, rB
+ evpkswshilvs rD, rA, rB
+ evpkswgshefrs rD, rA, rB
+ evpkswshfrs rD, rA, rB
+ evpkswshilvfrs rD, rA, rB
+ evpksdswfrs rD, rA, rB
+ evpksdshefrs rD, rA, rB
+ evpkuduws rD, rA, rB
+ evpksdsws rD, rA, rB
+ evpkswgswfrs rD, rA, rB
+ evilveh rD, rA, rB
+ evilveoh rD, rA, rB
+ evilvhih rD, rA, rB
+ evilvhiloh rD, rA, rB
+ evilvloh rD, rA, rB
+ evilvlohih rD, rA, rB
+ evilvoeh rD, rA, rB
+ evilvoh rD, rA, rB
+ evdlveb rD, rA, rB
+ evdlveh rD, rA, rB
+ evdlveob rD, rA, rB
+ evdlveoh rD, rA, rB
+ evdlvob rD, rA, rB
+ evdlvoh rD, rA, rB
+ evdlvoeb rD, rA, rB
+ evdlvoeh rD, rA, rB
+ evmaxbu rD, rA, rB
+ evmaxbs rD, rA, rB
+ evmaxhu rD, rA, rB
+ evmaxhs rD, rA, rB
+ evmaxwu rD, rA, rB
+ evmaxws rD, rA, rB
+ evmaxdu rD, rA, rB
+ evmaxds rD, rA, rB
+ evminbu rD, rA, rB
+ evminbs rD, rA, rB
+ evminhu rD, rA, rB
+ evminhs rD, rA, rB
+ evminwu rD, rA, rB
+ evminws rD, rA, rB
+ evmindu rD, rA, rB
+ evminds rD, rA, rB
+ evavgwu rD, rA, rB
+ evavgws rD, rA, rB
+ evavgbu rD, rA, rB
+ evavgbs rD, rA, rB
+ evavghu rD, rA, rB
+ evavghs rD, rA, rB
+ evavgdu rD, rA, rB
+ evavgds rD, rA, rB
+ evavgwur rD, rA, rB
+ evavgwsr rD, rA, rB
+ evavgbur rD, rA, rB
+ evavgbsr rD, rA, rB
+ evavghur rD, rA, rB
+ evavghsr rD, rA, rB
+ evavgdur rD, rA, rB
+ evavgdsr rD, rA, rB
+
+;#SPE2 mapped by macro
+ evdotphsssi rD, rA, rB
+ evdotphsssia rD, rA, rB
+ evdotpwsssi rD, rA, rB
+ evdotpwsssia rD, rA, rB
+
+
+
+
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe_ambiguous.d binutils-2.28-spe2/gas/testsuite/gas/ppc/spe_ambiguous.d
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe_ambiguous.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe_ambiguous.d 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,15 @@
+#as: -mvle
+#objdump: -d -Mspe
+#name: Validate SPE instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 12 04 evsubfw r0,r1,r2
+ 4: 10 01 12 04 evsubw r0,r2,r1
+ 8: 10 1f 12 06 evsubifw r0,31,r2
+ c: 10 1f 12 06 evsubiw r0,r2,31
+ 10: 10 01 12 18 evnor r0,r1,r2
+ 14: 10 01 0a 18 evnot r0,r1
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe_ambiguous.s binutils-2.28-spe2/gas/testsuite/gas/ppc/spe_ambiguous.s
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe_ambiguous.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe_ambiguous.s 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,21 @@
+# PA SPE instructions
+ .section ".text"
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ rT,0
+ .equ UIMM, 31
+ .equ UIMM_2, 2
+ .equ UIMM_4, 4
+ .equ UIMM_8, 8
+ .equ SIMM, -16
+ .equ crD, 0
+ .equ crS, 0
+
+ evsubfw rS, rA, rB
+ evsubw rS, rB, rA
+ evsubifw rS, UIMM, rB
+ evsubiw rS, rB, UIMM
+ evnor rS, rA, rB
+ evnot rS, rA
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe.d binutils-2.28-spe2/gas/testsuite/gas/ppc/spe.d
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe.d 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,267 @@
+#as: -mvle
+#objdump: -d -Mspe
+#name: Validate SPE instructions
+
+.*: +file format elf.*-powerpc.*
+
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 12 00 evaddw r0,r1,r2
+ 4: 10 1f 12 02 evaddiw r0,r2,31
+ 8: 10 01 12 04 evsubfw r0,r1,r2
+ c: 10 01 12 04 evsubfw r0,r1,r2
+ 10: 10 1f 12 06 evsubifw r0,31,r2
+ 14: 10 1f 12 06 evsubifw r0,31,r2
+ 18: 10 01 02 08 evabs r0,r1
+ 1c: 10 01 02 09 evneg r0,r1
+ 20: 10 01 02 0a evextsb r0,r1
+ 24: 10 01 02 0b evextsh r0,r1
+ 28: 10 01 02 0c evrndw r0,r1
+ 2c: 10 01 02 0d evcntlzw r0,r1
+ 30: 10 01 02 0e evcntlsw r0,r1
+ 34: 10 01 12 0f brinc r0,r1,r2
+ 38: 10 01 12 11 evand r0,r1,r2
+ 3c: 10 01 12 12 evandc r0,r1,r2
+ 40: 10 01 12 16 evxor r0,r1,r2
+ 44: 10 01 0a 17 evmr r0,r1
+ 48: 10 01 12 17 evor r0,r1,r2
+ 4c: 10 01 12 18 evnor r0,r1,r2
+ 50: 10 01 0a 18 evnor r0,r1,r1
+ 54: 10 01 12 19 eveqv r0,r1,r2
+ 58: 10 01 12 1b evorc r0,r1,r2
+ 5c: 10 01 12 1e evnand r0,r1,r2
+ 60: 10 01 12 20 evsrwu r0,r1,r2
+ 64: 10 01 12 21 evsrws r0,r1,r2
+ 68: 10 01 fa 22 evsrwiu r0,r1,31
+ 6c: 10 01 fa 23 evsrwis r0,r1,31
+ 70: 10 01 12 24 evslw r0,r1,r2
+ 74: 10 01 fa 26 evslwi r0,r1,31
+ 78: 10 01 12 28 evrlw r0,r1,r2
+ 7c: 10 10 02 29 evsplati r0,-16
+ 80: 10 01 fa 2a evrlwi r0,r1,31
+ 84: 10 10 02 2b evsplatfi r0,-16
+ 88: 10 01 12 2c evmergehi r0,r1,r2
+ 8c: 10 01 12 2d evmergelo r0,r1,r2
+ 90: 10 01 12 2e evmergehilo r0,r1,r2
+ 94: 10 01 12 2f evmergelohi r0,r1,r2
+ 98: 10 01 12 30 evcmpgtu cr0,r1,r2
+ 9c: 10 01 12 31 evcmpgts cr0,r1,r2
+ a0: 10 01 12 32 evcmpltu cr0,r1,r2
+ a4: 10 01 12 33 evcmplts cr0,r1,r2
+ a8: 10 01 12 34 evcmpeq cr0,r1,r2
+ ac: 10 01 12 78 evsel r0,r1,r2,cr0
+ b0: 10 01 12 80 evfsadd r0,r1,r2
+ b4: 10 01 12 81 evfssub r0,r1,r2
+ b8: 10 01 12 82 evfsmadd r0,r1,r2
+ bc: 10 01 12 83 evfsmsub r0,r1,r2
+ c0: 10 01 02 84 evfsabs r0,r1
+ c4: 10 01 02 85 evfsnabs r0,r1
+ c8: 10 01 02 86 evfsneg r0,r1
+ cc: 10 01 12 88 evfsmul r0,r1,r2
+ d0: 10 01 12 89 evfsdiv r0,r1,r2
+ d4: 10 01 12 8a evfsnmadd r0,r1,r2
+ d8: 10 01 12 8b evfsnmsub r0,r1,r2
+ dc: 10 01 12 8c evfscmpgt cr0,r1,r2
+ e0: 10 01 12 8d evfscmplt cr0,r1,r2
+ e4: 10 01 12 8e evfscmpeq cr0,r1,r2
+ e8: 10 00 12 90 evfscfui r0,r2
+ ec: 10 00 12 91 evfscfsi r0,r2
+ f0: 10 00 12 92 evfscfuf r0,r2
+ f4: 10 00 12 93 evfscfsf r0,r2
+ f8: 10 00 12 94 evfsctui r0,r2
+ fc: 10 00 12 95 evfsctsi r0,r2
+ 100: 10 00 12 96 evfsctuf r0,r2
+ 104: 10 00 12 97 evfsctsf r0,r2
+ 108: 10 00 12 98 evfsctuiz r0,r2
+ 10c: 10 00 12 9a evfsctsiz r0,r2
+ 110: 10 01 12 9c evfststgt cr0,r1,r2
+ 114: 10 01 12 9d evfststlt cr0,r1,r2
+ 118: 10 01 12 9e evfststeq cr0,r1,r2
+ 11c: 10 01 13 00 evlddx r0,r1,r2
+ 120: 10 01 0b 01 evldd r0,8\(r1\)
+ 124: 10 01 13 02 evldwx r0,r1,r2
+ 128: 10 01 0b 03 evldw r0,8\(r1\)
+ 12c: 10 01 13 04 evldhx r0,r1,r2
+ 130: 10 01 0b 05 evldh r0,8\(r1\)
+ 134: 10 01 13 08 evlhhesplatx r0,r1,r2
+ 138: 10 01 0b 09 evlhhesplat r0,2\(r1\)
+ 13c: 10 01 13 0c evlhhousplatx r0,r1,r2
+ 140: 10 01 0b 0d evlhhousplat r0,2\(r1\)
+ 144: 10 01 13 0e evlhhossplatx r0,r1,r2
+ 148: 10 01 0b 0f evlhhossplat r0,2\(r1\)
+ 14c: 10 01 13 10 evlwhex r0,r1,r2
+ 150: 10 01 0b 11 evlwhe r0,4\(r1\)
+ 154: 10 01 13 14 evlwhoux r0,r1,r2
+ 158: 10 01 0b 15 evlwhou r0,4\(r1\)
+ 15c: 10 01 13 16 evlwhosx r0,r1,r2
+ 160: 10 01 0b 17 evlwhos r0,4\(r1\)
+ 164: 10 01 13 18 evlwwsplatx r0,r1,r2
+ 168: 10 01 0b 19 evlwwsplat r0,4\(r1\)
+ 16c: 10 01 13 1c evlwhsplatx r0,r1,r2
+ 170: 10 01 0b 1d evlwhsplat r0,4\(r1\)
+ 174: 10 01 13 20 evstddx r0,r1,r2
+ 178: 10 01 0b 21 evstdd r0,8\(r1\)
+ 17c: 10 01 13 22 evstdwx r0,r1,r2
+ 180: 10 01 0b 23 evstdw r0,8\(r1\)
+ 184: 10 01 13 24 evstdhx r0,r1,r2
+ 188: 10 01 0b 25 evstdh r0,8\(r1\)
+ 18c: 10 01 13 30 evstwhex r0,r1,r2
+ 190: 10 01 0b 31 evstwhe r0,4\(r1\)
+ 194: 10 01 13 34 evstwhox r0,r1,r2
+ 198: 10 01 0b 35 evstwho r0,4\(r1\)
+ 19c: 10 01 13 38 evstwwex r0,r1,r2
+ 1a0: 10 01 0b 39 evstwwe r0,4\(r1\)
+ 1a4: 10 01 13 3c evstwwox r0,r1,r2
+ 1a8: 10 01 0b 3d evstwwo r0,4\(r1\)
+ 1ac: 10 01 14 03 evmhessf r0,r1,r2
+ 1b0: 10 01 14 07 evmhossf r0,r1,r2
+ 1b4: 10 01 14 08 evmheumi r0,r1,r2
+ 1b8: 10 01 14 09 evmhesmi r0,r1,r2
+ 1bc: 10 01 14 0b evmhesmf r0,r1,r2
+ 1c0: 10 01 14 0c evmhoumi r0,r1,r2
+ 1c4: 10 01 14 0d evmhosmi r0,r1,r2
+ 1c8: 10 01 14 0f evmhosmf r0,r1,r2
+ 1cc: 10 01 14 23 evmhessfa r0,r1,r2
+ 1d0: 10 01 14 27 evmhossfa r0,r1,r2
+ 1d4: 10 01 14 28 evmheumia r0,r1,r2
+ 1d8: 10 01 14 29 evmhesmia r0,r1,r2
+ 1dc: 10 01 14 2b evmhesmfa r0,r1,r2
+ 1e0: 10 01 14 2c evmhoumia r0,r1,r2
+ 1e4: 10 01 14 2d evmhosmia r0,r1,r2
+ 1e8: 10 01 14 2f evmhosmfa r0,r1,r2
+ 1ec: 10 01 14 43 evmwlssf r0,r1,r2
+ 1f0: 10 01 14 47 evmwhssf r0,r1,r2
+ 1f4: 10 01 14 48 evmwlumi r0,r1,r2
+ 1f8: 10 01 14 4b evmwlsmf r0,r1,r2
+ 1fc: 10 01 14 4c evmwhumi r0,r1,r2
+ 200: 10 01 14 4d evmwhsmi r0,r1,r2
+ 204: 10 01 14 4f evmwhsmf r0,r1,r2
+ 208: 10 01 14 53 evmwssf r0,r1,r2
+ 20c: 10 01 14 58 evmwumi r0,r1,r2
+ 210: 10 01 14 59 evmwsmi r0,r1,r2
+ 214: 10 01 14 5b evmwsmf r0,r1,r2
+ 218: 10 01 14 63 evmwlssfa r0,r1,r2
+ 21c: 10 01 14 67 evmwhssfa r0,r1,r2
+ 220: 10 01 14 68 evmwlumia r0,r1,r2
+ 224: 10 01 14 6b evmwlsmfa r0,r1,r2
+ 228: 10 01 14 6c evmwhumia r0,r1,r2
+ 22c: 10 01 14 6d evmwhsmia r0,r1,r2
+ 230: 10 01 14 6f evmwhsmfa r0,r1,r2
+ 234: 10 01 14 73 evmwssfa r0,r1,r2
+ 238: 10 01 14 78 evmwumia r0,r1,r2
+ 23c: 10 01 14 79 evmwsmia r0,r1,r2
+ 240: 10 01 14 7b evmwsmfa r0,r1,r2
+ 244: 10 01 04 c0 evaddusiaaw r0,r1
+ 248: 10 01 04 c1 evaddssiaaw r0,r1
+ 24c: 10 01 04 c2 evsubfusiaaw r0,r1
+ 250: 10 01 04 c3 evsubfssiaaw r0,r1
+ 254: 10 01 04 c4 evmra r0,r1
+ 258: 10 01 14 c6 evdivws r0,r1,r2
+ 25c: 10 01 14 c7 evdivwu r0,r1,r2
+ 260: 10 01 04 c8 evaddumiaaw r0,r1
+ 264: 10 01 04 c9 evaddsmiaaw r0,r1
+ 268: 10 01 04 ca evsubfumiaaw r0,r1
+ 26c: 10 01 04 cb evsubfsmiaaw r0,r1
+ 270: 10 01 15 00 evmheusiaaw r0,r1,r2
+ 274: 10 01 15 01 evmhessiaaw r0,r1,r2
+ 278: 10 01 15 03 evmhessfaaw r0,r1,r2
+ 27c: 10 01 15 04 evmhousiaaw r0,r1,r2
+ 280: 10 01 15 05 evmhossiaaw r0,r1,r2
+ 284: 10 01 15 07 evmhossfaaw r0,r1,r2
+ 288: 10 01 15 08 evmheumiaaw r0,r1,r2
+ 28c: 10 01 15 09 evmhesmiaaw r0,r1,r2
+ 290: 10 01 15 0b evmhesmfaaw r0,r1,r2
+ 294: 10 01 15 0c evmhoumiaaw r0,r1,r2
+ 298: 10 01 15 0d evmhosmiaaw r0,r1,r2
+ 29c: 10 01 15 0f evmhosmfaaw r0,r1,r2
+ 2a0: 10 01 15 28 evmhegumiaa r0,r1,r2
+ 2a4: 10 01 15 29 evmhegsmiaa r0,r1,r2
+ 2a8: 10 01 15 2b evmhegsmfaa r0,r1,r2
+ 2ac: 10 01 15 2c evmhogumiaa r0,r1,r2
+ 2b0: 10 01 15 2d evmhogsmiaa r0,r1,r2
+ 2b4: 10 01 15 2f evmhogsmfaa r0,r1,r2
+ 2b8: 10 01 15 40 evmwlusiaaw r0,r1,r2
+ 2bc: 10 01 15 41 evmwlssiaaw r0,r1,r2
+ 2c0: 10 01 15 43 evmwlssfaaw r0,r1,r2
+ 2c4: 10 01 15 44 evmwhusiaa r0,r1,r2
+ 2c8: 10 01 15 45 evmwhssmaa r0,r1,r2
+ 2cc: 10 01 15 47 evmwhssfaa r0,r1,r2
+ 2d0: 10 01 15 48 evmwlumiaaw r0,r1,r2
+ 2d4: 10 01 15 49 evmwlsmiaaw r0,r1,r2
+ 2d8: 10 01 15 4b evmwlsmfaaw r0,r1,r2
+ 2dc: 10 01 15 4c evmwhumiaa r0,r1,r2
+ 2e0: 10 01 15 4d evmwhsmiaa r0,r1,r2
+ 2e4: 10 01 15 4f evmwhsmfaa r0,r1,r2
+ 2e8: 10 01 15 53 evmwssfaa r0,r1,r2
+ 2ec: 10 01 15 58 evmwumiaa r0,r1,r2
+ 2f0: 10 01 15 59 evmwsmiaa r0,r1,r2
+ 2f4: 10 01 15 5b evmwsmfaa r0,r1,r2
+ 2f8: 10 01 15 64 evmwhgumiaa r0,r1,r2
+ 2fc: 10 01 15 65 evmwhgsmiaa r0,r1,r2
+ 300: 10 01 15 67 evmwhgssfaa r0,r1,r2
+ 304: 10 01 15 6f evmwhgsmfaa r0,r1,r2
+ 308: 10 01 15 80 evmheusianw r0,r1,r2
+ 30c: 10 01 15 81 evmhessianw r0,r1,r2
+ 310: 10 01 15 83 evmhessfanw r0,r1,r2
+ 314: 10 01 15 84 evmhousianw r0,r1,r2
+ 318: 10 01 15 85 evmhossianw r0,r1,r2
+ 31c: 10 01 15 87 evmhossfanw r0,r1,r2
+ 320: 10 01 15 88 evmheumianw r0,r1,r2
+ 324: 10 01 15 89 evmhesmianw r0,r1,r2
+ 328: 10 01 15 8b evmhesmfanw r0,r1,r2
+ 32c: 10 01 15 8c evmhoumianw r0,r1,r2
+ 330: 10 01 15 8d evmhosmianw r0,r1,r2
+ 334: 10 01 15 8f evmhosmfanw r0,r1,r2
+ 338: 10 01 15 a8 evmhegumian r0,r1,r2
+ 33c: 10 01 15 a9 evmhegsmian r0,r1,r2
+ 340: 10 01 15 ab evmhegsmfan r0,r1,r2
+ 344: 10 01 15 ac evmhogumian r0,r1,r2
+ 348: 10 01 15 ad evmhogsmian r0,r1,r2
+ 34c: 10 01 15 af evmhogsmfan r0,r1,r2
+ 350: 10 01 15 c0 evmwlusianw r0,r1,r2
+ 354: 10 01 15 c1 evmwlssianw r0,r1,r2
+ 358: 10 01 15 c3 evmwlssfanw r0,r1,r2
+ 35c: 10 01 15 c4 evmwhusian r0,r1,r2
+ 360: 10 01 15 c5 evmwhssian r0,r1,r2
+ 364: 10 01 15 c7 evmwhssfan r0,r1,r2
+ 368: 10 01 15 c8 evmwlumianw r0,r1,r2
+ 36c: 10 01 15 c9 evmwlsmianw r0,r1,r2
+ 370: 10 01 15 cb evmwlsmfanw r0,r1,r2
+ 374: 10 01 15 cc evmwhumian r0,r1,r2
+ 378: 10 01 15 cd evmwhsmian r0,r1,r2
+ 37c: 10 01 15 cf evmwhsmfan r0,r1,r2
+ 380: 10 01 15 d3 evmwssfan r0,r1,r2
+ 384: 10 01 15 d8 evmwumian r0,r1,r2
+ 388: 10 01 15 d9 evmwsmian r0,r1,r2
+ 38c: 10 01 15 db evmwsmfan r0,r1,r2
+ 390: 10 01 15 e4 evmwhgumian r0,r1,r2
+ 394: 10 01 15 e5 evmwhgsmian r0,r1,r2
+ 398: 10 01 15 e7 evmwhgssfan r0,r1,r2
+ 39c: 10 01 15 ef evmwhgsmfan r0,r1,r2
+ 3a0: 7c 01 16 3e evlddepx r0,r1,r2
+ 3a4: 7c 01 17 3e evstddepx r0,r1,r2
+ 3a8: 10 01 12 c0 efsadd r0,r1,r2
+ 3ac: 10 01 12 c1 efssub r0,r1,r2
+ 3b0: 10 01 02 c4 efsabs r0,r1
+ 3b4: 10 01 02 c5 efsnabs r0,r1
+ 3b8: 10 01 02 c6 efsneg r0,r1
+ 3bc: 10 01 12 c8 efsmul r0,r1,r2
+ 3c0: 10 01 12 c9 efsdiv r0,r1,r2
+ 3c4: 10 01 12 cc efscmpgt cr0,r1,r2
+ 3c8: 10 01 12 cd efscmplt cr0,r1,r2
+ 3cc: 10 01 12 ce efscmpeq cr0,r1,r2
+ 3d0: 10 00 12 d0 efscfui r0,r2
+ 3d4: 10 00 12 d1 efscfsi r0,r2
+ 3d8: 10 00 12 d2 efscfuf r0,r2
+ 3dc: 10 00 12 d3 efscfsf r0,r2
+ 3e0: 10 00 12 d4 efsctui r0,r2
+ 3e4: 10 00 12 d5 efsctsi r0,r2
+ 3e8: 10 00 12 d6 efsctuf r0,r2
+ 3ec: 10 00 12 d7 efsctsf r0,r2
+ 3f0: 10 00 12 d8 efsctuiz r0,r2
+ 3f4: 10 00 12 da efsctsiz r0,r2
+ 3f8: 10 01 12 dc efststgt cr0,r1,r2
+ 3fc: 10 01 12 dd efststlt cr0,r1,r2
+ 400: 10 01 12 de efststeq cr0,r1,r2
diff -ruN binutils-2.28-lsp/gas/testsuite/gas/ppc/spe.s binutils-2.28-spe2/gas/testsuite/gas/ppc/spe.s
--- binutils-2.28-lsp/gas/testsuite/gas/ppc/spe.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-spe2/gas/testsuite/gas/ppc/spe.s 2017-06-23 17:44:50.951717000 +0300
@@ -0,0 +1,274 @@
+# PA SPE instructions
+ .section ".text"
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ rT,0
+ .equ UIMM, 31
+ .equ UIMM_2, 2
+ .equ UIMM_4, 4
+ .equ UIMM_8, 8
+ .equ SIMM, -16
+ .equ crD, 0
+ .equ crS, 0
+
+ evaddw rS, rA, rB
+ evaddiw rS, rB, UIMM
+ evsubfw rS, rA, rB
+ evsubw rS, rB, rA
+ evsubifw rS, UIMM, rB
+ evsubiw rS, rB, UIMM
+ evabs rS, rA
+ evneg rS, rA
+ evextsb rS, rA
+ evextsh rS, rA
+ evrndw rS, rA
+ evcntlzw rS, rA
+ evcntlsw rS, rA
+ brinc rS, rA, rB
+ evand rS, rA, rB
+ evandc rS, rA, rB
+ evxor rS, rA, rB
+ evmr rS, rA
+ evor rS, rA, rB
+ evnor rS, rA, rB
+ evnot rS, rA
+ eveqv rS, rA, rB
+ evorc rS, rA, rB
+ evnand rS, rA, rB
+ evsrwu rS, rA, rB
+ evsrws rS, rA, rB
+ evsrwiu rS, rA, UIMM
+ evsrwis rS, rA, UIMM
+ evslw rS, rA, rB
+ evslwi rS, rA, UIMM
+ evrlw rS, rA, rB
+ evsplati rS, SIMM
+ evrlwi rS, rA, UIMM
+ evsplatfi rS, SIMM
+ evmergehi rS, rA, rB
+ evmergelo rS, rA, rB
+ evmergehilo rS, rA, rB
+ evmergelohi rS, rA, rB
+ evcmpgtu crD, rA, rB
+ evcmpgts crD, rA, rB
+ evcmpltu crD, rA, rB
+ evcmplts crD, rA, rB
+ evcmpeq crD, rA, rB
+ evsel rS, rA, rB, crS
+ evfsadd rS, rA, rB
+ evfssub rS, rA, rB
+ evfsmadd rS, rA, rB
+ evfsmsub rS, rA, rB
+ evfsabs rS, rA
+ evfsnabs rS, rA
+ evfsneg rS, rA
+ evfsmul rS, rA, rB
+ evfsdiv rS, rA, rB
+ evfsnmadd rS, rA, rB
+ evfsnmsub rS, rA, rB
+ evfscmpgt crD, rA, rB
+ evfscmplt crD, rA, rB
+ evfscmpeq crD, rA, rB
+ evfscfui rS, rB
+ evfscfsi rS, rB
+ evfscfuf rS, rB
+ evfscfsf rS, rB
+ evfsctui rS, rB
+ evfsctsi rS, rB
+ evfsctuf rS, rB
+ evfsctsf rS, rB
+ evfsctuiz rS, rB
+ evfsctsiz rS, rB
+ evfststgt crD, rA, rB
+ evfststlt crD, rA, rB
+ evfststeq crD, rA, rB
+ evlddx rS, rA, rB
+ evldd rS, UIMM_8(rA)
+ evldwx rS, rA, rB
+ evldw rS, UIMM_8(rA)
+ evldhx rS, rA, rB
+ evldh rS, UIMM_8(rA)
+ evlhhesplatx rS, rA, rB
+ evlhhesplat rS, UIMM_2(rA)
+ evlhhousplatx rS, rA, rB
+ evlhhousplat rS, UIMM_2(rA)
+ evlhhossplatx rS, rA, rB
+ evlhhossplat rS, UIMM_2(rA)
+ evlwhex rS, rA, rB
+ evlwhe rS, UIMM_4(rA)
+ evlwhoux rS, rA, rB
+ evlwhou rS, UIMM_4(rA)
+ evlwhosx rS, rA, rB
+ evlwhos rS, UIMM_4(rA)
+ evlwwsplatx rS, rA, rB
+ evlwwsplat rS, UIMM_4(rA)
+ evlwhsplatx rS, rA, rB
+ evlwhsplat rS, UIMM_4(rA)
+ evstddx rS, rA, rB
+ evstdd rS, UIMM_8(rA)
+ evstdwx rS, rA, rB
+ evstdw rS, UIMM_8(rA)
+ evstdhx rS, rA, rB
+ evstdh rS, UIMM_8(rA)
+ evstwhex rS, rA, rB
+ evstwhe rS, UIMM_4(rA)
+ evstwhox rS, rA, rB
+ evstwho rS, UIMM_4(rA)
+ evstwwex rS, rA, rB
+ evstwwe rS, UIMM_4(rA)
+ evstwwox rS, rA, rB
+ evstwwo rS, UIMM_4(rA)
+ evmhessf rS, rA, rB
+ evmhossf rS, rA, rB
+ evmheumi rS, rA, rB
+ evmhesmi rS, rA, rB
+ evmhesmf rS, rA, rB
+ evmhoumi rS, rA, rB
+ evmhosmi rS, rA, rB
+ evmhosmf rS, rA, rB
+ evmhessfa rS, rA, rB
+ evmhossfa rS, rA, rB
+ evmheumia rS, rA, rB
+ evmhesmia rS, rA, rB
+ evmhesmfa rS, rA, rB
+ evmhoumia rS, rA, rB
+ evmhosmia rS, rA, rB
+ evmhosmfa rS, rA, rB
+ evmwlssf rD, rA, rB
+ evmwhssf rS, rA, rB
+ evmwlumi rS, rA, rB
+ evmwlsmf rD, rA, rB
+ evmwhumi rS, rA, rB
+ evmwhsmi rS, rA, rB
+ evmwhsmf rS, rA, rB
+ evmwssf rS, rA, rB
+ evmwumi rS, rA, rB
+ evmwsmi rS, rA, rB
+ evmwsmf rS, rA, rB
+ evmwlssfa rD, rA, rB
+ evmwhssfa rS, rA, rB
+ evmwlumia rS, rA, rB
+ evmwlsmfa rD, rA, rB
+ evmwhumia rS, rA, rB
+ evmwhsmia rS, rA, rB
+ evmwhsmfa rS, rA, rB
+ evmwssfa rS, rA, rB
+ evmwumia rS, rA, rB
+ evmwsmia rS, rA, rB
+ evmwsmfa rS, rA, rB
+ evaddusiaaw rS, rA
+ evaddssiaaw rS, rA
+ evsubfusiaaw rS, rA
+ evsubfssiaaw rS, rA
+ evmra rS, rA
+ evdivws rS, rA, rB
+ evdivwu rS, rA, rB
+ evaddumiaaw rS, rA
+ evaddsmiaaw rS, rA
+ evsubfumiaaw rS, rA
+ evsubfsmiaaw rS, rA
+ evmheusiaaw rS, rA, rB
+ evmhessiaaw rS, rA, rB
+ evmhessfaaw rS, rA, rB
+ evmhousiaaw rS, rA, rB
+ evmhossiaaw rS, rA, rB
+ evmhossfaaw rS, rA, rB
+ evmheumiaaw rS, rA, rB
+ evmhesmiaaw rS, rA, rB
+ evmhesmfaaw rS, rA, rB
+ evmhoumiaaw rS, rA, rB
+ evmhosmiaaw rS, rA, rB
+ evmhosmfaaw rS, rA, rB
+ evmhegumiaa rS, rA, rB
+ evmhegsmiaa rS, rA, rB
+ evmhegsmfaa rS, rA, rB
+ evmhogumiaa rS, rA, rB
+ evmhogsmiaa rS, rA, rB
+ evmhogsmfaa rS, rA, rB
+ evmwlusiaaw rS, rA, rB
+ evmwlssiaaw rS, rA, rB
+ evmwlssfaaw rD, rA, rB
+ evmwhusiaa rD, rA, rB
+ evmwhssmaa rD, rA, rB
+ evmwhssfaa rD, rA, rB
+ evmwlumiaaw rS, rA, rB
+ evmwlsmiaaw rS, rA, rB
+ evmwlsmfaaw rD, rA, rB
+ evmwhumiaa rD, rA, rB
+ evmwhsmiaa rD, rA, rB
+ evmwhsmfaa rD, rA, rB
+ evmwssfaa rS, rA, rB
+ evmwumiaa rS, rA, rB
+ evmwsmiaa rS, rA, rB
+ evmwsmfaa rS, rA, rB
+ evmwhgumiaa rD, rA, rB
+ evmwhgsmiaa rD, rA, rB
+ evmwhgssfaa rD, rA, rB
+ evmwhgsmfaa rD, rA, rB
+ evmheusianw rS, rA, rB
+ evmhessianw rS, rA, rB
+ evmhessfanw rS, rA, rB
+ evmhousianw rS, rA, rB
+ evmhossianw rS, rA, rB
+ evmhossfanw rS, rA, rB
+ evmheumianw rS, rA, rB
+ evmhesmianw rS, rA, rB
+ evmhesmfanw rS, rA, rB
+ evmhoumianw rS, rA, rB
+ evmhosmianw rS, rA, rB
+ evmhosmfanw rS, rA, rB
+ evmhegumian rS, rA, rB
+ evmhegsmian rS, rA, rB
+ evmhegsmfan rS, rA, rB
+ evmhogumian rS, rA, rB
+ evmhogsmian rS, rA, rB
+ evmhogsmfan rS, rA, rB
+ evmwlusianw rS, rA, rB
+ evmwlssianw rS, rA, rB
+ evmwlssfanw rD, rA, rB
+ evmwhusian rD, rA, rB
+ evmwhssian rD, rA, rB
+ evmwhssfan rD, rA, rB
+ evmwlumianw rS, rA, rB
+ evmwlsmianw rS, rA, rB
+ evmwlsmfanw rD, rA, rB
+ evmwhumian rD, rA, rB
+ evmwhsmian rD, rA, rB
+ evmwhsmfan rD, rA, rB
+ evmwssfan rS, rA, rB
+ evmwumian rS, rA, rB
+ evmwsmian rS, rA, rB
+ evmwsmfan rS, rA, rB
+ evmwhgumian rD, rA, rB
+ evmwhgsmian rD, rA, rB
+ evmwhgssfan rD, rA, rB
+ evmwhgsmfan rD, rA, rB
+ evlddepx rT, rA, rB
+ evstddepx rT, rA, rB
+
+;#SPE mapped by macro
+ evsadd rS, rA, rB
+ evssub rS, rA, rB
+ evsabs rS, rA
+ evsnabs rS, rA
+ evsneg rS, rA
+ evsmul rS, rA, rB
+ evsdiv rS, rA, rB
+ evscmpgt crD, rA, rB
+ evsgmplt crD, rA, rB
+ evsgmpeq crD, rA, rB
+ evscfui rS, rB
+ evscfsi rS, rB
+ evscfuf rS, rB
+ evscfsf rS, rB
+ evsctui rS, rB
+ evsctsi rS, rB
+ evsctuf rS, rB
+ evsctsf rS, rB
+ evsctuiz rS, rB
+ evsctsiz rS, rB
+ evststgt crD, rA, rB
+ evststlt crD, rA, rB
+ evststeq crD, rA, rB
diff -ruN binutils-2.28-lsp/include/opcode/ppc.h binutils-2.28-spe2/include/opcode/ppc.h
--- binutils-2.28-lsp/include/opcode/ppc.h 2017-06-23 17:38:44.083243055 +0300
+++ binutils-2.28-spe2/include/opcode/ppc.h 2017-06-23 17:55:36.864599055 +0300
@@ -70,6 +70,8 @@
extern const int powerpc_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const int vle_num_opcodes;
+extern const struct powerpc_opcode spe2_opcodes[];
+extern const int spe2_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
@@ -220,6 +222,9 @@
/* Opcode is supported by e200z4. */
#define PPC_OPCODE_E200Z4 0x80000000000ull
+/* Opcode is only supported by Freescale SPE2 APU. */
+#define PPC_OPCODE_SPE2 0x4000000000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -231,6 +236,12 @@
/* A macro to convert a VLE opcode to a VLE opcode segment. */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
+
+/* A macro to extract the extended opcode from a SPE2 instruction. */
+#define SPE2_XOP(i) ((i) & 0x7ff)
+
+/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
+#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
\f
/* The operands table is an array of struct powerpc_operand. */
diff -ruN binutils-2.28-lsp/opcodes/ppc-dis.c binutils-2.28-spe2/opcodes/ppc-dis.c
--- binutils-2.28-lsp/opcodes/ppc-dis.c 2017-06-23 17:39:16.986783055 +0300
+++ binutils-2.28-spe2/opcodes/ppc-dis.c 2017-06-23 17:56:52.074975055 +0300
@@ -212,13 +212,15 @@
0 },
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
PPC_OPCODE_SPE },
+ { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_SPE,
+ PPC_OPCODE_SPE2 },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500 | PPC_OPCODE_LSP),
+ | PPC_OPCODE_LSP | PPC_OPCODE_SPE2),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
@@ -358,6 +360,8 @@
static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
#define VLE_OPCD_SEGS 32
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
+#define SPE2_OPCD_SEGS 13
+static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1];
/* Calculate opcode table indices to speed up disassembly,
and init dialect. */
@@ -405,6 +409,24 @@
}
}
+ /* SPE2 opcodes */
+ i = spe2_num_opcodes;
+ while (--i >= 0)
+ {
+ unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
+ unsigned seg = SPE2_XOP_TO_SEG (xop);
+
+ spe2_opcd_indices[seg] = i;
+ }
+
+ last = spe2_num_opcodes;
+ for (i = SPE2_OPCD_SEGS; i > 1; --i)
+ {
+ if (spe2_opcd_indices[i] == 0)
+ spe2_opcd_indices[i] = last;
+ last = spe2_opcd_indices[i];
+ }
+
if (info->arch == bfd_arch_powerpc)
powerpc_init_dialect (info);
}
@@ -587,6 +609,61 @@
return NULL;
}
+/* Find a match for INSN in the SPE2 opcode table. */
+
+static const struct powerpc_opcode *
+lookup_spe2 (unsigned long insn)
+{
+ const struct powerpc_opcode *opcode;
+ const struct powerpc_opcode *opcode_end;
+ unsigned op, xop, seg;
+
+ op = PPC_OP (insn);
+ if (op != 0x4)
+ {
+ /* This is not SPE2 insn.
+ * All SPE2 instructions have OP=4 and differs by XOP */
+ return NULL;
+ }
+ xop = SPE2_XOP (insn);
+ seg = SPE2_XOP_TO_SEG (xop);
+
+
+ /* Find the first match in the opcode table for this major opcode. */
+ opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
+ for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
+ opcode < opcode_end;
+ ++opcode)
+ {
+ unsigned long table_opcd = opcode->opcode;
+ unsigned long table_mask = opcode->mask;
+ unsigned long insn2;
+ const unsigned char *opindex;
+ const struct powerpc_operand *operand;
+ int invalid;
+
+ insn2 = insn;
+ if ((insn2 & table_mask) != table_opcd)
+ continue;
+
+ /* Check validity of operands. */
+ invalid = 0;
+ for (opindex = opcode->operands; *opindex != 0; ++opindex)
+ {
+ operand = powerpc_operands + *opindex;
+ if (operand->extract)
+ (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
+ }
+ if (invalid)
+ continue;
+
+ return opcode;
+ }
+
+ return NULL;
+}
+
+
/* Print a PowerPC or POWER instruction. */
static int
@@ -636,7 +713,11 @@
opcode = lookup_vle (insn);
if (opcode != NULL)
insn_is_short = PPC_OP_SE_VLE(opcode->mask);
+ else
+ opcode = lookup_spe2 (insn);
}
+ if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
+ opcode = lookup_spe2 (insn);
if (opcode == NULL)
opcode = lookup_powerpc (insn, dialect);
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
diff -ruN binutils-2.28-lsp/opcodes/ppc-opc.c binutils-2.28-spe2/opcodes/ppc-opc.c
--- binutils-2.28-lsp/opcodes/ppc-opc.c 2017-06-23 22:12:39.138198000 +0300
+++ binutils-2.28-spe2/opcodes/ppc-opc.c 2017-06-23 23:38:05.522746700 +0300
@@ -124,12 +124,17 @@
static long extract_vleui (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vleil (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm1_ex0 (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_evuimm_lt8 (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_off_spe2 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_Ddd (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_Ddd (unsigned long, ppc_cpu_t, int *);
\f
/* The operands table.
@@ -645,7 +650,10 @@
#define FC SH
{ 0x1f, 11, NULL, NULL, 0 },
-#define EVUIMM_LT16 SH + 1
+#define EVUIMM_LT8 SH + 1
+ { 0x1f, 11, insert_evuimm_lt8, NULL, 0 },
+
+#define EVUIMM_LT16 EVUIMM_LT8 + 1
{ 0x1f, 11, insert_evuimm_lt16, NULL, 0 },
/* The SI field in a HTM X form instruction. */
@@ -783,6 +791,8 @@
/* The SIX field in a VX form instruction. */
#define SIX UIM6 + 1
+ /* The MMMM field in a VX form instruction for SPE2 */
+#define MMMM SIX
{ 0xf, 11, NULL, NULL, 0 },
/* The PS field in a VX form instruction. */
@@ -794,7 +804,13 @@
{ 0xf, 6, NULL, NULL, 0 },
/* The other UIMM field in a half word EVX form instruction. */
-#define EVUIMM_2 SHB + 1
+#define EVUIMM_1 SHB + 1
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS },
+
+#define EVUIMM_1_EX0 EVUIMM_1 + 1
+ { 0x1f, 11, insert_evuimm1_ex0, NULL, PPC_OPERAND_PARENS },
+
+#define EVUIMM_2 EVUIMM_1_EX0 + 1
{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
#define EVUIMM_2_EX0 EVUIMM_2 + 1
@@ -817,6 +833,8 @@
/* The WS or DRM field in an X form instruction. */
#define WS EVUIMM_8_EX0 + 1
#define DRM WS
+ /* The NNN field in a VX form instruction for SPE2 */
+#define NNN WS
{ 0x7, 11, NULL, NULL, 0 },
/* PowerPC paired singles extensions. */
@@ -985,6 +1003,22 @@
#define VX_OFF IMM8 + 1
{ 0x3, 0, insert_off_lsp, NULL, 0 },
+
+#define VX_OFF_SPE2 VX_OFF + 1
+ { 0x7, 0, insert_off_spe2, NULL, 0 },
+
+#define BBB VX_OFF_SPE2 + 1
+ { 0x7, 13, NULL, NULL, 0 },
+
+#define DDD BBB + 1
+#define VX_MASK_DDD (VX_MASK & ~0x1)
+ { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
+
+#define HH DDD + 1
+ { 0x3, 13, NULL, NULL, 0 },
+
+#define DD RM
+
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -2326,6 +2360,21 @@
}
static unsigned long
+insert_evuimm1_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x1f)
+ return insn | ((value & 0x1f) << 11);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static unsigned long
insert_evuimm2_ex0 (unsigned long insn,
long value,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
@@ -2371,6 +2420,21 @@
}
static unsigned long
+insert_evuimm_lt8 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >= 0 && value <= 7)
+ return insn | ((value & 0x7) << 11);
+ else
+ {
+ *errmsg = _("UIMM values >7 are illegal");
+ return 0;
+ }
+}
+
+static unsigned long
insert_evuimm_lt16 (unsigned long insn,
long value,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
@@ -2414,6 +2478,44 @@
return 0;
}
}
+
+static unsigned long
+insert_off_spe2 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x7)
+ return insn | (value & 0x7);
+ else
+ {
+ *errmsg = _("invalid offset");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_Ddd (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >= 0 && value <= 0x7)
+ return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2);
+ else
+ {
+ *errmsg = _("invalid Ddd value");
+ return 0;
+ }
+}
+
+static long
+extract_Ddd (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4);
+}
\f
/* Macros used to form opcodes. */
@@ -2653,6 +2755,36 @@
#define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
#define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
+/* Additional format of VX SPE2 form instruction. */
+#define VX_RA_CONST(op, xop, bits11_15) (OP (op) | (((unsigned long)(bits11_15) & 0x1f) << 16) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
+
+#define VX_RB_CONST(op, xop, bits16_20) (OP (op) | (((unsigned long)(bits16_20) & 0x1f) << 11) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
+
+#define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
+
+#define VX_SPE_CRFD(op, xop, bits9_10) (OP (op) | (((unsigned long)(bits9_10) & 0x3) << 21) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
+
+#define VX_SPE2_CLR(op, xop, bit16) (OP (op) | (((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
+
+#define VX_SPE2_SPLATB(op, xop, bits19_20) (OP (op) | (((unsigned long)(bits19_20) & 0x3) << 11) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
+
+#define VX_SPE2_OCTET(op, xop, bits16_17) (OP (op) | (((unsigned long)(bits16_17) & 0x3) << 14) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
+
+#define VX_SPE2_DDHH(op, xop, bit16) (OP (op) | (((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
+
+#define VX_SPE2_HH(op, xop, bit16, bits19_20) (OP (op) |(((unsigned long)(bit16) & 0x1) << 15) | (((unsigned long)(bits19_20) & 0x3) << 11) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
+
+#define VX_SPE2_EVMAR(op, xop) (OP (op) | ((unsigned long)(0x1) << 11) | (((unsigned long)(xop)) & 0x7ff))
+#define VX_SPE2_EVMAR_MASK (VX_SPE2_EVMAR(0x3f, 0x7ff) | ((unsigned long)(0x1) << 11))
+
/* A VX_MASK with the VA field fixed. */
#define VXVA_MASK (VX_MASK | (0x1f << 16))
@@ -3117,6 +3249,7 @@
#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
#define PPCE300 PPC_OPCODE_E300
#define PPCSPE PPC_OPCODE_SPE
+#define PPCSPE2 PPC_OPCODE_SPE2
#define PPCISEL PPC_OPCODE_ISEL
#define PPCEFS PPC_OPCODE_EFS
#define PPCBRLK PPC_OPCODE_BRLOCK
@@ -3460,7 +3593,9 @@
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
@@ -3469,7 +3604,9 @@
{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
+{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
@@ -3677,6 +3814,7 @@
{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
@@ -3687,6 +3825,7 @@
{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3702,8 +3841,10 @@
{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
+{"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3788,16 +3929,24 @@
{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
+{"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3806,6 +3955,10 @@
{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
+{"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3842,21 +3995,33 @@
{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+{"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
+{"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
+{"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
+{"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
@@ -6185,6 +6350,7 @@
{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
+{"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
@@ -6303,6 +6469,7 @@
{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
+{"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
@@ -8086,7 +8253,867 @@
{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
+
+/* old SPE instructions have new names with the same opcodes */
+{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
+{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
+{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"},
+{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"},
+{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"},
+{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"},
+{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"},
+{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"},
+{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"},
+{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"},
+{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"},
+{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"},
+{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"},
+{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"},
+{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"},
+{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"},
+{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"},
+{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"},
+{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"},
+{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"},
+{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"},
+{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"},
+{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"},
+
+/* SPE2 instructions which just are mapped to SPE2 */
+{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"},
+{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"},
+{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"},
+{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"}
+
};
const int powerpc_num_macros =
sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
+
+/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
+const struct powerpc_opcode spe2_opcodes[] = {
+{"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
+{"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
+{"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
+{"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
+{"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
+{"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
+{"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
+{"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
+{"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
+{"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
+{"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
+{"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
+{"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
+{"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}},
+{"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}},
+{"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
+{"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
+{"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
+{"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
+{"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
+{"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}},
+{"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
+{"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
+{"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
+{"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
+{"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
+{"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
+{"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
+{"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
+{"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
+{"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
+{"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
+{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
+{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
+{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"evfsmax", VX (4, 672), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsmin", VX (4, 673), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsaddsub", VX (4, 674), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfssubadd", VX (4, 675), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfssum", VX (4, 676), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsdiff", VX (4, 677), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfssumdiff", VX (4, 678), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsdiffsum", VX (4, 679), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsaddx", VX (4, 680), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfssubx", VX (4, 681), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsaddsubx", VX (4, 682), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfssubaddx", VX (4, 683), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsmulx", VX (4, 684), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsmule", VX (4, 686), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evfsmulo", VX (4, 687), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"efsmax", VX (4, 688), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"efsmin", VX (4, 689), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"efdmax", VX (4, 696), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"efdmin", VX (4, 697), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"efsmadd", VX (4, 706), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"efsmsub", VX (4, 707), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"efsnmadd", VX (4, 714), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"efsnmsub", VX (4, 715), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"efdmadd", VX (4, 738), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
+{"efdmsub", VX (4, 739), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
+{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"efdnmadd", VX (4, 746), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
+{"efdnmsub", VX (4, 747), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
+{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
+{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
+{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}},
+{"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
+{"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
+{"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}},
+{"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}},
+{"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
+{"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
+{"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
+{"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
+{"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
+{"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
+{"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}},
+{"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
+{"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
+{"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
+{"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
+{"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
+{"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
+{"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
+{"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
+{"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}},
+{"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
+{"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
+{"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
+{"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
+{"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
+{"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
+{"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
+{"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}},
+{"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}},
+{"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
+{"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+{"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
+
+};
+
+const int spe2_num_opcodes =
+ sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2017-06-23 20:52 Alexander Fedotov
@ 2017-06-23 20:55 ` Alexander Fedotov
2017-06-23 20:56 ` Alexander Fedotov
2017-06-24 13:18 ` Alan Modra
2017-06-24 13:11 ` Alan Modra
1 sibling, 2 replies; 20+ messages in thread
From: Alexander Fedotov @ 2017-06-23 20:55 UTC (permalink / raw)
To: Alan Modra, binutils; +Cc: Edmar Wienskoski
[-- Attachment #1: Type: text/plain, Size: 302 bytes --]
This patch for LSP instructions support
On Fri, Jun 23, 2017 at 11:51 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> Hello Alan
>
> We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
> All of them are based on 2.28 release.
>
> Best regards,
> Alexander
--
Best regards,
AF
[-- Attachment #2: 2.28-lsp.patch --]
[-- Type: text/x-patch, Size: 118355 bytes --]
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.d binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.d
--- binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.d 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,3 @@
+#name: Test LSP operands checks
+#as: -mvle
+#error-output: lsp-checks.l
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.l binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.l
--- binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.l 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.l 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,92 @@
+[^:]*: Assembler messages:
+[^:]*:22: Error: invalid offset
+[^:]*:23: Error: UIMM values >15 are illegal
+[^:]*:24: Error: UIMM values >15 are illegal
+[^:]*:25: Error: UIMM values >15 are illegal
+[^:]*:26: Error: UIMM values >15 are illegal
+[^:]*:27: Error: UIMM values >15 are illegal
+[^:]*:28: Error: UIMM values >15 are illegal
+[^:]*:29: Error: GPR odd is illegal
+[^:]*:30: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:31: Error: GPR odd is illegal
+[^:]*:32: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:33: Error: GPR odd is illegal
+[^:]*:34: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:35: Error: GPR odd is illegal
+[^:]*:36: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:37: Error: GPR odd is illegal
+[^:]*:38: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:39: Error: GPR odd is illegal
+[^:]*:40: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:41: Error: GPR odd is illegal
+[^:]*:42: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:43: Error: GPR odd is illegal
+[^:]*:44: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:45: Error: GPR odd is illegal
+[^:]*:46: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:47: Error: GPR odd is illegal
+[^:]*:48: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:49: Error: GPR odd is illegal
+[^:]*:50: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:51: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:52: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:53: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:54: Error: GPR odd is illegal
+[^:]*:55: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:56: Error: GPR odd is illegal
+[^:]*:57: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:58: Error: GPR odd is illegal
+[^:]*:59: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:60: Error: GPR odd is illegal
+[^:]*:61: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:62: Error: GPR odd is illegal
+[^:]*:63: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:64: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:65: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:66: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:67: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:68: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:69: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:70: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:71: Error: GPR odd is illegal
+[^:]*:72: Error: UIMM = 00000 is illegal
+[^:]*:73: Error: GPR odd is illegal
+[^:]*:74: Error: UIMM = 00000 is illegal
+[^:]*:75: Error: GPR odd is illegal
+[^:]*:76: Error: UIMM = 00000 is illegal
+[^:]*:77: Error: GPR odd is illegal
+[^:]*:78: Error: UIMM = 00000 is illegal
+[^:]*:79: Error: GPR odd is illegal
+[^:]*:80: Error: UIMM = 00000 is illegal
+[^:]*:81: Error: GPR odd is illegal
+[^:]*:82: Error: UIMM = 00000 is illegal
+[^:]*:83: Error: GPR odd is illegal
+[^:]*:84: Error: UIMM = 00000 is illegal
+[^:]*:85: Error: GPR odd is illegal
+[^:]*:86: Error: UIMM = 00000 is illegal
+[^:]*:87: Error: GPR odd is illegal
+[^:]*:88: Error: UIMM = 00000 is illegal
+[^:]*:89: Error: GPR odd is illegal
+[^:]*:90: Error: UIMM = 00000 is illegal
+[^:]*:91: Error: GPR odd is illegal
+[^:]*:92: Error: UIMM = 00000 is illegal
+[^:]*:93: Error: UIMM = 00000 is illegal
+[^:]*:94: Error: UIMM = 00000 is illegal
+[^:]*:95: Error: UIMM = 00000 is illegal
+[^:]*:96: Error: UIMM = 00000 is illegal
+[^:]*:97: Error: UIMM = 00000 is illegal
+[^:]*:98: Error: GPR odd is illegal
+[^:]*:99: Error: UIMM = 00000 is illegal
+[^:]*:100: Error: GPR odd is illegal
+[^:]*:101: Error: UIMM = 00000 is illegal
+[^:]*:102: Error: GPR odd is illegal
+[^:]*:103: Error: UIMM = 00000 is illegal
+[^:]*:104: Error: GPR odd is illegal
+[^:]*:105: Error: UIMM = 00000 is illegal
+[^:]*:106: Error: UIMM = 00000 is illegal
+[^:]*:107: Error: UIMM = 00000 is illegal
+[^:]*:108: Error: UIMM = 00000 is illegal
+[^:]*:109: Error: UIMM = 00000 is illegal
+[^:]*:110: Error: UIMM = 00000 is illegal
+[^:]*:111: Error: UIMM = 00000 is illegal
+[^:]*:112: Error: UIMM = 00000 is illegal
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.s binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.s
--- binutils-2.28-vle/gas/testsuite/gas/ppc/lsp-checks.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp-checks.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,112 @@
+# Test PA LSP operands checks
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0 ;# ok
+ .equ rD_odd, 1 ;# GPR odd is illegal
+ .equ rS,0 ;# ok
+ .equ rS_odd, 1 ;# GPR odd is illegal
+ .equ UIMM_GT15, 16 ;# UIMM values >15 are illegal
+ .equ UIMM_2, 2 ;# ok
+ .equ UIMM_2_ILL, 3 ;# 3 is not a multiple of 2
+ .equ UIMM_2_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ UIMM_4, 4 ;# ok
+ .equ UIMM_4_ILL, 3 ;# 3 is not a multiple of 4
+ .equ UIMM_4_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ UIMM_8, 8 ;# ok
+ .equ UIMM_8_ILL, 7 ;# 7 is not a multiple of 8
+ .equ UIMM_8_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ offset, 0 ;# invalid offset
+
+ zxtrw rD, rA, rB, offset
+ zvsrhiu rD, rA, UIMM_GT15
+ zvsrhis rD, rA, UIMM_GT15
+ zvslhi rD, rA, UIMM_GT15
+ zvrlhi rD, rA, UIMM_GT15
+ zvslhius rD, rA, UIMM_GT15
+ zvslhiss rD, rA, UIMM_GT15
+ zldd rD_odd, UIMM_8(rA)
+ zldd rD, UIMM_8_ILL(rA)
+ zldw rD_odd, UIMM_8(rA)
+ zldw rD, UIMM_8_ILL(rA)
+ zldh rD_odd, UIMM_8(rA)
+ zldh rD, UIMM_8_ILL(rA)
+ zlwgsfd rD_odd, UIMM_4(rA)
+ zlwgsfd rD, UIMM_4_ILL(rA)
+ zlwwosd rD_odd, UIMM_4(rA)
+ zlwwosd rD, UIMM_4_ILL(rA)
+ zlwhsplatwd rD_odd, UIMM_4(rA)
+ zlwhsplatwd rD, UIMM_4_ILL(rA)
+ zlwhsplatd rD_odd, UIMM_4(rA)
+ zlwhsplatd rD, UIMM_4_ILL(rA)
+ zlwhgwsfd rD_odd, UIMM_4(rA)
+ zlwhgwsfd rD, UIMM_4_ILL(rA)
+ zlwhed rD_odd, UIMM_4(rA)
+ zlwhed rD, UIMM_4_ILL(rA)
+ zlwhosd rD_odd, UIMM_4(rA)
+ zlwhosd rD, UIMM_4_ILL(rA)
+ zlwhoud rD_odd, UIMM_4(rA)
+ zlwh rD, UIMM_4_ILL(rA)
+ zlww rD, UIMM_4_ILL(rA)
+ zlhgwsf rD, UIMM_2_ILL(rA)
+ zlhhsplat rD, UIMM_2_ILL(rA)
+ zstdd rS_odd, UIMM_8(rA)
+ zstdd rS, UIMM_8_ILL(rA)
+ zstdw rS_odd, UIMM_8(rA)
+ zstdw rS, UIMM_8_ILL(rA)
+ zstdh rS_odd, UIMM_8(rA)
+ zstdh rS, UIMM_8_ILL(rA)
+ zstwhed rS_odd, UIMM_4(rA)
+ zstwhed rS, UIMM_4_ILL(rA)
+ zstwhod rS_odd, UIMM_4(rA)
+ zstwhod rS, UIMM_4_ILL(rA)
+ zlhhe rD, UIMM_2_ILL(rA)
+ zlhhos rD, UIMM_2_ILL(rA)
+ zlhhou rD, UIMM_2_ILL(rA)
+ zsthe rS, UIMM_2_ILL(rA)
+ zstho rS, UIMM_2_ILL(rA)
+ zstwh rS, UIMM_4_ILL(rA)
+ zstww rS, UIMM_4_ILL(rA)
+ zlddu rD_odd, UIMM_8(rA)
+ zlddu rD, UIMM_8_ZERO(rA)
+ zldwu rD_odd, UIMM_8(rA)
+ zldwu rD, UIMM_8_ZERO(rA)
+ zldhu rD_odd, UIMM_8(rA)
+ zldhu rD, UIMM_8_ZERO(rA)
+ zlwgsfdu rD_odd, UIMM_4(rA)
+ zlwgsfdu rD, UIMM_4_ZERO(rA)
+ zlwwosdu rD_odd, UIMM_4(rA)
+ zlwwosdu rD, UIMM_4_ZERO(rA)
+ zlwhsplatwdu rD_odd, UIMM_4(rA)
+ zlwhsplatwdu rD, UIMM_4_ZERO(rA)
+ zlwhsplatdu rD_odd, UIMM_4(rA)
+ zlwhsplatdu rD, UIMM_4_ZERO(rA)
+ zlwhgwsfdu rD_odd, UIMM_4(rA)
+ zlwhgwsfdu rD, UIMM_4_ZERO(rA)
+ zlwhedu rD_odd, UIMM_4(rA)
+ zlwhedu rD, UIMM_4_ZERO(rA)
+ zlwhosdu rD_odd, UIMM_4(rA)
+ zlwhosdu rD, UIMM_4_ZERO(rA)
+ zlwhoudu rD_odd, UIMM_4(rA)
+ zlwhoudu rD, UIMM_4_ZERO(rA)
+ zlwhu rD, UIMM_4_ZERO(rA)
+ zlwwu rD, UIMM_4_ZERO(rA)
+ zlhgwsfu rD, UIMM_2_ZERO(rA)
+ zlhhsplatu rD, UIMM_2_ZERO(rA)
+ zstddu rS, UIMM_8_ZERO(rA)
+ zstdwu rS_odd, UIMM_8(rA)
+ zstdwu rS, UIMM_8_ZERO(rA)
+ zstdhu rS_odd, UIMM_8(rA)
+ zstdhu rS, UIMM_8_ZERO(rA)
+ zstwhedu rS_odd, UIMM_4(rA)
+ zstwhedu rS, UIMM_4_ZERO(rA)
+ zstwhodu rS_odd, UIMM_4(rA)
+ zstwhodu rS, UIMM_4_ZERO(rA)
+ zlhheu rD, UIMM_2_ZERO(rA)
+ zlhhosu rD, UIMM_2_ZERO(rA)
+ zlhhouu rD, UIMM_2_ZERO(rA)
+ zstheu rS, UIMM_2_ZERO(rA)
+ zsthou rS, UIMM_2_ZERO(rA)
+ zstwhu rS, UIMM_4_ZERO(rA)
+ zstwwu rS, UIMM_4_ZERO(rA)
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/lsp.d binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp.d
--- binutils-2.28-vle/gas/testsuite/gas/ppc/lsp.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp.d 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,687 @@
+#as: -mvle
+#objdump: -d -Mvle
+#name: Validate LSP instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 7a 00 zvaddih r0,r1,15
+ 4: 10 01 7a 01 zvsubifh r0,r1,15
+ 8: 10 01 12 04 zvaddh r0,r1,r2
+ c: 10 01 12 05 zvsubfh r0,r1,r2
+ 10: 10 01 12 06 zvaddsubfh r0,r1,r2
+ 14: 10 01 12 07 zvsubfaddh r0,r1,r2
+ 18: 10 01 12 0c zvaddhx r0,r1,r2
+ 1c: 10 01 12 0d zvsubfhx r0,r1,r2
+ 20: 10 01 12 0e zvaddsubfhx r0,r1,r2
+ 24: 10 01 12 0f zvsubfaddhx r0,r1,r2
+ 28: 10 01 12 10 zaddwus r0,r1,r2
+ 2c: 10 01 12 11 zsubfwus r0,r1,r2
+ 30: 10 01 12 12 zaddwss r0,r1,r2
+ 34: 10 01 12 13 zsubfwss r0,r1,r2
+ 38: 10 01 12 14 zvaddhus r0,r1,r2
+ 3c: 10 01 12 15 zvsubfhus r0,r1,r2
+ 40: 10 01 12 16 zvaddhss r0,r1,r2
+ 44: 10 01 12 17 zvsubfhss r0,r1,r2
+ 48: 10 01 12 1a zvaddsubfhss r0,r1,r2
+ 4c: 10 01 12 1b zvsubfaddhss r0,r1,r2
+ 50: 10 01 12 1c zvaddhxss r0,r1,r2
+ 54: 10 01 12 1d zvsubfhxss r0,r1,r2
+ 58: 10 01 12 1e zvaddsubfhxss r0,r1,r2
+ 5c: 10 01 12 1f zvsubfaddhxss r0,r1,r2
+ 60: 10 01 12 20 zaddheuw r0,r1,r2
+ 64: 10 01 12 21 zsubfheuw r0,r1,r2
+ 68: 10 01 12 22 zaddhesw r0,r1,r2
+ 6c: 10 01 12 23 zsubfhesw r0,r1,r2
+ 70: 10 01 12 24 zaddhouw r0,r1,r2
+ 74: 10 01 12 25 zsubfhouw r0,r1,r2
+ 78: 10 01 12 26 zaddhosw r0,r1,r2
+ 7c: 10 01 12 27 zsubfhosw r0,r1,r2
+ 80: 10 01 12 2c zvmergehih r0,r1,r2
+ 84: 10 01 12 2d zvmergeloh r0,r1,r2
+ 88: 10 01 12 2e zvmergehiloh r0,r1,r2
+ 8c: 10 01 12 2f zvmergelohih r0,r1,r2
+ 90: 10 01 12 30 zvcmpgthu cr0,r1,r2
+ 94: 10 01 12 30 zvcmpgthu cr0,r1,r2
+ 98: 10 01 12 31 zvcmplthu cr0,r1,r2
+ 9c: 10 01 12 31 zvcmplthu cr0,r1,r2
+ a0: 10 01 12 32 zvcmpeqh cr0,r1,r2
+ a4: 10 01 12 38 zpkswgshfrs r0,r1,r2
+ a8: 10 01 12 39 zpkswgswfrs r0,r1,r2
+ ac: 10 01 12 3a zvpkshgwshfrs r0,r1,r2
+ b0: 10 01 12 3b zvpkswshfrs r0,r1,r2
+ b4: 10 01 12 3c zvpkswuhs r0,r1,r2
+ b8: 10 01 12 3d zvpkswshs r0,r1,r2
+ bc: 10 01 12 3e zvpkuwuhs r0,r1,r2
+ c0: 10 10 02 3f zvsplatih r0,-16
+ c4: 10 10 0a 3f zvsplatfih r0,-16
+ c8: 10 01 2a 3f zcntlsw r0,r1
+ cc: 10 01 32 3f zvcntlzh r0,r1
+ d0: 10 01 3a 3f zvcntlsh r0,r1
+ d4: 10 01 4a 3f znegws r0,r1
+ d8: 10 01 52 3f zvnegh r0,r1
+ dc: 10 01 5a 3f zvneghs r0,r1
+ e0: 10 01 62 3f zvnegho r0,r1
+ e4: 10 01 6a 3f zvneghos r0,r1
+ e8: 10 01 82 3f zrndwh r0,r1
+ ec: 10 01 8a 3f zrndwhss r0,r1
+ f0: 10 01 a2 3f zvabsh r0,r1
+ f4: 10 01 aa 3f zvabshs r0,r1
+ f8: 10 01 b2 3f zabsw r0,r1
+ fc: 10 01 ba 3f zabsws r0,r1
+ 100: 10 01 c2 3f zsatswuw r0,r1
+ 104: 10 01 ca 3f zsatuwsw r0,r1
+ 108: 10 01 d2 3f zsatswuh r0,r1
+ 10c: 10 01 da 3f zsatswsh r0,r1
+ 110: 10 01 e2 3f zvsatshuh r0,r1
+ 114: 10 01 ea 3f zvsatuhsh r0,r1
+ 118: 10 01 f2 3f zsatuwuh r0,r1
+ 11c: 10 01 fa 3f zsatuwsh r0,r1
+ 120: 10 01 12 60 zsatsduw r0,r1,r2
+ 124: 10 01 12 61 zsatsdsw r0,r1,r2
+ 128: 10 01 12 62 zsatuduw r0,r1,r2
+ 12c: 10 01 12 64 zvselh r0,r1,r2
+ 130: 10 01 12 65 zxtrw r0,r1,r2,1
+ 134: 10 01 12 68 zbrminc r0,r1,r2
+ 138: 10 01 12 69 zcircinc r0,r1,r2
+ 13c: 10 01 12 6b zdivwsf r0,r1,r2
+ 140: 10 01 12 70 zvsrhu r0,r1,r2
+ 144: 10 01 12 71 zvsrhs r0,r1,r2
+ 148: 10 01 7a 72 zvsrhiu r0,r1,15
+ 14c: 10 01 7a 73 zvsrhis r0,r1,15
+ 150: 10 01 12 74 zvslh r0,r1,r2
+ 154: 10 01 12 75 zvrlh r0,r1,r2
+ 158: 10 01 7a 76 zvslhi r0,r1,15
+ 15c: 10 01 7a 77 zvrlhi r0,r1,15
+ 160: 10 01 12 78 zvslhus r0,r1,r2
+ 164: 10 01 12 79 zvslhss r0,r1,r2
+ 168: 10 01 7a 7a zvslhius r0,r1,15
+ 16c: 10 01 7a 7b zvslhiss r0,r1,15
+ 170: 10 01 12 7c zslwus r0,r1,r2
+ 174: 10 01 12 7d zslwss r0,r1,r2
+ 178: 10 01 7a 7e zslwius r0,r1,15
+ 17c: 10 01 7a 7f zslwiss r0,r1,15
+ 180: 10 01 14 60 zaddwgui r0,r1,r2
+ 184: 10 01 14 61 zsubfwgui r0,r1,r2
+ 188: 10 01 14 62 zaddd r0,r1,r2
+ 18c: 10 01 14 63 zsubfd r0,r1,r2
+ 190: 10 01 14 64 zvaddsubfw r0,r1,r2
+ 194: 10 01 14 65 zvsubfaddw r0,r1,r2
+ 198: 10 01 14 66 zvaddw r0,r1,r2
+ 19c: 10 01 14 67 zvsubfw r0,r1,r2
+ 1a0: 10 01 14 68 zaddwgsi r0,r1,r2
+ 1a4: 10 01 14 69 zsubfwgsi r0,r1,r2
+ 1a8: 10 01 14 6a zadddss r0,r1,r2
+ 1ac: 10 01 14 6b zsubfdss r0,r1,r2
+ 1b0: 10 01 14 6c zvaddsubfwss r0,r1,r2
+ 1b4: 10 01 14 6d zvsubfaddwss r0,r1,r2
+ 1b8: 10 01 14 6e zvaddwss r0,r1,r2
+ 1bc: 10 01 14 6f zvsubfwss r0,r1,r2
+ 1c0: 10 01 14 70 zaddwgsf r0,r1,r2
+ 1c4: 10 01 14 71 zsubfwgsf r0,r1,r2
+ 1c8: 10 01 14 72 zadddus r0,r1,r2
+ 1cc: 10 01 14 73 zsubfdus r0,r1,r2
+ 1d0: 10 01 14 76 zvaddwus r0,r1,r2
+ 1d4: 10 01 14 77 zvsubfwus r0,r1,r2
+ 1d8: 10 01 04 78 zvunpkhgwsf r0,r1
+ 1dc: 10 01 0c 78 zvunpkhsf r0,r1
+ 1e0: 10 01 14 78 zvunpkhui r0,r1
+ 1e4: 10 01 1c 78 zvunpkhsi r0,r1
+ 1e8: 10 01 24 78 zunpkwgsf r0,r1
+ 1ec: 10 01 14 88 zvdotphgwasmf r0,r1,r2
+ 1f0: 10 01 14 89 zvdotphgwasmfr r0,r1,r2
+ 1f4: 10 01 14 8a zvdotphgwasmfaa r0,r1,r2
+ 1f8: 10 01 14 8b zvdotphgwasmfraa r0,r1,r2
+ 1fc: 10 01 14 8c zvdotphgwasmfan r0,r1,r2
+ 200: 10 01 14 8d zvdotphgwasmfran r0,r1,r2
+ 204: 10 01 14 90 zvmhulgwsmf r0,r1,r2
+ 208: 10 01 14 91 zvmhulgwsmfr r0,r1,r2
+ 20c: 10 01 14 92 zvmhulgwsmfaa r0,r1,r2
+ 210: 10 01 14 93 zvmhulgwsmfraa r0,r1,r2
+ 214: 10 01 14 94 zvmhulgwsmfan r0,r1,r2
+ 218: 10 01 14 95 zvmhulgwsmfran r0,r1,r2
+ 21c: 10 01 14 96 zvmhulgwsmfanp r0,r1,r2
+ 220: 10 01 14 97 zvmhulgwsmfranp r0,r1,r2
+ 224: 10 01 14 98 zmhegwsmf r0,r1,r2
+ 228: 10 01 14 99 zmhegwsmfr r0,r1,r2
+ 22c: 10 01 14 9a zmhegwsmfaa r0,r1,r2
+ 230: 10 01 14 9b zmhegwsmfraa r0,r1,r2
+ 234: 10 01 14 9c zmhegwsmfan r0,r1,r2
+ 238: 10 01 14 9d zmhegwsmfran r0,r1,r2
+ 23c: 10 01 14 a8 zvdotphxgwasmf r0,r1,r2
+ 240: 10 01 14 a9 zvdotphxgwasmfr r0,r1,r2
+ 244: 10 01 14 aa zvdotphxgwasmfaa r0,r1,r2
+ 248: 10 01 14 ab zvdotphxgwasmfraa r0,r1,r2
+ 24c: 10 01 14 ac zvdotphxgwasmfan r0,r1,r2
+ 250: 10 01 14 ad zvdotphxgwasmfran r0,r1,r2
+ 254: 10 01 14 b0 zvmhllgwsmf r0,r1,r2
+ 258: 10 01 14 b1 zvmhllgwsmfr r0,r1,r2
+ 25c: 10 01 14 b2 zvmhllgwsmfaa r0,r1,r2
+ 260: 10 01 14 b3 zvmhllgwsmfraa r0,r1,r2
+ 264: 10 01 14 b4 zvmhllgwsmfan r0,r1,r2
+ 268: 10 01 14 b5 zvmhllgwsmfran r0,r1,r2
+ 26c: 10 01 14 b6 zvmhllgwsmfanp r0,r1,r2
+ 270: 10 01 14 b7 zvmhllgwsmfranp r0,r1,r2
+ 274: 10 01 14 b8 zmheogwsmf r0,r1,r2
+ 278: 10 01 14 b9 zmheogwsmfr r0,r1,r2
+ 27c: 10 01 14 ba zmheogwsmfaa r0,r1,r2
+ 280: 10 01 14 bb zmheogwsmfraa r0,r1,r2
+ 284: 10 01 14 bc zmheogwsmfan r0,r1,r2
+ 288: 10 01 14 bd zmheogwsmfran r0,r1,r2
+ 28c: 10 01 14 c8 zvdotphgwssmf r0,r1,r2
+ 290: 10 01 14 c9 zvdotphgwssmfr r0,r1,r2
+ 294: 10 01 14 ca zvdotphgwssmfaa r0,r1,r2
+ 298: 10 01 14 cb zvdotphgwssmfraa r0,r1,r2
+ 29c: 10 01 14 cc zvdotphgwssmfan r0,r1,r2
+ 2a0: 10 01 14 cd zvdotphgwssmfran r0,r1,r2
+ 2a4: 10 01 14 d0 zvmhuugwsmf r0,r1,r2
+ 2a8: 10 01 14 d1 zvmhuugwsmfr r0,r1,r2
+ 2ac: 10 01 14 d2 zvmhuugwsmfaa r0,r1,r2
+ 2b0: 10 01 14 d3 zvmhuugwsmfraa r0,r1,r2
+ 2b4: 10 01 14 d4 zvmhuugwsmfan r0,r1,r2
+ 2b8: 10 01 14 d5 zvmhuugwsmfran r0,r1,r2
+ 2bc: 10 01 14 d6 zvmhuugwsmfanp r0,r1,r2
+ 2c0: 10 01 14 d7 zvmhuugwsmfranp r0,r1,r2
+ 2c4: 10 01 14 d8 zmhogwsmf r0,r1,r2
+ 2c8: 10 01 14 d9 zmhogwsmfr r0,r1,r2
+ 2cc: 10 01 14 da zmhogwsmfaa r0,r1,r2
+ 2d0: 10 01 14 db zmhogwsmfraa r0,r1,r2
+ 2d4: 10 01 14 dc zmhogwsmfan r0,r1,r2
+ 2d8: 10 01 14 dd zmhogwsmfran r0,r1,r2
+ 2dc: 10 01 14 f0 zvmhxlgwsmf r0,r1,r2
+ 2e0: 10 01 14 f1 zvmhxlgwsmfr r0,r1,r2
+ 2e4: 10 01 14 f2 zvmhxlgwsmfaa r0,r1,r2
+ 2e8: 10 01 14 f3 zvmhxlgwsmfraa r0,r1,r2
+ 2ec: 10 01 14 f4 zvmhxlgwsmfan r0,r1,r2
+ 2f0: 10 01 14 f5 zvmhxlgwsmfran r0,r1,r2
+ 2f4: 10 01 14 f6 zvmhxlgwsmfanp r0,r1,r2
+ 2f8: 10 01 14 f7 zvmhxlgwsmfranp r0,r1,r2
+ 2fc: 10 01 15 00 zmhegui r0,r1,r2
+ 300: 10 01 15 01 zvdotphgaui r0,r1,r2
+ 304: 10 01 15 02 zmheguiaa r0,r1,r2
+ 308: 10 01 15 03 zvdotphgauiaa r0,r1,r2
+ 30c: 10 01 15 04 zmheguian r0,r1,r2
+ 310: 10 01 15 05 zvdotphgauian r0,r1,r2
+ 314: 10 01 15 08 zmhegsi r0,r1,r2
+ 318: 10 01 15 09 zvdotphgasi r0,r1,r2
+ 31c: 10 01 15 0a zmhegsiaa r0,r1,r2
+ 320: 10 01 15 0b zvdotphgasiaa r0,r1,r2
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+ 84c: 10 01 16 c2 zvdotphsuiaa r0,r1,r2
+ 850: 10 01 16 c3 zvdotphsuiaas r0,r1,r2
+ 854: 10 01 16 c4 zvdotphsuian r0,r1,r2
+ 858: 10 01 16 c5 zvdotphsuians r0,r1,r2
+ 85c: 10 01 16 c8 zvdotphssi r0,r1,r2
+ 860: 10 01 16 c9 zvdotphssis r0,r1,r2
+ 864: 10 01 16 ca zvdotphssiaa r0,r1,r2
+ 868: 10 01 16 cb zvdotphssiaas r0,r1,r2
+ 86c: 10 01 16 cc zvdotphssian r0,r1,r2
+ 870: 10 01 16 cd zvdotphssians r0,r1,r2
+ 874: 10 01 16 d0 zvdotphssui r0,r1,r2
+ 878: 10 01 16 d1 zvdotphssuis r0,r1,r2
+ 87c: 10 01 16 d2 zvdotphssuiaa r0,r1,r2
+ 880: 10 01 16 d3 zvdotphssuiaas r0,r1,r2
+ 884: 10 01 16 d4 zvdotphssuian r0,r1,r2
+ 888: 10 01 16 d5 zvdotphssuians r0,r1,r2
+ 88c: 10 01 16 d8 zvdotphssfs r0,r1,r2
+ 890: 10 01 16 d9 zvdotphssfrs r0,r1,r2
+ 894: 10 01 16 da zvdotphssfaas r0,r1,r2
+ 898: 10 01 16 db zvdotphssfraas r0,r1,r2
+ 89c: 10 01 16 dc zvdotphssfans r0,r1,r2
+ 8a0: 10 01 16 dd zvdotphssfrans r0,r1,r2
+ 8a4: 10 01 16 e1 zmwluis r0,r1,r2
+ 8a8: 10 01 16 e2 zmwluiaa r0,r1,r2
+ 8ac: 10 01 16 e3 zmwluiaas r0,r1,r2
+ 8b0: 10 01 16 e4 zmwluian r0,r1,r2
+ 8b4: 10 01 16 e5 zmwluians r0,r1,r2
+ 8b8: 10 01 16 e9 zmwlsis r0,r1,r2
+ 8bc: 10 01 16 eb zmwlsiaas r0,r1,r2
+ 8c0: 10 01 16 ed zmwlsians r0,r1,r2
+ 8c4: 10 01 16 f1 zmwlsuis r0,r1,r2
+ 8c8: 10 01 16 f3 zmwlsuiaas r0,r1,r2
+ 8cc: 10 01 16 f5 zmwlsuians r0,r1,r2
+ 8d0: 10 01 16 f8 zmwsf r0,r1,r2
+ 8d4: 10 01 16 f9 zmwsfr r0,r1,r2
+ 8d8: 10 01 16 fa zmwsfaas r0,r1,r2
+ 8dc: 10 01 16 fb zmwsfraas r0,r1,r2
+ 8e0: 10 01 16 fc zmwsfans r0,r1,r2
+ 8e4: 10 01 16 fd zmwsfrans r0,r1,r2
+ 8e8: 10 01 13 00 zlddx r0,r1,r2
+ 8ec: 10 01 13 01 zldd r0,16\(r1\)
+ 8f0: 10 01 13 02 zldwx r0,r1,r2
+ 8f4: 10 01 13 03 zldw r0,16\(r1\)
+ 8f8: 10 01 13 04 zldhx r0,r1,r2
+ 8fc: 10 01 13 05 zldh r0,16\(r1\)
+ 900: 10 01 13 08 zlwgsfdx r0,r1,r2
+ 904: 10 01 13 09 zlwgsfd r0,8\(r1\)
+ 908: 10 01 13 0a zlwwosdx r0,r1,r2
+ 90c: 10 01 13 0b zlwwosd r0,8\(r1\)
+ 910: 10 01 13 0c zlwhsplatwdx r0,r1,r2
+ 914: 10 01 13 0d zlwhsplatwd r0,8\(r1\)
+ 918: 10 01 13 0e zlwhsplatdx r0,r1,r2
+ 91c: 10 01 13 0f zlwhsplatd r0,8\(r1\)
+ 920: 10 01 13 10 zlwhgwsfdx r0,r1,r2
+ 924: 10 01 13 11 zlwhgwsfd r0,8\(r1\)
+ 928: 10 01 13 12 zlwhedx r0,r1,r2
+ 92c: 10 01 13 13 zlwhed r0,8\(r1\)
+ 930: 10 01 13 14 zlwhosdx r0,r1,r2
+ 934: 10 01 13 15 zlwhosd r0,8\(r1\)
+ 938: 10 01 13 16 zlwhoudx r0,r1,r2
+ 93c: 10 01 13 17 zlwhoud r0,8\(r1\)
+ 940: 10 01 13 18 zlwhx r0,r1,r2
+ 944: 10 01 13 19 zlwh r0,8\(r1\)
+ 948: 10 01 13 1a zlwwx r0,r1,r2
+ 94c: 10 01 13 1b zlww r0,8\(r1\)
+ 950: 10 01 13 1c zlhgwsfx r0,r1,r2
+ 954: 10 01 13 1d zlhgwsf r0,4\(r1\)
+ 958: 10 01 13 1e zlhhsplatx r0,r1,r2
+ 95c: 10 01 13 1f zlhhsplat r0,4\(r1\)
+ 960: 10 01 13 20 zstddx r0,r1,r2
+ 964: 10 01 13 21 zstdd r0,16\(r1\)
+ 968: 10 01 13 22 zstdwx r0,r1,r2
+ 96c: 10 01 13 23 zstdw r0,16\(r1\)
+ 970: 10 01 13 24 zstdhx r0,r1,r2
+ 974: 10 01 13 25 zstdh r0,16\(r1\)
+ 978: 10 01 13 28 zstwhedx r0,r1,r2
+ 97c: 10 01 13 29 zstwhed r0,8\(r1\)
+ 980: 10 01 13 2a zstwhodx r0,r1,r2
+ 984: 10 01 13 2b zstwhod r0,8\(r1\)
+ 988: 10 01 13 30 zlhhex r0,r1,r2
+ 98c: 10 01 13 31 zlhhe r0,4\(r1\)
+ 990: 10 01 13 32 zlhhosx r0,r1,r2
+ 994: 10 01 13 33 zlhhos r0,4\(r1\)
+ 998: 10 01 13 34 zlhhoux r0,r1,r2
+ 99c: 10 01 13 35 zlhhou r0,4\(r1\)
+ 9a0: 10 01 13 38 zsthex r0,r1,r2
+ 9a4: 10 01 13 39 zsthe r0,4\(r1\)
+ 9a8: 10 01 13 3a zsthox r0,r1,r2
+ 9ac: 10 01 13 3b zstho r0,4\(r1\)
+ 9b0: 10 01 13 3c zstwhx r0,r1,r2
+ 9b4: 10 01 13 3d zstwh r0,8\(r1\)
+ 9b8: 10 01 13 3e zstwwx r0,r1,r2
+ 9bc: 10 01 13 3f zstww r0,8\(r1\)
+ 9c0: 10 01 13 40 zlddmx r0,r1,r2
+ 9c4: 10 01 13 41 zlddu r0,16\(r1\)
+ 9c8: 10 01 13 42 zldwmx r0,r1,r2
+ 9cc: 10 01 13 43 zldwu r0,16\(r1\)
+ 9d0: 10 01 13 44 zldhmx r0,r1,r2
+ 9d4: 10 01 13 45 zldhu r0,16\(r1\)
+ 9d8: 10 01 13 48 zlwgsfdmx r0,r1,r2
+ 9dc: 10 01 13 49 zlwgsfdu r0,8\(r1\)
+ 9e0: 10 01 13 4a zlwwosdmx r0,r1,r2
+ 9e4: 10 01 13 4b zlwwosdu r0,8\(r1\)
+ 9e8: 10 01 13 4c zlwhsplatwdmx r0,r1,r2
+ 9ec: 10 01 13 4d zlwhsplatwdu r0,8\(r1\)
+ 9f0: 10 01 13 4e zlwhsplatdmx r0,r1,r2
+ 9f4: 10 01 13 4f zlwhsplatdu r0,8\(r1\)
+ 9f8: 10 01 13 50 zlwhgwsfdmx r0,r1,r2
+ 9fc: 10 01 13 51 zlwhgwsfdu r0,8\(r1\)
+ a00: 10 01 13 52 zlwhedmx r0,r1,r2
+ a04: 10 01 13 53 zlwhedu r0,8\(r1\)
+ a08: 10 01 13 54 zlwhosdmx r0,r1,r2
+ a0c: 10 01 13 55 zlwhosdu r0,8\(r1\)
+ a10: 10 01 13 56 zlwhoudmx r0,r1,r2
+ a14: 10 01 13 57 zlwhoudu r0,8\(r1\)
+ a18: 10 01 13 58 zlwhmx r0,r1,r2
+ a1c: 10 01 13 59 zlwhu r0,8\(r1\)
+ a20: 10 01 13 5a zlwwmx r0,r1,r2
+ a24: 10 01 13 5b zlwwu r0,8\(r1\)
+ a28: 10 01 13 5c zlhgwsfmx r0,r1,r2
+ a2c: 10 01 13 5d zlhgwsfu r0,4\(r1\)
+ a30: 10 01 13 5e zlhhsplatmx r0,r1,r2
+ a34: 10 01 13 5f zlhhsplatu r0,4\(r1\)
+ a38: 10 01 13 60 zstddmx r0,r1,r2
+ a3c: 10 01 13 61 zstddu r0,16\(r1\)
+ a40: 10 01 13 62 zstdwmx r0,r1,r2
+ a44: 10 01 13 63 zstdwu r0,16\(r1\)
+ a48: 10 01 13 64 zstdhmx r0,r1,r2
+ a4c: 10 01 13 65 zstdhu r0,16\(r1\)
+ a50: 10 01 13 68 zstwhedmx r0,r1,r2
+ a54: 10 01 13 69 zstwhedu r0,8\(r1\)
+ a58: 10 01 13 6a zstwhodmx r0,r1,r2
+ a5c: 10 01 13 6b zstwhodu r0,8\(r1\)
+ a60: 10 01 13 70 zlhhemx r0,r1,r2
+ a64: 10 01 13 71 zlhheu r0,4\(r1\)
+ a68: 10 01 13 72 zlhhosmx r0,r1,r2
+ a6c: 10 01 13 73 zlhhosu r0,4\(r1\)
+ a70: 10 01 13 74 zlhhoumx r0,r1,r2
+ a74: 10 01 13 75 zlhhouu r0,4\(r1\)
+ a78: 10 01 13 78 zsthemx r0,r1,r2
+ a7c: 10 01 13 79 zstheu r0,4\(r1\)
+ a80: 10 01 13 7a zsthomx r0,r1,r2
+ a84: 10 01 13 7b zsthou r0,4\(r1\)
+ a88: 10 01 13 7c zstwhmx r0,r1,r2
+ a8c: 10 01 13 7d zstwhu r0,8\(r1\)
+ a90: 10 01 13 7e zstwwmx r0,r1,r2
+ a94: 10 01 13 7f zstwwu r0,8\(r1\)
\ No newline at end of file
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/lsp.s binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp.s
--- binutils-2.28-vle/gas/testsuite/gas/ppc/lsp.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/lsp.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,695 @@
+# PA LSP instructions
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ UIMM, 15 ;#UIMM values >15 are illegal
+ .equ UIMM_2, 4
+ .equ UIMM_4, 8
+ .equ UIMM_8, 16
+ .equ SIMM, -16
+ .equ crD, 0
+ .equ offset, 1
+
+ zvaddih rD, rA, UIMM
+ zvsubifh rD, rA, UIMM
+ zvaddh rD, rA, rB
+ zvsubfh rD, rA, rB
+ zvaddsubfh rD, rA, rB
+ zvsubfaddh rD, rA, rB
+ zvaddhx rD, rA, rB
+ zvsubfhx rD, rA, rB
+ zvaddsubfhx rD, rA, rB
+ zvsubfaddhx rD, rA, rB
+ zaddwus rD, rA, rB
+ zsubfwus rD, rA, rB
+ zaddwss rD, rA, rB
+ zsubfwss rD, rA, rB
+ zvaddhus rD, rA, rB
+ zvsubfhus rD, rA, rB
+ zvaddhss rD, rA, rB
+ zvsubfhss rD, rA, rB
+ zvaddsubfhss rD, rA, rB
+ zvsubfaddhss rD, rA, rB
+ zvaddhxss rD, rA, rB
+ zvsubfhxss rD, rA, rB
+ zvaddsubfhxss rD, rA, rB
+ zvsubfaddhxss rD, rA, rB
+ zaddheuw rD, rA, rB
+ zsubfheuw rD, rA, rB
+ zaddhesw rD, rA, rB
+ zsubfhesw rD, rA, rB
+ zaddhouw rD, rA, rB
+ zsubfhouw rD, rA, rB
+ zaddhosw rD, rA, rB
+ zsubfhosw rD, rA, rB
+ zvmergehih rD, rA, rB
+ zvmergeloh rD, rA, rB
+ zvmergehiloh rD, rA, rB
+ zvmergelohih rD, rA, rB
+ zvcmpgthu crD, rA, rB
+ zvcmpgths crD, rA, rB
+ zvcmplthu crD, rA, rB
+ zvcmplths crD, rA, rB
+ zvcmpeqh crD, rA, rB
+ zpkswgshfrs rD, rA, rB
+ zpkswgswfrs rD, rA, rB
+ zvpkshgwshfrs rD, rA, rB
+ zvpkswshfrs rD, rA, rB
+ zvpkswuhs rD, rA, rB
+ zvpkswshs rD, rA, rB
+ zvpkuwuhs rD, rA, rB
+ zvsplatih rD, SIMM
+ zvsplatfih rD, SIMM
+ zcntlsw rD, rA
+ zvcntlzh rD, rA
+ zvcntlsh rD, rA
+ znegws rD, rA
+ zvnegh rD, rA
+ zvneghs rD, rA
+ zvnegho rD, rA
+ zvneghos rD, rA
+ zrndwh rD, rA
+ zrndwhss rD, rA
+ zvabsh rD, rA
+ zvabshs rD, rA
+ zabsw rD, rA
+ zabsws rD, rA
+ zsatswuw rD, rA
+ zsatuwsw rD, rA
+ zsatswuh rD, rA
+ zsatswsh rD, rA
+ zvsatshuh rD, rA
+ zvsatuhsh rD, rA
+ zsatuwuh rD, rA
+ zsatuwsh rD, rA
+ zsatsduw rD, rA, rB
+ zsatsdsw rD, rA, rB
+ zsatuduw rD, rA, rB
+ zvselh rD, rA, rB
+ zxtrw rD, rA, rB, offset
+ zbrminc rD, rA, rB
+ zcircinc rD, rA, rB
+ zdivwsf rD, rA, rB
+ zvsrhu rD, rA, rB
+ zvsrhs rD, rA, rB
+ zvsrhiu rD, rA, UIMM
+ zvsrhis rD, rA, UIMM
+ zvslh rD, rA, rB
+ zvrlh rD, rA, rB
+ zvslhi rD, rA, UIMM
+ zvrlhi rD, rA, UIMM
+ zvslhus rD, rA, rB
+ zvslhss rD, rA, rB
+ zvslhius rD, rA, UIMM
+ zvslhiss rD, rA, UIMM
+ zslwus rD, rA, rB
+ zslwss rD, rA, rB
+ zslwius rD, rA, UIMM
+ zslwiss rD, rA, UIMM
+ zaddwgui rD, rA, rB
+ zsubfwgui rD, rA, rB
+ zaddd rD, rA, rB
+ zsubfd rD, rA, rB
+ zvaddsubfw rD, rA, rB
+ zvsubfaddw rD, rA, rB
+ zvaddw rD, rA, rB
+ zvsubfw rD, rA, rB
+ zaddwgsi rD, rA, rB
+ zsubfwgsi rD, rA, rB
+ zadddss rD, rA, rB
+ zsubfdss rD, rA, rB
+ zvaddsubfwss rD, rA, rB
+ zvsubfaddwss rD, rA, rB
+ zvaddwss rD, rA, rB
+ zvsubfwss rD, rA, rB
+ zaddwgsf rD, rA, rB
+ zsubfwgsf rD, rA, rB
+ zadddus rD, rA, rB
+ zsubfdus rD, rA, rB
+ zvaddwus rD, rA, rB
+ zvsubfwus rD, rA, rB
+ zvunpkhgwsf rD, rA
+ zvunpkhsf rD, rA
+ zvunpkhui rD, rA
+ zvunpkhsi rD, rA
+ zunpkwgsf rD, rA
+ zvdotphgwasmf rD, rA, rB
+ zvdotphgwasmfr rD, rA, rB
+ zvdotphgwasmfaa rD, rA, rB
+ zvdotphgwasmfraa rD, rA, rB
+ zvdotphgwasmfan rD, rA, rB
+ zvdotphgwasmfran rD, rA, rB
+ zvmhulgwsmf rD, rA, rB
+ zvmhulgwsmfr rD, rA, rB
+ zvmhulgwsmfaa rD, rA, rB
+ zvmhulgwsmfraa rD, rA, rB
+ zvmhulgwsmfan rD, rA, rB
+ zvmhulgwsmfran rD, rA, rB
+ zvmhulgwsmfanp rD, rA, rB
+ zvmhulgwsmfranp rD, rA, rB
+ zmhegwsmf rD, rA, rB
+ zmhegwsmfr rD, rA, rB
+ zmhegwsmfaa rD, rA, rB
+ zmhegwsmfraa rD, rA, rB
+ zmhegwsmfan rD, rA, rB
+ zmhegwsmfran rD, rA, rB
+ zvdotphxgwasmf rD, rA, rB
+ zvdotphxgwasmfr rD, rA, rB
+ zvdotphxgwasmfaa rD, rA, rB
+ zvdotphxgwasmfraa rD, rA, rB
+ zvdotphxgwasmfan rD, rA, rB
+ zvdotphxgwasmfran rD, rA, rB
+ zvmhllgwsmf rD, rA, rB
+ zvmhllgwsmfr rD, rA, rB
+ zvmhllgwsmfaa rD, rA, rB
+ zvmhllgwsmfraa rD, rA, rB
+ zvmhllgwsmfan rD, rA, rB
+ zvmhllgwsmfran rD, rA, rB
+ zvmhllgwsmfanp rD, rA, rB
+ zvmhllgwsmfranp rD, rA, rB
+ zmheogwsmf rD, rA, rB
+ zmheogwsmfr rD, rA, rB
+ zmheogwsmfaa rD, rA, rB
+ zmheogwsmfraa rD, rA, rB
+ zmheogwsmfan rD, rA, rB
+ zmheogwsmfran rD, rA, rB
+ zvdotphgwssmf rD, rA, rB
+ zvdotphgwssmfr rD, rA, rB
+ zvdotphgwssmfaa rD, rA, rB
+ zvdotphgwssmfraa rD, rA, rB
+ zvdotphgwssmfan rD, rA, rB
+ zvdotphgwssmfran rD, rA, rB
+ zvmhuugwsmf rD, rA, rB
+ zvmhuugwsmfr rD, rA, rB
+ zvmhuugwsmfaa rD, rA, rB
+ zvmhuugwsmfraa rD, rA, rB
+ zvmhuugwsmfan rD, rA, rB
+ zvmhuugwsmfran rD, rA, rB
+ zvmhuugwsmfanp rD, rA, rB
+ zvmhuugwsmfranp rD, rA, rB
+ zmhogwsmf rD, rA, rB
+ zmhogwsmfr rD, rA, rB
+ zmhogwsmfaa rD, rA, rB
+ zmhogwsmfraa rD, rA, rB
+ zmhogwsmfan rD, rA, rB
+ zmhogwsmfran rD, rA, rB
+ zvmhxlgwsmf rD, rA, rB
+ zvmhxlgwsmfr rD, rA, rB
+ zvmhxlgwsmfaa rD, rA, rB
+ zvmhxlgwsmfraa rD, rA, rB
+ zvmhxlgwsmfan rD, rA, rB
+ zvmhxlgwsmfran rD, rA, rB
+ zvmhxlgwsmfanp rD, rA, rB
+ zvmhxlgwsmfranp rD, rA, rB
+ zmhegui rD, rA, rB
+ zvdotphgaui rD, rA, rB
+ zmheguiaa rD, rA, rB
+ zvdotphgauiaa rD, rA, rB
+ zmheguian rD, rA, rB
+ zvdotphgauian rD, rA, rB
+ zmhegsi rD, rA, rB
+ zvdotphgasi rD, rA, rB
+ zmhegsiaa rD, rA, rB
+ zvdotphgasiaa rD, rA, rB
+ zmhegsian rD, rA, rB
+ zvdotphgasian rD, rA, rB
+ zmhegsui rD, rA, rB
+ zvdotphgasui rD, rA, rB
+ zmhegsuiaa rD, rA, rB
+ zvdotphgasuiaa rD, rA, rB
+ zmhegsuian rD, rA, rB
+ zvdotphgasuian rD, rA, rB
+ zmhegsmf rD, rA, rB
+ zvdotphgasmf rD, rA, rB
+ zmhegsmfaa rD, rA, rB
+ zvdotphgasmfaa rD, rA, rB
+ zmhegsmfan rD, rA, rB
+ zvdotphgasmfan rD, rA, rB
+ zmheogui rD, rA, rB
+ zvdotphxgaui rD, rA, rB
+ zmheoguiaa rD, rA, rB
+ zvdotphxgauiaa rD, rA, rB
+ zmheoguian rD, rA, rB
+ zvdotphxgauian rD, rA, rB
+ zmheogsi rD, rA, rB
+ zvdotphxgasi rD, rA, rB
+ zmheogsiaa rD, rA, rB
+ zvdotphxgasiaa rD, rA, rB
+ zmheogsian rD, rA, rB
+ zvdotphxgasian rD, rA, rB
+ zmheogsui rD, rA, rB
+ zvdotphxgasui rD, rA, rB
+ zmheogsuiaa rD, rA, rB
+ zvdotphxgasuiaa rD, rA, rB
+ zmheogsuian rD, rA, rB
+ zvdotphxgasuian rD, rA, rB
+ zmheogsmf rD, rA, rB
+ zvdotphxgasmf rD, rA, rB
+ zmheogsmfaa rD, rA, rB
+ zvdotphxgasmfaa rD, rA, rB
+ zmheogsmfan rD, rA, rB
+ zvdotphxgasmfan rD, rA, rB
+ zmhogui rD, rA, rB
+ zvdotphgsui rD, rA, rB
+ zmhoguiaa rD, rA, rB
+ zvdotphgsuiaa rD, rA, rB
+ zmhoguian rD, rA, rB
+ zvdotphgsuian rD, rA, rB
+ zmhogsi rD, rA, rB
+ zvdotphgssi rD, rA, rB
+ zmhogsiaa rD, rA, rB
+ zvdotphgssiaa rD, rA, rB
+ zmhogsian rD, rA, rB
+ zvdotphgssian rD, rA, rB
+ zmhogsui rD, rA, rB
+ zvdotphgssui rD, rA, rB
+ zmhogsuiaa rD, rA, rB
+ zvdotphgssuiaa rD, rA, rB
+ zmhogsuian rD, rA, rB
+ zvdotphgssuian rD, rA, rB
+ zmhogsmf rD, rA, rB
+ zvdotphgssmf rD, rA, rB
+ zmhogsmfaa rD, rA, rB
+ zvdotphgssmfaa rD, rA, rB
+ zmhogsmfan rD, rA, rB
+ zvdotphgssmfan rD, rA, rB
+ zmwgui rD, rA, rB
+ zmwguiaa rD, rA, rB
+ zmwguiaas rD, rA, rB
+ zmwguian rD, rA, rB
+ zmwguians rD, rA, rB
+ zmwgsi rD, rA, rB
+ zmwgsiaa rD, rA, rB
+ zmwgsiaas rD, rA, rB
+ zmwgsian rD, rA, rB
+ zmwgsians rD, rA, rB
+ zmwgsui rD, rA, rB
+ zmwgsuiaa rD, rA, rB
+ zmwgsuiaas rD, rA, rB
+ zmwgsuian rD, rA, rB
+ zmwgsuians rD, rA, rB
+ zmwgsmf rD, rA, rB
+ zmwgsmfr rD, rA, rB
+ zmwgsmfaa rD, rA, rB
+ zmwgsmfraa rD, rA, rB
+ zmwgsmfan rD, rA, rB
+ zmwgsmfran rD, rA, rB
+ zvmhului rD, rA, rB
+ zvmhuluiaa rD, rA, rB
+ zvmhuluiaas rD, rA, rB
+ zvmhuluian rD, rA, rB
+ zvmhuluians rD, rA, rB
+ zvmhuluianp rD, rA, rB
+ zvmhuluianps rD, rA, rB
+ zvmhulsi rD, rA, rB
+ zvmhulsiaa rD, rA, rB
+ zvmhulsiaas rD, rA, rB
+ zvmhulsian rD, rA, rB
+ zvmhulsians rD, rA, rB
+ zvmhulsianp rD, rA, rB
+ zvmhulsianps rD, rA, rB
+ zvmhulsui rD, rA, rB
+ zvmhulsuiaa rD, rA, rB
+ zvmhulsuiaas rD, rA, rB
+ zvmhulsuian rD, rA, rB
+ zvmhulsuians rD, rA, rB
+ zvmhulsuianp rD, rA, rB
+ zvmhulsuianps rD, rA, rB
+ zvmhulsf rD, rA, rB
+ zvmhulsfr rD, rA, rB
+ zvmhulsfaas rD, rA, rB
+ zvmhulsfraas rD, rA, rB
+ zvmhulsfans rD, rA, rB
+ zvmhulsfrans rD, rA, rB
+ zvmhulsfanps rD, rA, rB
+ zvmhulsfranps rD, rA, rB
+ zvmhllui rD, rA, rB
+ zvmhlluiaa rD, rA, rB
+ zvmhlluiaas rD, rA, rB
+ zvmhlluian rD, rA, rB
+ zvmhlluians rD, rA, rB
+ zvmhlluianp rD, rA, rB
+ zvmhlluianps rD, rA, rB
+ zvmhllsi rD, rA, rB
+ zvmhllsiaa rD, rA, rB
+ zvmhllsiaas rD, rA, rB
+ zvmhllsian rD, rA, rB
+ zvmhllsians rD, rA, rB
+ zvmhllsianp rD, rA, rB
+ zvmhllsianps rD, rA, rB
+ zvmhllsui rD, rA, rB
+ zvmhllsuiaa rD, rA, rB
+ zvmhllsuiaas rD, rA, rB
+ zvmhllsuian rD, rA, rB
+ zvmhllsuians rD, rA, rB
+ zvmhllsuianp rD, rA, rB
+ zvmhllsuianps rD, rA, rB
+ zvmhllsf rD, rA, rB
+ zvmhllsfr rD, rA, rB
+ zvmhllsfaas rD, rA, rB
+ zvmhllsfraas rD, rA, rB
+ zvmhllsfans rD, rA, rB
+ zvmhllsfrans rD, rA, rB
+ zvmhllsfanps rD, rA, rB
+ zvmhllsfranps rD, rA, rB
+ zvmhuuui rD, rA, rB
+ zvmhuuuiaa rD, rA, rB
+ zvmhuuuiaas rD, rA, rB
+ zvmhuuuian rD, rA, rB
+ zvmhuuuians rD, rA, rB
+ zvmhuuuianp rD, rA, rB
+ zvmhuuuianps rD, rA, rB
+ zvmhuusi rD, rA, rB
+ zvmhuusiaa rD, rA, rB
+ zvmhuusiaas rD, rA, rB
+ zvmhuusian rD, rA, rB
+ zvmhuusians rD, rA, rB
+ zvmhuusianp rD, rA, rB
+ zvmhuusianps rD, rA, rB
+ zvmhuusui rD, rA, rB
+ zvmhuusuiaa rD, rA, rB
+ zvmhuusuiaas rD, rA, rB
+ zvmhuusuian rD, rA, rB
+ zvmhuusuians rD, rA, rB
+ zvmhuusuianp rD, rA, rB
+ zvmhuusuianps rD, rA, rB
+ zvmhuusf rD, rA, rB
+ zvmhuusfr rD, rA, rB
+ zvmhuusfaas rD, rA, rB
+ zvmhuusfraas rD, rA, rB
+ zvmhuusfans rD, rA, rB
+ zvmhuusfrans rD, rA, rB
+ zvmhuusfanps rD, rA, rB
+ zvmhuusfranps rD, rA, rB
+ zvmhxlui rD, rA, rB
+ zvmhxluiaa rD, rA, rB
+ zvmhxluiaas rD, rA, rB
+ zvmhxluian rD, rA, rB
+ zvmhxluians rD, rA, rB
+ zvmhxluianp rD, rA, rB
+ zvmhxluianps rD, rA, rB
+ zvmhxlsi rD, rA, rB
+ zvmhxlsiaa rD, rA, rB
+ zvmhxlsiaas rD, rA, rB
+ zvmhxlsian rD, rA, rB
+ zvmhxlsians rD, rA, rB
+ zvmhxlsianp rD, rA, rB
+ zvmhxlsianps rD, rA, rB
+ zvmhxlsui rD, rA, rB
+ zvmhxlsuiaa rD, rA, rB
+ zvmhxlsuiaas rD, rA, rB
+ zvmhxlsuian rD, rA, rB
+ zvmhxlsuians rD, rA, rB
+ zvmhxlsuianp rD, rA, rB
+ zvmhxlsuianps rD, rA, rB
+ zvmhxlsf rD, rA, rB
+ zvmhxlsfr rD, rA, rB
+ zvmhxlsfaas rD, rA, rB
+ zvmhxlsfraas rD, rA, rB
+ zvmhxlsfans rD, rA, rB
+ zvmhxlsfrans rD, rA, rB
+ zvmhxlsfanps rD, rA, rB
+ zvmhxlsfranps rD, rA, rB
+ zmheui rD, rA, rB
+ zmheuiaa rD, rA, rB
+ zmheuiaas rD, rA, rB
+ zmheuian rD, rA, rB
+ zmheuians rD, rA, rB
+ zmhesi rD, rA, rB
+ zmhesiaa rD, rA, rB
+ zmhesiaas rD, rA, rB
+ zmhesian rD, rA, rB
+ zmhesians rD, rA, rB
+ zmhesui rD, rA, rB
+ zmhesuiaa rD, rA, rB
+ zmhesuiaas rD, rA, rB
+ zmhesuian rD, rA, rB
+ zmhesuians rD, rA, rB
+ zmhesf rD, rA, rB
+ zmhesfr rD, rA, rB
+ zmhesfaas rD, rA, rB
+ zmhesfraas rD, rA, rB
+ zmhesfans rD, rA, rB
+ zmhesfrans rD, rA, rB
+ zmheoui rD, rA, rB
+ zmheouiaa rD, rA, rB
+ zmheouiaas rD, rA, rB
+ zmheouian rD, rA, rB
+ zmheouians rD, rA, rB
+ zmheosi rD, rA, rB
+ zmheosiaa rD, rA, rB
+ zmheosiaas rD, rA, rB
+ zmheosian rD, rA, rB
+ zmheosians rD, rA, rB
+ zmheosui rD, rA, rB
+ zmheosuiaa rD, rA, rB
+ zmheosuiaas rD, rA, rB
+ zmheosuian rD, rA, rB
+ zmheosuians rD, rA, rB
+ zmheosf rD, rA, rB
+ zmheosfr rD, rA, rB
+ zmheosfaas rD, rA, rB
+ zmheosfraas rD, rA, rB
+ zmheosfans rD, rA, rB
+ zmheosfrans rD, rA, rB
+ zmhoui rD, rA, rB
+ zmhouiaa rD, rA, rB
+ zmhouiaas rD, rA, rB
+ zmhouian rD, rA, rB
+ zmhouians rD, rA, rB
+ zmhosi rD, rA, rB
+ zmhosiaa rD, rA, rB
+ zmhosiaas rD, rA, rB
+ zmhosian rD, rA, rB
+ zmhosians rD, rA, rB
+ zmhosui rD, rA, rB
+ zmhosuiaa rD, rA, rB
+ zmhosuiaas rD, rA, rB
+ zmhosuian rD, rA, rB
+ zmhosuians rD, rA, rB
+ zmhosf rD, rA, rB
+ zmhosfr rD, rA, rB
+ zmhosfaas rD, rA, rB
+ zmhosfraas rD, rA, rB
+ zmhosfans rD, rA, rB
+ zmhosfrans rD, rA, rB
+ zvmhuih rD, rA, rB
+ zvmhuihs rD, rA, rB
+ zvmhuiaah rD, rA, rB
+ zvmhuiaahs rD, rA, rB
+ zvmhuianh rD, rA, rB
+ zvmhuianhs rD, rA, rB
+ zvmhsihs rD, rA, rB
+ zvmhsiaahs rD, rA, rB
+ zvmhsianhs rD, rA, rB
+ zvmhsuihs rD, rA, rB
+ zvmhsuiaahs rD, rA, rB
+ zvmhsuianhs rD, rA, rB
+ zvmhsfh rD, rA, rB
+ zvmhsfrh rD, rA, rB
+ zvmhsfaahs rD, rA, rB
+ zvmhsfraahs rD, rA, rB
+ zvmhsfanhs rD, rA, rB
+ zvmhsfranhs rD, rA, rB
+ zvdotphaui rD, rA, rB
+ zvdotphauis rD, rA, rB
+ zvdotphauiaa rD, rA, rB
+ zvdotphauiaas rD, rA, rB
+ zvdotphauian rD, rA, rB
+ zvdotphauians rD, rA, rB
+ zvdotphasi rD, rA, rB
+ zvdotphasis rD, rA, rB
+ zvdotphasiaa rD, rA, rB
+ zvdotphasiaas rD, rA, rB
+ zvdotphasian rD, rA, rB
+ zvdotphasians rD, rA, rB
+ zvdotphasui rD, rA, rB
+ zvdotphasuis rD, rA, rB
+ zvdotphasuiaa rD, rA, rB
+ zvdotphasuiaas rD, rA, rB
+ zvdotphasuian rD, rA, rB
+ zvdotphasuians rD, rA, rB
+ zvdotphasfs rD, rA, rB
+ zvdotphasfrs rD, rA, rB
+ zvdotphasfaas rD, rA, rB
+ zvdotphasfraas rD, rA, rB
+ zvdotphasfans rD, rA, rB
+ zvdotphasfrans rD, rA, rB
+ zvdotphxaui rD, rA, rB
+ zvdotphxauis rD, rA, rB
+ zvdotphxauiaa rD, rA, rB
+ zvdotphxauiaas rD, rA, rB
+ zvdotphxauian rD, rA, rB
+ zvdotphxauians rD, rA, rB
+ zvdotphxasi rD, rA, rB
+ zvdotphxasis rD, rA, rB
+ zvdotphxasiaa rD, rA, rB
+ zvdotphxasiaas rD, rA, rB
+ zvdotphxasian rD, rA, rB
+ zvdotphxasians rD, rA, rB
+ zvdotphxasui rD, rA, rB
+ zvdotphxasuis rD, rA, rB
+ zvdotphxasuiaa rD, rA, rB
+ zvdotphxasuiaas rD, rA, rB
+ zvdotphxasuian rD, rA, rB
+ zvdotphxasuians rD, rA, rB
+ zvdotphxasfs rD, rA, rB
+ zvdotphxasfrs rD, rA, rB
+ zvdotphxasfaas rD, rA, rB
+ zvdotphxasfraas rD, rA, rB
+ zvdotphxasfans rD, rA, rB
+ zvdotphxasfrans rD, rA, rB
+ zvdotphsui rD, rA, rB
+ zvdotphsuis rD, rA, rB
+ zvdotphsuiaa rD, rA, rB
+ zvdotphsuiaas rD, rA, rB
+ zvdotphsuian rD, rA, rB
+ zvdotphsuians rD, rA, rB
+ zvdotphssi rD, rA, rB
+ zvdotphssis rD, rA, rB
+ zvdotphssiaa rD, rA, rB
+ zvdotphssiaas rD, rA, rB
+ zvdotphssian rD, rA, rB
+ zvdotphssians rD, rA, rB
+ zvdotphssui rD, rA, rB
+ zvdotphssuis rD, rA, rB
+ zvdotphssuiaa rD, rA, rB
+ zvdotphssuiaas rD, rA, rB
+ zvdotphssuian rD, rA, rB
+ zvdotphssuians rD, rA, rB
+ zvdotphssfs rD, rA, rB
+ zvdotphssfrs rD, rA, rB
+ zvdotphssfaas rD, rA, rB
+ zvdotphssfraas rD, rA, rB
+ zvdotphssfans rD, rA, rB
+ zvdotphssfrans rD, rA, rB
+ zmwluis rD, rA, rB
+ zmwluiaa rD, rA, rB
+ zmwluiaas rD, rA, rB
+ zmwluian rD, rA, rB
+ zmwluians rD, rA, rB
+ zmwlsis rD, rA, rB
+ zmwlsiaas rD, rA, rB
+ zmwlsians rD, rA, rB
+ zmwlsuis rD, rA, rB
+ zmwlsuiaas rD, rA, rB
+ zmwlsuians rD, rA, rB
+ zmwsf rD, rA, rB
+ zmwsfr rD, rA, rB
+ zmwsfaas rD, rA, rB
+ zmwsfraas rD, rA, rB
+ zmwsfans rD, rA, rB
+ zmwsfrans rD, rA, rB
+ zlddx rD, rA, rB
+ zldd rD, UIMM_8(rA)
+ zldwx rD, rA, rB
+ zldw rD, UIMM_8(rA)
+ zldhx rD, rA, rB
+ zldh rD, UIMM_8(rA)
+ zlwgsfdx rD, rA, rB
+ zlwgsfd rD, UIMM_4(rA)
+ zlwwosdx rD, rA, rB
+ zlwwosd rD, UIMM_4(rA)
+ zlwhsplatwdx rD, rA, rB
+ zlwhsplatwd rD, UIMM_4(rA)
+ zlwhsplatdx rD, rA, rB
+ zlwhsplatd rD, UIMM_4(rA)
+ zlwhgwsfdx rD, rA, rB
+ zlwhgwsfd rD, UIMM_4(rA)
+ zlwhedx rD, rA, rB
+ zlwhed rD, UIMM_4(rA)
+ zlwhosdx rD, rA, rB
+ zlwhosd rD, UIMM_4(rA)
+ zlwhoudx rD, rA, rB
+ zlwhoud rD, UIMM_4(rA)
+ zlwhx rD, rA, rB
+ zlwh rD, UIMM_4(rA)
+ zlwwx rD, rA, rB
+ zlww rD, UIMM_4(rA)
+ zlhgwsfx rD, rA, rB
+ zlhgwsf rD, UIMM_2(rA)
+ zlhhsplatx rD, rA, rB
+ zlhhsplat rD, UIMM_2(rA)
+ zstddx rS, rA, rB
+ zstdd rS, UIMM_8(rA)
+ zstdwx rS, rA, rB
+ zstdw rS, UIMM_8(rA)
+ zstdhx rS, rA, rB
+ zstdh rS, UIMM_8(rA)
+ zstwhedx rS, rA, rB
+ zstwhed rS, UIMM_4(rA)
+ zstwhodx rS, rA, rB
+ zstwhod rS, UIMM_4(rA)
+ zlhhex rS, rA, rB
+ zlhhe rD, UIMM_2(rA)
+ zlhhosx rS, rA, rB
+ zlhhos rD, UIMM_2(rA)
+ zlhhoux rS, rA, rB
+ zlhhou rD, UIMM_2(rA)
+ zsthex rS, rA, rB
+ zsthe rS, UIMM_2(rA)
+ zsthox rS, rA, rB
+ zstho rS, UIMM_2(rA)
+ zstwhx rS, rA, rB
+ zstwh rS, UIMM_4(rA)
+ zstwwx rS, rA, rB
+ zstww rS, UIMM_4(rA)
+ zlddmx rD, rA, rB
+ zlddu rD, UIMM_8(rA)
+ zldwmx rD, rA, rB
+ zldwu rD, UIMM_8(rA)
+ zldhmx rD, rA, rB
+ zldhu rD, UIMM_8(rA)
+ zlwgsfdmx rD, rA, rB
+ zlwgsfdu rD, UIMM_4(rA)
+ zlwwosdmx rD, rA, rB
+ zlwwosdu rD, UIMM_4(rA)
+ zlwhsplatwdmx rD, rA, rB
+ zlwhsplatwdu rD, UIMM_4(rA)
+ zlwhsplatdmx rD, rA, rB
+ zlwhsplatdu rD, UIMM_4(rA)
+ zlwhgwsfdmx rD, rA, rB
+ zlwhgwsfdu rD, UIMM_4(rA)
+ zlwhedmx rD, rA, rB
+ zlwhedu rD, UIMM_4(rA)
+ zlwhosdmx rD, rA, rB
+ zlwhosdu rD, UIMM_4(rA)
+ zlwhoudmx rD, rA, rB
+ zlwhoudu rD, UIMM_4(rA)
+ zlwhmx rD, rA, rB
+ zlwhu rD, UIMM_4(rA)
+ zlwwmx rD, rA, rB
+ zlwwu rD, UIMM_4(rA)
+ zlhgwsfmx rD, rA, rB
+ zlhgwsfu rD, UIMM_2(rA)
+ zlhhsplatmx rD, rA, rB
+ zlhhsplatu rD, UIMM_2(rA)
+ zstddmx rS, rA, rB
+ zstddu rS, UIMM_8(rA)
+ zstdwmx rS, rA, rB
+ zstdwu rS, UIMM_8(rA)
+ zstdhmx rS, rA, rB
+ zstdhu rS, UIMM_8(rA)
+ zstwhedmx rS, rA, rB
+ zstwhedu rS, UIMM_4(rA)
+ zstwhodmx rD, rA, rB
+ zstwhodu rS, UIMM_4(rA)
+ zlhhemx rD, rA, rB
+ zlhheu rD, UIMM_2(rA)
+ zlhhosmx rD, rA, rB
+ zlhhosu rD, UIMM_2(rA)
+ zlhhoumx rD, rA, rB
+ zlhhouu rD, UIMM_2(rA)
+ zsthemx rS, rA, rB
+ zstheu rS, UIMM_2(rA)
+ zsthomx rS, rA, rB
+ zsthou rS, UIMM_2(rA)
+ zstwhmx rS, rA, rB
+ zstwhu rS, UIMM_4(rA)
+ zstwwmx rS, rA, rB
+ zstwwu rS, UIMM_4(rA)
+
diff -ruN binutils-2.28-vle/gas/testsuite/gas/ppc/ppc.exp binutils-2.28-lsp/gas/testsuite/gas/ppc/ppc.exp
--- binutils-2.28-vle/gas/testsuite/gas/ppc/ppc.exp 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-lsp/gas/testsuite/gas/ppc/ppc.exp 2017-06-23 17:46:07.285531055 +0300
@@ -59,6 +59,8 @@
run_dump_test "vle-simple-4"
run_dump_test "vle-simple-5"
run_dump_test "vle-simple-6"
+ run_dump_test "lsp"
+ run_dump_test "lsp-checks"
}
}
diff -ruN binutils-2.28-vle/include/opcode/ppc.h binutils-2.28-lsp/include/opcode/ppc.h
--- binutils-2.28-vle/include/opcode/ppc.h 2017-06-23 17:06:46.227871056 +0300
+++ binutils-2.28-lsp/include/opcode/ppc.h 2017-06-23 17:38:44.083243055 +0300
@@ -194,6 +194,9 @@
/* Opcode is only supported by Power8 architecture. */
#define PPC_OPCODE_POWER8 0x2000000000ull
+/* Opcode is supported by PowerPC LSP */
+#define PPC_OPCODE_LSP 0x8000000000000000ull
+
/* Opcode which is supported by the Hardware Transactional Memory extension. */
/* Currently, this is the same as the POWER8 mask. If another cpu comes out
that isn't a superset of POWER8, we can define this to its own mask. */
diff -ruN binutils-2.28-vle/opcodes/ppc-dis.c binutils-2.28-lsp/opcodes/ppc-dis.c
--- binutils-2.28-vle/opcodes/ppc-dis.c 2017-06-23 17:16:54.219715056 +0300
+++ binutils-2.28-lsp/opcodes/ppc-dis.c 2017-06-23 17:39:16.986783055 +0300
@@ -218,7 +218,7 @@
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500),
+ | PPC_OPCODE_E500 | PPC_OPCODE_LSP),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
diff -ruN binutils-2.28-vle/opcodes/ppc-opc.c binutils-2.28-lsp/opcodes/ppc-opc.c
--- binutils-2.28-vle/opcodes/ppc-opc.c 2017-06-23 22:12:03.648462000 +0300
+++ binutils-2.28-lsp/opcodes/ppc-opc.c 2017-06-23 22:12:39.138198000 +0300
@@ -124,6 +124,12 @@
static long extract_vleui (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vleil (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
+static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
\f
/* The operands table.
@@ -576,9 +582,13 @@
#define RD RS
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
+#define RD_EVEN RS + 1
+#define RS_EVEN RD_EVEN
+ { 0x1f, 21, insert_rD_rS_even, NULL, PPC_OPERAND_GPR },
+
/* The RS and RT fields of the DS form stq and DQ form lq instructions,
which have special value restrictions. */
-#define RSQ RS + 1
+#define RSQ RS_EVEN + 1
#define RTQ RSQ
{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
@@ -635,8 +645,11 @@
#define FC SH
{ 0x1f, 11, NULL, NULL, 0 },
+#define EVUIMM_LT16 SH + 1
+ { 0x1f, 11, insert_evuimm_lt16, NULL, 0 },
+
/* The SI field in a HTM X form instruction. */
-#define HTM_SI SH + 1
+#define HTM_SI EVUIMM_LT16 + 1
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
/* The SH field in an MD form instruction. This is split. */
@@ -784,16 +797,25 @@
#define EVUIMM_2 SHB + 1
{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_2_EX0 EVUIMM_2 + 1
+ { 0x3e, 10, insert_evuimm2_ex0, NULL, PPC_OPERAND_PARENS },
+
/* The other UIMM field in a word EVX form instruction. */
-#define EVUIMM_4 EVUIMM_2 + 1
+#define EVUIMM_4 EVUIMM_2_EX0 + 1
{ 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_4_EX0 EVUIMM_4 + 1
+ { 0x7c, 9, insert_evuimm4_ex0, NULL, PPC_OPERAND_PARENS },
+
/* The other UIMM field in a double EVX form instruction. */
-#define EVUIMM_8 EVUIMM_4 + 1
+#define EVUIMM_8 EVUIMM_4_EX0 + 1
{ 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_8_EX0 EVUIMM_8 + 1
+ { 0xf8, 8, insert_evuimm8_ex0, NULL, PPC_OPERAND_PARENS },
+
/* The WS or DRM field in an X form instruction. */
-#define WS EVUIMM_8 + 1
+#define WS EVUIMM_8_EX0 + 1
#define DRM WS
{ 0x7, 11, NULL, NULL, 0 },
@@ -960,6 +982,9 @@
/* The 8-bit IMM8 field in a XX1 form instruction. */
#define IMM8 IH + 1
{ 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
+
+#define VX_OFF IMM8 + 1
+ { 0x3, 0, insert_off_lsp, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -2300,6 +2325,95 @@
return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
}
+static unsigned long
+insert_evuimm2_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x3e)
+ return insn | ((value & 0x3e) << 10);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_evuimm4_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x7c)
+ return insn | ((value & 0x7c) << 9);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_evuimm8_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0xf8)
+ return insn | ((value & 0xf8) << 8);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_evuimm_lt16 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >= 0 && value <= 15)
+ return insn | ((value & 0xf) << 11);
+ else
+ {
+ *errmsg = _("UIMM values >15 are illegal");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_rD_rS_even (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if ((value & 0x1) == 0)
+ return insn | ((value & 0x1e) << 21);
+ else
+ {
+ *errmsg = _("GPR odd is illegal");
+ return 0;
+ }
+}
+
+static unsigned long
+insert_off_lsp (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x3)
+ return insn | (value & 0x3);
+ else
+ {
+ *errmsg = _("invalid offset");
+ return 0;
+ }
+}
\f
/* Macros used to form opcodes. */
@@ -2532,6 +2646,13 @@
/* The mask for an VX form instruction. */
#define VX_MASK VX(0x3f, 0x7ff)
+/* A VX LSP form instruction. */
+#define VX_LSP(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xffff))
+
+/* The mask for an VX LSP form instruction. */
+#define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
+#define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
+
/* A VX_MASK with the VA field fixed. */
#define VXVA_MASK (VX_MASK | (0x1f << 16))
@@ -3010,6 +3131,7 @@
#define E500 PPC_OPCODE_E500
#define E6500 PPC_OPCODE_E6500
#define PPCVLE PPC_OPCODE_VLE
+#define PPCLSP PPC_OPCODE_LSP
#define PPCHTM PPC_OPCODE_HTM
#define E200Z4 PPC_OPCODE_E200Z4
/* The list of embedded processors that use the embedded operand ordering
@@ -7019,6 +7141,686 @@
{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
+/* by major opcode */
+{"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
+{"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
+{"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}},
+{"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
+{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
+{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
+{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
+{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
+{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
+{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
+{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
+{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
+{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
+{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
+{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
+{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
+{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
+{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
+{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
+{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
+{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
+{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
+
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
@ 2017-06-23 20:52 Alexander Fedotov
2017-06-23 20:55 ` Alexander Fedotov
2017-06-24 13:11 ` Alan Modra
0 siblings, 2 replies; 20+ messages in thread
From: Alexander Fedotov @ 2017-06-23 20:52 UTC (permalink / raw)
To: Alan Modra, binutils; +Cc: Edmar Wienskoski
[-- Attachment #1: Type: text/plain, Size: 144 bytes --]
Hello Alan
We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
All of them are based on 2.28 release.
Best regards,
Alexander
[-- Attachment #2: 2.28-vle.patch --]
[-- Type: text/x-patch, Size: 18120 bytes --]
diff -ruN binutils-2.28/bfd/elf32-ppc.c binutils-2.28-vle/bfd/elf32-ppc.c
--- binutils-2.28/bfd/elf32-ppc.c 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/bfd/elf32-ppc.c 2017-06-23 22:01:57.953766000 +0300
@@ -171,6 +171,9 @@
#define NOP 0x60000000
#define SUB_11_11_12 0x7d6c5850
+/* VLE some instructions */
+#define E_B 0x78000000
+
/* Offset of tp and dtp pointers from start of TLS block. */
#define TP_OFFSET 0x7000
#define DTP_OFFSET 0x8000
@@ -1444,6 +1447,21 @@
0x1fffffe, /* dst_mask */
TRUE), /* pcrel_offset */
+ /* A relative 24 bit branch. */
+ HOWTO (R_PPC_VLE_PLTREL24, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 24, /* bitsize */
+ TRUE, /* pc_relative */
+ 1, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ ppc_elf_unhandled_reloc, /* special_function */
+ "R_PPC_VLE_PLTREL24", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1fffffe, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
/* The 16 LSBS in split16a format. */
HOWTO (R_PPC_VLE_LO16A, /* type */
0, /* rightshift */
@@ -1656,6 +1674,21 @@
0x3e007ff, /* dst_mask */
FALSE), /* pcrel_offset */
+ /* e_li split20 format. */
+ HOWTO (R_PPC_VLE_ADDR20, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 20, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_ADDR20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
HOWTO (R_PPC_IRELATIVE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -2463,6 +2496,14 @@
return 0;
}
+static bfd_boolean
+ppc_elf_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
+{
+ if (hdr->sh_flags & SHF_PPC_VLE)
+ *flags |= SEC_PPC_VLE;
+ return TRUE;
+}
+
/* Return address for Ith PLT stub in section PLT, for relocation REL
or (bfd_vma) -1 if it should not be included. */
@@ -2511,6 +2552,8 @@
{
if ((asect->flags & SEC_SORT_ENTRIES) != 0)
shdr->sh_type = SHT_ORDERED;
+ if ((asect->flags & SEC_PPC_VLE) != 0)
+ shdr->sh_flags |= SHF_PPC_VLE;
return TRUE;
}
@@ -4247,6 +4290,7 @@
case R_PPC_VLE_HI16D:
case R_PPC_VLE_HA16A:
case R_PPC_VLE_HA16D:
+ case R_PPC_VLE_ADDR20:
break;
case R_PPC_EMB_SDA2REL:
@@ -4294,6 +4338,7 @@
break;
case R_PPC_PLTREL24:
+ case R_PPC_VLE_PLTREL24:
if (h == NULL)
break;
/* Fall through */
@@ -4365,6 +4410,7 @@
case R_PPC_NONE:
case R_PPC_max:
case R_PPC_RELAX:
+ case R_PPC_VLE_RELAX:
case R_PPC_RELAX_PLT:
case R_PPC_RELAX_PLTREL24:
case R_PPC_16DX_HA:
@@ -4965,6 +5011,23 @@
insn |= value & 0x7ff;
bfd_put_32 (input_bfd, insn, loc);
}
+
+static void
+ppc_elf_vle_split20 (bfd *output_bfd, bfd_byte *loc, bfd_vma value)
+{
+ unsigned int insn;
+
+ insn = bfd_get_32 (output_bfd, loc);
+ /* We have an li20 field, bits 17..20, 11..15, 21..31. */
+ /* Top 4 bits of value to 17..20. */
+ insn |= (value & 0xf0000) >> 5;
+ /* Next 5 bits of the value to 11..15. */
+ insn |= (value & 0xf800) << 5;
+ /* And the final 11 bits of the value to bits 21 to 31. */
+ insn |= value & 0x7ff;
+ bfd_put_32 (output_bfd, insn, loc);
+}
+
\f
/* Choose which PLT scheme to use, and set .plt flags appropriately.
Returns -1 on error, 0 for old PLT, 1 for new PLT. */
@@ -6907,6 +6970,13 @@
0x4e800420, /* bctr */
};
+typedef enum ppc_target_stub_entry_type
+ {
+ stub_entry_type_ppc = 0,
+ stub_entry_type_vle
+ }
+ppc_target_stub_entry_type;
+
static const int stub_entry[] =
{
0x3d800000, /* lis 12,xxx@ha */
@@ -6915,6 +6985,15 @@
0x4e800420, /* bctr */
};
+/* Keep the same size as stub_entry */
+static const int stub_entry_vle[] =
+ {
+ 0x7180e000, /* e_lis 12,xxx@ha */
+ 0x1d8c0000, /* e_add16i 12,12,xxx@l */
+ 0x7d8903a6, /* mtctr 12 */
+ 0x00064400, /* se_bctr, se_nop (size padding) */
+ };
+
struct ppc_elf_relax_info
{
unsigned int workaround_size;
@@ -6955,6 +7034,7 @@
bfd_size_type trampbase, trampoff, newsize, picfixup_size;
asection *got2;
bfd_boolean maybe_pasted;
+ ppc_target_stub_entry_type target_stub_type = 0;
*again = FALSE;
@@ -7035,21 +7115,43 @@
struct elf_link_hash_entry *h;
struct plt_entry **plist;
unsigned char sym_type;
+ reloc_howto_type *current_howto;
+ current_howto = NULL;
switch (r_type)
{
case R_PPC_REL24:
case R_PPC_LOCAL24PC:
case R_PPC_PLTREL24:
+ target_stub_type = stub_entry_type_ppc;
max_branch_offset = 1 << 25;
break;
case R_PPC_REL14:
case R_PPC_REL14_BRTAKEN:
case R_PPC_REL14_BRNTAKEN:
+ target_stub_type = stub_entry_type_ppc;
max_branch_offset = 1 << 15;
break;
+ case R_PPC_VLE_REL24:
+ target_stub_type = stub_entry_type_vle;
+ max_branch_offset = 1 << 25;
+ current_howto = ppc_elf_howto_table[r_type];
+ break;
+
+ case R_PPC_VLE_REL15:
+ target_stub_type = stub_entry_type_vle;
+ max_branch_offset = 1 << 16;
+ current_howto = ppc_elf_howto_table[r_type];
+ break;
+
+ case R_PPC_VLE_REL8:
+ target_stub_type = stub_entry_type_vle;
+ max_branch_offset = 1 << 9;
+ current_howto = ppc_elf_howto_table[r_type];
+ break;
+
case R_PPC_ADDR16_HA:
if (htab->params->pic_fixup > 0)
break;
@@ -7297,9 +7399,25 @@
symaddr = tsec->output_section->vma + tsec->output_offset + toff;
reladdr = isec->output_section->vma + isec->output_offset + roff;
- if (symaddr - reladdr + max_branch_offset
- < 2 * max_branch_offset)
- continue;
+
+ /* I don't trust the relocation check using ' ... < (2 * max_branch_offset)'
+ * Check for overflow using the bfd API first.
+ */
+ if (current_howto) /* current_howto is not necessarily defined for
+ all reloc types above, but use it if it is defined */
+ {
+ if (bfd_check_overflow (current_howto->complain_on_overflow,
+ current_howto->bitsize,
+ current_howto->rightshift,
+ bfd_arch_bits_per_address(abfd),
+ (symaddr-reladdr)) == bfd_reloc_ok )
+ continue;
+ }
+ else
+ {
+ if (((symaddr - reladdr) + max_branch_offset) < (2 * max_branch_offset))
+ continue;
+ }
}
/* Look for an existing fixup to this address. */
@@ -7328,7 +7446,7 @@
size = 4 * ARRAY_SIZE (stub_entry);
insn_offset = 0;
}
- stub_rtype = R_PPC_RELAX;
+ stub_rtype = (target_stub_type == stub_entry_type_vle) ? R_PPC_VLE_RELAX : R_PPC_RELAX;
if (tsec == htab->elf.splt
|| tsec == htab->glink)
{
@@ -7385,10 +7503,21 @@
case R_PPC_REL24:
case R_PPC_LOCAL24PC:
case R_PPC_PLTREL24:
- t0 = bfd_get_32 (abfd, hit_addr);
- t0 &= ~0x3fffffc;
- t0 |= val & 0x3fffffc;
- bfd_put_32 (abfd, t0, hit_addr);
+ if (r_type == R_PPC_PLTREL24
+ && (elf_section_flags (isec) & SHF_PPC_VLE) != 0)
+ {
+ t0 = bfd_get_32 (abfd, hit_addr);
+ t0 &= ~0x01fffffe;
+ t0 |= val & 0x01fffffe;
+ bfd_put_32 (abfd, t0, hit_addr);
+ }
+ else
+ {
+ t0 = bfd_get_32 (abfd, hit_addr);
+ t0 &= ~0x3fffffc;
+ t0 |= val & 0x3fffffc;
+ bfd_put_32 (abfd, t0, hit_addr);
+ }
break;
case R_PPC_REL14:
@@ -7399,6 +7528,27 @@
t0 |= val & 0xfffc;
bfd_put_32 (abfd, t0, hit_addr);
break;
+
+ case R_PPC_VLE_REL24:
+ t0 = bfd_get_32 (abfd, hit_addr);
+ t0 &= ~0x01fffffe;
+ t0 |= val & 0x01fffffe;
+ bfd_put_32 (abfd, t0, hit_addr);
+ break;
+
+ case R_PPC_VLE_REL15:
+ t0 = bfd_get_32 (abfd, hit_addr);
+ t0 &= ~0xfffe;
+ t0 |= val & 0xfffe;
+ bfd_put_32 (abfd, t0, hit_addr);
+ break;
+
+ case R_PPC_VLE_REL8:
+ t0 = bfd_get_32 (abfd, hit_addr);
+ t0 &= ~0xff;
+ t0 |= val & 0xff;
+ bfd_put_32 (abfd, t0, hit_addr);
+ break;
}
}
@@ -9043,6 +9193,7 @@
/* Fall through. */
case R_PPC_RELAX:
+ case R_PPC_VLE_RELAX:
{
const int *stub;
size_t size;
@@ -9063,8 +9214,8 @@
}
else
{
- stub = stub_entry;
- size = ARRAY_SIZE (stub_entry);
+ stub = (r_type == R_PPC_VLE_RELAX) ? stub_entry_vle : stub_entry;
+ size = ARRAY_SIZE (stub_entry); /* stub_entry and stub_entry_vle must be same size */
}
relocation += addend;
@@ -9072,10 +9223,23 @@
relocation = 0;
/* First insn is HA, second is LO. */
- insn = *stub++;
- insn |= ((relocation + 0x8000) >> 16) & 0xffff;
- bfd_put_32 (input_bfd, insn, contents + insn_offset);
- insn_offset += 4;
+ if (r_type == R_PPC_VLE_RELAX)
+ {
+ /* Write e_lis insn is @ha type relocation */
+ unsigned ha_val;
+ insn = *stub++;
+ ha_val = ((relocation + 0x8000) >> 16) & 0xffff;
+ insn |= (((ha_val & 0xf800) << 5) | (ha_val&0x7ff));
+ bfd_put_32 (input_bfd, insn, contents + insn_offset);
+ insn_offset += 4;
+ }
+ else
+ {
+ insn = *stub++;
+ insn |= ((relocation + 0x8000) >> 16) & 0xffff;
+ bfd_put_32 (input_bfd, insn, contents + insn_offset);
+ insn_offset += 4;
+ }
insn = *stub++;
insn |= relocation & 0xffff;
@@ -9482,6 +9646,10 @@
}
goto copy_reloc;
+ case R_PPC_VLE_ADDR20:
+ ppc_elf_vle_split20 (output_bfd, contents + rel->r_offset, relocation);
+ continue;
+
/* Relocate against the beginning of the section. */
case R_PPC_SECTOFF:
case R_PPC_SECTOFF_LO:
@@ -9759,8 +9927,15 @@
&& (strcmp (input_section->output_section->name, ".init") == 0
|| strcmp (input_section->output_section->name, ".fini") == 0))
{
+ unsigned int insn;
+
+ if ((elf_section_flags (input_section) & SHF_PPC_VLE) == 0)
+ insn = B;
+ else
+ insn = E_B;
+
/* Branch around the trampolines. */
- unsigned int insn = B + input_section->size - input_section->rawsize;
+ insn += input_section->size - input_section->rawsize;
bfd_put_32 (input_bfd, insn, contents + input_section->rawsize);
}
@@ -10949,6 +11124,7 @@
#define elf_backend_action_discarded ppc_elf_action_discarded
#define elf_backend_init_index_section _bfd_elf_init_1_index_section
#define elf_backend_lookup_section_flags_hook ppc_elf_lookup_section_flags
+#define elf_backend_section_flags ppc_elf_section_flags
#include "elf32-target.h"
diff -ruN binutils-2.28/binutils/objdump.c binutils-2.28-vle/binutils/objdump.c
--- binutils-2.28/binutils/objdump.c 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/binutils/objdump.c 2017-06-23 17:25:21.641299056 +0300
@@ -481,6 +481,10 @@
PF (SEC_NEVER_LOAD, "NEVER_LOAD");
PF (SEC_EXCLUDE, "EXCLUDE");
PF (SEC_SORT_ENTRIES, "SORT_ENTRIES");
+ if (bfd_get_arch(abfd) == bfd_arch_powerpc || bfd_get_arch (abfd) == bfd_mach_ppc_vle)
+ {
+ PF (SEC_TIC54X_BLOCK, "VLE"); /* hack, would have to include ppc.h */
+ }
if (bfd_get_arch (abfd) == bfd_arch_tic54x)
{
PF (SEC_TIC54X_BLOCK, "BLOCK");
diff -ruN binutils-2.28/binutils/readelf.c binutils-2.28-vle/binutils/readelf.c
--- binutils-2.28/binutils/readelf.c 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/binutils/readelf.c 2017-06-23 21:51:24.753324000 +0300
@@ -5491,7 +5491,9 @@
/* ARM specific. */
/* 21 */ { STRING_COMMA_LEN ("ENTRYSECT") },
/* 22 */ { STRING_COMMA_LEN ("ARM_PURECODE") },
- /* 23 */ { STRING_COMMA_LEN ("COMDEF") }
+ /* 23 */ { STRING_COMMA_LEN ("COMDEF") },
+ /* VLE specific. */
+ /* 24 */ { STRING_COMMA_LEN ("VLE") }
};
if (do_section_details)
@@ -5524,6 +5526,7 @@
case SHF_TLS: sindex = 9; break;
case SHF_EXCLUDE: sindex = 18; break;
case SHF_COMPRESSED: sindex = 20; break;
+ case SHF_PPC_VLE: sindex = 24; break;
default:
sindex = -1;
@@ -5617,6 +5620,7 @@
case SHF_TLS: *p = 'T'; break;
case SHF_EXCLUDE: *p = 'E'; break;
case SHF_COMPRESSED: *p = 'C'; break;
+ case SHF_PPC_VLE: *p = 'V'; break;
default:
if ((elf_header.e_machine == EM_X86_64
@@ -6333,6 +6337,8 @@
printf (_("l (large), "));
else if (elf_header.e_machine == EM_ARM)
printf (_("y (purecode), "));
+ else if (elf_header.e_machine == EM_PPC)
+ printf (_("V (VLE), "));
printf ("p (processor specific)\n");
}
diff -ruN binutils-2.28/gas/config/obj-elf.c binutils-2.28-vle/gas/config/obj-elf.c
--- binutils-2.28/gas/config/obj-elf.c 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/gas/config/obj-elf.c 2017-06-23 17:26:08.784859055 +0300
@@ -677,6 +677,11 @@
/* RX init/fini arrays can and should have the "awx" attributes set. */
;
#endif
+#ifdef TC_PPC
+ /* A section on powerpc-vle may have SHF_PPC_VLE. */
+ else if ((attr & ~ssect->attr) == SHF_PPC_VLE)
+ override = TRUE;
+#endif
else
{
if (group_name == NULL)
diff -ruN binutils-2.28/gas/config/tc-ppc.c binutils-2.28-vle/gas/config/tc-ppc.c
--- binutils-2.28/gas/config/tc-ppc.c 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/gas/config/tc-ppc.c 2017-06-23 17:48:51.463401055 +0300
@@ -1153,6 +1153,16 @@
}
}
+ else if (strcmp (arg, "no-vle") == 0)
+ {
+ sticky &= ~PPC_OPCODE_VLE;
+
+ new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke");
+ new_cpu &= ~PPC_OPCODE_VLE;
+
+ ppc_cpu = new_cpu;
+ }
+
else if (strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
@@ -3562,13 +3572,26 @@
}
int
-ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
+ppc_section_flags (flagword flags, bfd_vma attr, int type)
{
if (type == SHT_ORDERED)
flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
+ if (attr == SHF_PPC_VLE)
+ flags |= SEC_PPC_VLE;
+
return flags;
}
+
+bfd_vma
+ppc_elf_section_letter (int letter, const char **ptrmsg)
+{
+ if (letter == 'v')
+ return SHF_PPC_VLE;
+
+ *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
+ return -1;
+}
#endif /* OBJ_ELF */
\f
diff -ruN binutils-2.28/gas/config/tc-ppc.h binutils-2.28-vle/gas/config/tc-ppc.h
--- binutils-2.28/gas/config/tc-ppc.h 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/gas/config/tc-ppc.h 2017-06-23 17:28:07.396135056 +0300
@@ -226,6 +226,9 @@
#define tc_comment_chars ppc_comment_chars
extern const char *ppc_comment_chars;
+#define md_elf_section_letter ppc_elf_section_letter
+extern bfd_vma ppc_elf_section_letter (int, const char **);
+
/* Keep relocations relative to the GOT, or non-PC relative. */
#define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
extern int ppc_fix_adjustable (struct fix *);
diff -ruN binutils-2.28/gas/doc/as.texinfo binutils-2.28-vle/gas/doc/as.texinfo
--- binutils-2.28/gas/doc/as.texinfo 2017-03-02 11:23:53.000000000 +0300
+++ binutils-2.28-vle/gas/doc/as.texinfo 2017-06-23 17:29:31.519652342 +0300
@@ -6495,6 +6495,8 @@
section is allocatable
@item e
section is excluded from executable and shared library.
+@item v
+section contains PowerPC VLE code (sets the SHF_PPC_VLE flag bit)
@item w
section is writable
@item x
diff -ruN binutils-2.28/include/elf/ppc.h binutils-2.28-vle/include/elf/ppc.h
--- binutils-2.28/include/elf/ppc.h 2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28-vle/include/elf/ppc.h 2017-06-23 17:34:20.838930833 +0300
@@ -79,8 +79,10 @@
RELOC_NUMBER (R_PPC_RELAX, 48)
RELOC_NUMBER (R_PPC_RELAX_PLT, 49)
RELOC_NUMBER (R_PPC_RELAX_PLTREL24, 50)
+ RELOC_NUMBER (R_PPC_VLE_RELAX, 51)
/* Reloc only used internally by gas. As above, value is unimportant. */
- RELOC_NUMBER (R_PPC_16DX_HA, 51)
+ RELOC_NUMBER (R_PPC_16DX_HA, 52)
+ RELOC_NUMBER (R_PPC_VLE_PLTREL24, 53)
#endif
/* Relocs added to support TLS. */
@@ -152,6 +154,7 @@
RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D, 230)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
+ RELOC_NUMBER (R_PPC_VLE_ADDR20, 233)
/* Power9 split rel16 for addpcis. */
RELOC_NUMBER (R_PPC_REL16DX_HA, 246)
@@ -198,6 +201,9 @@
/* Processor specific section headers, sh_flags field. */
#define SHF_PPC_VLE 0x10000000 /* PowerPC VLE text section. */
+/* BFD section headers flag. */
+#define SEC_PPC_VLE SEC_TIC54X_BLOCK
+
/* Processor specific section headers, sh_type field. */
#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \
diff -ruN binutils-2.28/opcodes/ppc-dis.c binutils-2.28-vle/opcodes/ppc-dis.c
--- binutils-2.28/opcodes/ppc-dis.c 2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28-vle/opcodes/ppc-dis.c 2017-06-23 17:16:54.219715056 +0300
@@ -108,8 +108,8 @@
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
- PPC_OPCODE_VLE },
+ | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4 | PPC_OPCODE_VLE),
+ 0 },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
@@ -235,12 +235,13 @@
dialect = POWERPC_DIALECT (info);
/* Disassemble according to the section headers flags for VLE-mode. */
- if (dialect & PPC_OPCODE_VLE
- && info->section != NULL && info->section->owner != NULL
+ if (dialect & PPC_OPCODE_VLE)
+ return dialect;
+ else if (info->section != NULL && info->section->owner != NULL
&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
- return dialect;
+ return PPC_OPCODE_VLE;
else
return dialect & ~ PPC_OPCODE_VLE;
}
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2016-07-26 23:26 ` Alan Modra
@ 2016-08-01 16:43 ` Andrew Jenner
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Jenner @ 2016-08-01 16:43 UTC (permalink / raw)
To: Alan Modra; +Cc: binutils, Kwok Cheung Yeung
On 27/07/2016 00:26, Alan Modra wrote:
> You missed an include/ChangeLog entry, and that last line of
> opcodes/ChangeLog is a little terse. Please expand it a little.
> I'd say minimal requirement is:
> (powerpc_opcodes): Add E200Z4 insns.
> (vle_opcodes): Add context save/restore insns.
>
> OK with that fixed.
Committed and pushed with those changes. Thanks!
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] PowerPC VLE changes
2016-07-26 16:41 Andrew Jenner
@ 2016-07-26 23:26 ` Alan Modra
2016-08-01 16:43 ` Andrew Jenner
0 siblings, 1 reply; 20+ messages in thread
From: Alan Modra @ 2016-07-26 23:26 UTC (permalink / raw)
To: Andrew Jenner; +Cc: binutils, Kwok Cheung Yeung
On Tue, Jul 26, 2016 at 05:42:01PM +0100, Andrew Jenner wrote:
> bfd/ChangeLog:
>
> * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
> (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
> (ppc_elf_vle_split16): Clear field before inserting.
>
> opcodes/ChangeLog:
>
> * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
> 'e_cmplwi' to 'e_cmpli' instead.
> (OPVUPRT, OPVUPRT_MASK): Define.
> (powerpc_opcodes, vle_opcodes): Add entries.
You missed an include/ChangeLog entry, and that last line of
opcodes/ChangeLog is a little terse. Please expand it a little.
I'd say minimal requirement is:
(powerpc_opcodes): Add E200Z4 insns.
(vle_opcodes): Add context save/restore insns.
OK with that fixed.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] PowerPC VLE changes
@ 2016-07-26 16:41 Andrew Jenner
2016-07-26 23:26 ` Alan Modra
0 siblings, 1 reply; 20+ messages in thread
From: Andrew Jenner @ 2016-07-26 16:41 UTC (permalink / raw)
To: binutils, Kwok Cheung Yeung
[-- Attachment #1: Type: text/plain, Size: 880 bytes --]
I'm in the process of preparing patches to add PowerPC VLE support to
GCC. This patch is a prerequisite for that, fixing some BFD issues and
adding some instructions:
* Volatile Context Save/Restore APU instructions as documented in
http://www.nxp.com/files/32bit/doc/ref_manual/e200z3RM.pdf .
* E200z4 decorated load and store instructions as documented in
http://www.nxp.com/files/32bit/doc/ref_manual/MPC5748GRM.pdf .
Okay to commit?
Thanks,
Andrew
---
bfd/ChangeLog:
* elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
(ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
(ppc_elf_vle_split16): Clear field before inserting.
opcodes/ChangeLog:
* ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
'e_cmplwi' to 'e_cmpli' instead.
(OPVUPRT, OPVUPRT_MASK): Define.
(powerpc_opcodes, vle_opcodes): Add entries.
[-- Attachment #2: binutils_vle.patch --]
[-- Type: text/x-patch, Size: 8003 bytes --]
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 81b3d84..8d5131a 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -1425,7 +1425,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
"R_PPC_VLE_REL15", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0xfe, /* dst_mask */
+ 0xfffe, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 24 bit branch. */
@@ -3948,7 +3948,8 @@ is_branch_reloc (enum elf_ppc_reloc_type r_type)
|| r_type == R_PPC_ADDR24
|| r_type == R_PPC_ADDR14
|| r_type == R_PPC_ADDR14_BRTAKEN
- || r_type == R_PPC_ADDR14_BRNTAKEN);
+ || r_type == R_PPC_ADDR14_BRNTAKEN
+ || r_type == R_PPC_VLE_REL24);
}
static void
@@ -4899,6 +4900,7 @@ ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *loc,
insn = bfd_get_32 (output_bfd, loc);
top5 = value & 0xf800;
top5 = top5 << (split16_format == split16a_type ? 9 : 5);
+ insn &= (split16_format == split16a_type ? ~0x1f007ff : ~0x1f07ff);
insn |= top5;
insn |= value & 0x7ff;
bfd_put_32 (output_bfd, insn, loc);
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 628a7a1..d9f973d 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -214,6 +214,9 @@ extern const int vle_num_opcodes;
/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
#define PPC_OPCODE_VSX3 0x40000000000ull
+ /* Opcode is supported by e200z4. */
+#define PPC_OPCODE_E200Z4 0x80000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 77a2a60..da1301e 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -105,6 +105,11 @@ struct ppc_mopt ppc_opts[] = {
0 },
{ "com", PPC_OPCODE_COMMON,
0 },
+ { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
+ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
+ PPC_OPCODE_VLE },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 8106ab7..d4fc7c0 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2374,6 +2374,12 @@ extract_vleil (unsigned long insn,
#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
#define OPVUP_MASK OPVUP (0x3f, 0xff)
+/* The main opcode combined with an update code and the RT fields specified in
+ D form instruction. Used for VLE volatile context save/restore
+ instructions. */
+#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
+#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
+
/* An A form instruction. */
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
#define A_MASK A (0x3f, 0x1f, 1)
@@ -3055,6 +3061,7 @@ extract_vleil (unsigned long insn,
#define E6500 PPC_OPCODE_E6500
#define PPCVLE PPC_OPCODE_VLE
#define PPCHTM PPC_OPCODE_HTM
+#define E200Z4 PPC_OPCODE_E200Z4
/* The list of embedded processors that use the embedded operand ordering
for the 3 operand dcbt and dcbtst instructions. */
#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
@@ -5815,6 +5822,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
+{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
@@ -5865,6 +5873,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
+{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
@@ -5888,6 +5897,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
+{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
@@ -5938,6 +5948,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
+{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
@@ -5975,6 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
+{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
@@ -5992,6 +6004,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
+{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
@@ -7070,7 +7083,9 @@ const struct powerpc_opcode vle_opcodes[] = {
{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
+{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
+{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
@@ -7097,6 +7112,16 @@ const struct powerpc_opcode vle_opcodes[] = {
{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
+{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
@@ -7144,10 +7169,8 @@ const struct powerpc_opcode vle_opcodes[] = {
{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
-{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
-{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2017-06-24 13:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
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2017-03-24 15:32 [PATCH] PowerPC VLE changes Александр Федотов
2017-03-27 14:32 ` Andrew Jenner
2017-03-28 14:14 ` Александр Федотов
2017-03-28 23:33 ` Alan Modra
2017-03-29 19:36 ` Alexander Fedotov
2017-04-04 1:29 ` Alan Modra
2017-04-04 10:23 ` Alexander Fedotov
2017-04-04 10:33 ` Alexander Fedotov
2017-04-22 8:51 ` Alan Modra
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2017-06-23 20:52 Alexander Fedotov
2017-06-23 20:55 ` Alexander Fedotov
2017-06-23 20:56 ` Alexander Fedotov
2017-06-23 21:34 ` Alexander Fedotov
2017-06-24 13:22 ` Alan Modra
2017-06-24 13:21 ` Alan Modra
2017-06-24 13:18 ` Alan Modra
2017-06-24 13:11 ` Alan Modra
2016-07-26 16:41 Andrew Jenner
2016-07-26 23:26 ` Alan Modra
2016-08-01 16:43 ` Andrew Jenner
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