[PATCH] RISC-V: Add support for 'Zvfh' and 'Zvfhmin'

[PATCH] RISC-V: Add support for 'Zvfh' and 'Zvfhmin'

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit adds support for recently ratified vector FP16 extensions:
'Zvfh' and 'Zvfhmin'.

This is based on:
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point>
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfh-vector-extension-for-half-precision-floating-point>

Despite not having any new instructions, it will be necessary since those
extensions are already implemented in GCC.

Note that however, in this commit, following dependencies are implemented.

1.  'Zvfhmin' -> 'Zve32f'
2.  'Zvfh' -> 'Zvfhmin' (not 'Zvfh' -> 'Zve32f' as in the documentation)
3.  'Zvfh' -> 'Zfhmin'

This is because the instructions and configurations supported by the
'Zvfh' extension is a strict superset of the 'Zvfhmin' extension and
'Zvfh' -> 'Zve32f' dependency is indirectly derived from that fact.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implications
	related to 'Zvfh' and 'Zvfhmin' extensions.
	(riscv_supported_std_z_ext) Add 'Zvfh' and 'Zvfhmin' to the list.
---
 bfd/elfxx-riscv.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2ce95d90df52..ee4598729480 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1110,6 +1110,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
+  {"zvfh", "zvfhmin",	check_implicit_always},
+  {"zvfh", "zfhmin",	check_implicit_always},
+  {"zvfhmin", "zve32f",	check_implicit_always},
   {"zve64d", "d",	check_implicit_always},
   {"zve64d", "zve64f",	check_implicit_always},
   {"zve64f", "zve32f",	check_implicit_always},
@@ -1287,6 +1290,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkng",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },

base-commit: 92f46037a0f672d1480f754f76a9bfa0334d099c
-- 
2.41.0

Re: [PATCH] RISC-V: Add support for 'Zvfh' and 'Zvfhmin'

[Nelson Chu]

[-- Attachment #1: Type: text/plain, Size: 3004 bytes --]

I'm not sure about the implied rule, but that won't be problem since we can
update them whenever.  So it looks reasonable and good.

Thanks
Nelson

On Thu, Aug 3, 2023 at 2:00 PM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> This commit adds support for recently ratified vector FP16 extensions:
> 'Zvfh' and 'Zvfhmin'.
>
> This is based on:
> <
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
> >
> <
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfh-vector-extension-for-half-precision-floating-point
> >
>
> Despite not having any new instructions, it will be necessary since those
> extensions are already implemented in GCC.
>
> Note that however, in this commit, following dependencies are implemented.
>
> 1.  'Zvfhmin' -> 'Zve32f'
> 2.  'Zvfh' -> 'Zvfhmin' (not 'Zvfh' -> 'Zve32f' as in the documentation)
> 3.  'Zvfh' -> 'Zfhmin'
>
> This is because the instructions and configurations supported by the
> 'Zvfh' extension is a strict superset of the 'Zvfhmin' extension and
> 'Zvfh' -> 'Zve32f' dependency is indirectly derived from that fact.
>
> bfd/ChangeLog:
>
>         * elfxx-riscv.c (riscv_implicit_subsets): Add implications
>         related to 'Zvfh' and 'Zvfhmin' extensions.
>         (riscv_supported_std_z_ext) Add 'Zvfh' and 'Zvfhmin' to the list.
> ---
>  bfd/elfxx-riscv.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 2ce95d90df52..ee4598729480 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1110,6 +1110,9 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
>    {"v", "d",           check_implicit_always},
>    {"v", "zve64d",      check_implicit_always},
>    {"v", "zvl128b",     check_implicit_always},
> +  {"zvfh", "zvfhmin",  check_implicit_always},
> +  {"zvfh", "zfhmin",   check_implicit_always},
> +  {"zvfhmin", "zve32f",        check_implicit_always},
>    {"zve64d", "d",      check_implicit_always},
>    {"zve64d", "zve64f", check_implicit_always},
>    {"zve64f", "zve32f", check_implicit_always},
> @@ -1287,6 +1290,8 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
>    {"zve64d",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> +  {"zvfh",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> +  {"zvfhmin",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkg",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkn",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkng",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>
> base-commit: 92f46037a0f672d1480f754f76a9bfa0334d099c
> --
> 2.41.0
>
>