From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>, Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: RE: [PATCH v2 3/3] x86: support AVX10.1 vector size restrictions
Date: Tue, 5 Sep 2023 08:11:17 +0000 [thread overview]
Message-ID: <SA1PR11MB59462F4F2B084028380CB7ACECE8A@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <f57c5c9e-5092-26c4-48a2-fe14402f23a5@suse.com>
> Recognize "/<number>" suffixes on both -march=+avx10.1 and the
> corresponding .arch directive, setting an upper bound on the vector size
> that insns may use. Such a restriction can be reset by setting a new base
> architecture, by using a suffix-less form, by disabling AVX10, or by
> enabling any other VEX/EVEX-based vector extension.
Currently in GCC community, they are asking for an option -m[no-]evex512
to enable/disable 512 bit register and 64 bit mask register. I will add a similar
option in binutils afterwards.
Also, they are not willing to introduce actual -mavx10.1-256/512. Therefore,
it might become a little problematic to introduce them in binutils only.
But since there will be finally -mavx10.2-256/512, the current code change
for attribute is always ok.
Thx,
Haochen
next prev parent reply other threads:[~2023-09-05 8:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-05 7:49 [PATCH v2 0/3] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-09-05 7:51 ` [PATCH v2 1/3] x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQ Jan Beulich
2023-09-05 7:52 ` [PATCH v2 2/3] x86: support AVX10.1/512 Jan Beulich
2023-09-05 8:00 ` Jiang, Haochen
2023-09-05 8:04 ` Jan Beulich
2023-09-05 8:13 ` Jiang, Haochen
2023-09-05 7:53 ` [PATCH v2 3/3] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-09-05 8:11 ` Jiang, Haochen [this message]
2023-09-05 8:40 ` Jan Beulich
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