* [PATCH v2 0/4] x86/APX: misc adjustments
@ 2024-02-23 11:10 Jan Beulich
2024-02-23 11:11 ` [PATCH v2 1/4] x86/APX: respect {vex}/{vex3} Jan Beulich
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Jan Beulich @ 2024-02-23 11:10 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu, Lili Cui
In part doing what was originally asked for during review.
1: respect {vex}/{vex3}
2: correct .insn opcode space determination when REX2 is needed
3: optimize certain XOR and SUB forms
4: honor -mevexwig= for byte-size insns
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] x86/APX: respect {vex}/{vex3}
2024-02-23 11:10 [PATCH v2 0/4] x86/APX: misc adjustments Jan Beulich
@ 2024-02-23 11:11 ` Jan Beulich
2024-02-23 11:12 ` [PATCH v2 2/4] x86/APX: correct .insn opcode space determination when REX2 is needed Jan Beulich
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2024-02-23 11:11 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu, Lili Cui
Even when an EVEX encoding is available, use of such a prefix ought to
be respected (resulting in an error) rather than ignored. As requested
during review already, introduce a new encoding enumerator to record use
of eGPR-s, and update state transitions accordingly.
The optimize_encoding() change also addresses an internal assembler
error that was previously raised when respective memory operands used
eGPR-s for addressing.
While this results in a change of diagnostic issued for VEX-encoded
insns, the new one is at least no worse than the prior one.
---
Question is whether for the state transitions we want to introduce a
couple of helper functions: check_register() has duplicates each of
what RC_SAE_specifier() and check_VecOperations() also do.
---
v2: Add comments in testcase.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -439,9 +439,6 @@ struct _i386_insn
/* Prefer the REX2 prefix in encoding. */
bool rex2_encoding;
- /* Need to use an Egpr capable encoding (REX2 or EVEX). */
- bool has_egpr;
-
/* Disable instruction size optimization. */
bool no_optimize;
@@ -451,6 +448,7 @@ struct _i386_insn
encoding_default = 0,
encoding_vex,
encoding_vex3,
+ encoding_egpr, /* REX2 or EVEX. */
encoding_evex,
encoding_evex512,
encoding_error
@@ -1887,7 +1885,7 @@ static INLINE bool need_evex_encoding (c
{
return i.encoding == encoding_evex
|| i.encoding == encoding_evex512
- || (t->opcode_modifier.vex && i.has_egpr)
+ || (t->opcode_modifier.vex && i.encoding == encoding_egpr)
|| i.mask.reg;
}
@@ -2489,7 +2487,8 @@ static INLINE int
fits_in_imm4 (offsetT num)
{
/* Despite the name, check for imm3 if we're dealing with EVEX. */
- return (num & (i.encoding != encoding_evex ? 0xf : 7)) == num;
+ return (num & (i.encoding != encoding_evex
+ && i.encoding != encoding_egpr ? 0xf : 7)) == num;
}
static i386_operand_type
@@ -4837,6 +4836,7 @@ optimize_encoding (void)
}
}
else if (i.encoding != encoding_evex
+ && i.encoding != encoding_egpr
&& !i.types[0].bitfield.zmmword
&& !i.types[1].bitfield.zmmword
&& !i.mask.reg
@@ -6839,10 +6839,13 @@ md_assemble (char *line)
if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
optimize_encoding ();
- /* Past optimization there's no need to distinguish encoding_evex and
- encoding_evex512 anymore. */
+ /* Past optimization there's no need to distinguish encoding_evex,
+ encoding_evex512, and encoding_egpr anymore. */
if (i.encoding == encoding_evex512)
i.encoding = encoding_evex;
+ else if (i.encoding == encoding_egpr)
+ i.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex
+ : encoding_default;
if (use_unaligned_vector_move)
encode_with_unaligned_vector_move ();
@@ -8277,27 +8280,42 @@ VEX_check_encoding (const insn_template
return 1;
}
- if (i.encoding == encoding_evex
- || i.encoding == encoding_evex512)
+ switch (i.encoding)
{
+ case encoding_default:
+ break;
+
+ case encoding_vex:
+ case encoding_vex3:
+ /* This instruction must be encoded with VEX prefix. */
+ if (!t->opcode_modifier.vex)
+ {
+ i.error = no_vex_encoding;
+ return 1;
+ }
+ break;
+
+ case encoding_evex:
+ case encoding_evex512:
/* This instruction must be encoded with EVEX prefix. */
if (!t->opcode_modifier.evex)
{
i.error = no_evex_encoding;
return 1;
}
- return 0;
- }
+ break;
- if (!t->opcode_modifier.vex)
- {
- /* This instruction template doesn't have VEX prefix. */
- if (i.encoding != encoding_default)
+ case encoding_egpr:
+ /* This instruction must be encoded with REX2 or EVEX prefix. */
+ if (t->opcode_modifier.vex && !t->opcode_modifier.evex)
{
- i.error = no_vex_encoding;
+ i.error = no_evex_encoding;
return 1;
}
- return 0;
+ break;
+
+ default:
+ abort ();
}
return 0;
@@ -12896,6 +12914,19 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
if (i.encoding == encoding_evex512)
i.encoding = encoding_evex;
+ if (i.encoding == encoding_egpr)
+ {
+ if (vex || xop)
+ {
+ as_bad (_("eGPR use conflicts with encoding specifier"));
+ goto done;
+ }
+ if (evex)
+ i.encoding = encoding_evex;
+ else
+ i.encoding = encoding_default;
+ }
+
/* Are we to emit ModR/M encoding? */
if (!i.short_form
&& (i.mem_operands
@@ -13340,11 +13371,18 @@ RC_SAE_specifier (const char *pstr)
return NULL;
}
- if (i.encoding == encoding_default)
- i.encoding = encoding_evex512;
- else if (i.encoding != encoding_evex
- && i.encoding != encoding_evex512)
- return NULL;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ case encoding_egpr:
+ i.encoding = encoding_evex512;
+ break;
+ case encoding_evex:
+ case encoding_evex512:
+ break;
+ default:
+ return NULL;
+ }
i.rounding.type = RC_NamesTable[j].type;
@@ -13405,11 +13443,18 @@ check_VecOperations (char *op_string)
}
op_string++;
- if (i.encoding == encoding_default)
- i.encoding = encoding_evex;
- else if (i.encoding != encoding_evex
- && i.encoding != encoding_evex512)
- goto unknown_vec_op;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ case encoding_egpr:
+ i.encoding = encoding_evex;
+ break;
+ case encoding_evex:
+ case encoding_evex512:
+ break;
+ default:
+ goto unknown_vec_op;
+ }
i.broadcast.type = bcst_type;
i.broadcast.operand = this_operand;
@@ -15676,11 +15721,19 @@ static bool check_register (const reg_en
if (vector_size < VSZ512)
return false;
- if (i.encoding == encoding_default)
- i.encoding = encoding_evex512;
- else if (i.encoding != encoding_evex
- && i.encoding != encoding_evex512)
- i.encoding = encoding_error;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ case encoding_egpr:
+ i.encoding = encoding_evex512;
+ break;
+ case encoding_evex:
+ case encoding_evex512:
+ break;
+ default:
+ i.encoding = encoding_error;
+ break;
+ }
}
if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword)
@@ -15706,11 +15759,19 @@ static bool check_register (const reg_en
|| flag_code != CODE_64BIT)
return false;
- if (i.encoding == encoding_default
- || i.encoding == encoding_evex512)
- i.encoding = encoding_evex;
- else if (i.encoding != encoding_evex)
- i.encoding = encoding_error;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ case encoding_egpr:
+ case encoding_evex512:
+ i.encoding = encoding_evex;
+ break;
+ case encoding_evex:
+ break;
+ default:
+ i.encoding = encoding_error;
+ break;
+ }
}
if (r->reg_flags & RegRex2)
@@ -15719,7 +15780,19 @@ static bool check_register (const reg_en
|| flag_code != CODE_64BIT)
return false;
- i.has_egpr = true;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ i.encoding = encoding_egpr;
+ break;
+ case encoding_egpr:
+ case encoding_evex:
+ case encoding_evex512:
+ break;
+ default:
+ i.encoding = encoding_error;
+ break;
+ }
}
if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -209,11 +209,18 @@ operatorT i386_operator (const char *nam
|| i386_types[j].sz[0] > 8
|| (i386_types[j].sz[0] & (i386_types[j].sz[0] - 1)))
return O_illegal;
- if (i.encoding == encoding_default)
- i.encoding = encoding_evex;
- else if (i.encoding != encoding_evex
- && i.encoding != encoding_evex512)
- return O_illegal;
+ switch (i.encoding)
+ {
+ case encoding_default:
+ case encoding_egpr:
+ i.encoding = encoding_evex;
+ break;
+ case encoding_evex:
+ case encoding_evex512:
+ break;
+ default:
+ return O_illegal;
+ }
if (!i.broadcast.bytes && !i.broadcast.type)
{
i.broadcast.bytes = i386_types[j].sz[0];
--- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l
@@ -101,102 +101,109 @@
.*:108: Error: extended GPR cannot be used as base/index for `gf2p8affineinvqb'
.*:109: Error: extended GPR cannot be used as base/index for `gf2p8affineqb'
.*:110: Error: extended GPR cannot be used as base/index for `gf2p8mulb'
-.*:112: Error: extended GPR cannot be used as base/index for `vaesimc'
-.*:113: Error: extended GPR cannot be used as base/index for `vaeskeygenassist'
-.*:114: Error: extended GPR cannot be used as base/index for `vblendpd'
-.*:115: Error: extended GPR cannot be used as base/index for `vblendpd'
-.*:116: Error: extended GPR cannot be used as base/index for `vblendps'
-.*:117: Error: extended GPR cannot be used as base/index for `vblendps'
-.*:118: Error: extended GPR cannot be used as base/index for `vblendvpd'
-.*:119: Error: extended GPR cannot be used as base/index for `vblendvpd'
-.*:120: Error: extended GPR cannot be used as base/index for `vblendvps'
-.*:121: Error: extended GPR cannot be used as base/index for `vblendvps'
-.*:122: Error: extended GPR cannot be used as base/index for `vdppd'
-.*:123: Error: extended GPR cannot be used as base/index for `vdpps'
-.*:124: Error: extended GPR cannot be used as base/index for `vdpps'
-.*:125: Error: extended GPR cannot be used as base/index for `vhaddpd'
-.*:126: Error: extended GPR cannot be used as base/index for `vhaddpd'
-.*:127: Error: extended GPR cannot be used as base/index for `vhsubps'
-.*:128: Error: extended GPR cannot be used as base/index for `vhsubps'
-.*:129: Error: extended GPR cannot be used as base/index for `vlddqu'
-.*:130: Error: extended GPR cannot be used as base/index for `vlddqu'
-.*:131: Error: extended GPR cannot be used as base/index for `vldmxcsr'
-.*:132: Error: extended GPR cannot be used as base/index for `vmaskmovpd'
-.*:133: Error: extended GPR cannot be used as base/index for `vmaskmovpd'
-.*:134: Error: extended GPR cannot be used as base/index for `vmaskmovpd'
-.*:135: Error: extended GPR cannot be used as base/index for `vmaskmovpd'
-.*:136: Error: extended GPR cannot be used as base/index for `vmaskmovps'
-.*:137: Error: extended GPR cannot be used as base/index for `vmaskmovps'
-.*:138: Error: extended GPR cannot be used as base/index for `vmaskmovps'
-.*:139: Error: extended GPR cannot be used as base/index for `vmaskmovps'
-.*:140: Error: register type mismatch for `vmovmskpd'
-.*:141: Error: register type mismatch for `vmovmskpd'
-.*:142: Error: register type mismatch for `vmovmskps'
-.*:143: Error: register type mismatch for `vmovmskps'
-.*:144: Error: extended GPR cannot be used as base/index for `vpblendd'
-.*:145: Error: extended GPR cannot be used as base/index for `vpblendd'
-.*:146: Error: extended GPR cannot be used as base/index for `vpblendvb'
-.*:147: Error: extended GPR cannot be used as base/index for `vpblendvb'
-.*:148: Error: extended GPR cannot be used as base/index for `vpblendw'
-.*:149: Error: extended GPR cannot be used as base/index for `vpblendw'
-.*:150: Error: extended GPR cannot be used as base/index for `vpcmpeqb'
-.*:151: Error: extended GPR cannot be used as base/index for `vpcmpeqd'
-.*:152: Error: extended GPR cannot be used as base/index for `vpcmpeqq'
-.*:153: Error: extended GPR cannot be used as base/index for `vpcmpeqw'
-.*:154: Error: extended GPR cannot be used as base/index for `vpcmpestri'
-.*:155: Error: extended GPR cannot be used as base/index for `vpcmpestrm'
-.*:156: Error: extended GPR cannot be used as base/index for `vpcmpgtb'
-.*:157: Error: extended GPR cannot be used as base/index for `vpcmpgtd'
-.*:158: Error: extended GPR cannot be used as base/index for `vpcmpgtq'
-.*:159: Error: extended GPR cannot be used as base/index for `vpcmpgtw'
-.*:160: Error: extended GPR cannot be used as base/index for `vpcmpistri'
-.*:161: Error: extended GPR cannot be used as base/index for `vpcmpistrm'
-.*:162: Error: extended GPR cannot be used as base/index for `vperm2f128'
-.*:163: Error: extended GPR cannot be used as base/index for `vperm2i128'
-.*:164: Error: extended GPR cannot be used as base/index for `vphaddd'
-.*:165: Error: extended GPR cannot be used as base/index for `vphaddd'
-.*:166: Error: extended GPR cannot be used as base/index for `vphaddsw'
-.*:167: Error: extended GPR cannot be used as base/index for `vphaddsw'
-.*:168: Error: extended GPR cannot be used as base/index for `vphaddw'
-.*:169: Error: extended GPR cannot be used as base/index for `vphaddw'
-.*:170: Error: extended GPR cannot be used as base/index for `vphminposuw'
-.*:171: Error: extended GPR cannot be used as base/index for `vphsubd'
-.*:172: Error: extended GPR cannot be used as base/index for `vphsubd'
-.*:173: Error: extended GPR cannot be used as base/index for `vphsubsw'
-.*:174: Error: extended GPR cannot be used as base/index for `vphsubsw'
-.*:175: Error: extended GPR cannot be used as base/index for `vphsubw'
-.*:176: Error: extended GPR cannot be used as base/index for `vphsubw'
-.*:177: Error: extended GPR cannot be used as base/index for `vpmaskmovd'
-.*:178: Error: extended GPR cannot be used as base/index for `vpmaskmovd'
-.*:179: Error: extended GPR cannot be used as base/index for `vpmaskmovd'
-.*:180: Error: extended GPR cannot be used as base/index for `vpmaskmovd'
-.*:181: Error: extended GPR cannot be used as base/index for `vpmaskmovq'
-.*:182: Error: extended GPR cannot be used as base/index for `vpmaskmovq'
-.*:183: Error: extended GPR cannot be used as base/index for `vpmaskmovq'
-.*:184: Error: extended GPR cannot be used as base/index for `vpmaskmovq'
-.*:185: Error: register type mismatch for `vpmovmskb'
-.*:186: Error: register type mismatch for `vpmovmskb'
-.*:187: Error: extended GPR cannot be used as base/index for `vpsignb'
-.*:188: Error: extended GPR cannot be used as base/index for `vpsignb'
-.*:189: Error: extended GPR cannot be used as base/index for `vpsignd'
-.*:190: Error: extended GPR cannot be used as base/index for `vpsignd'
-.*:191: Error: extended GPR cannot be used as base/index for `vpsignw'
-.*:192: Error: extended GPR cannot be used as base/index for `vpsignw'
-.*:193: Error: extended GPR cannot be used as base/index for `vptest'
-.*:194: Error: extended GPR cannot be used as base/index for `vptest'
-.*:195: Error: extended GPR cannot be used as base/index for `vrcpps'
-.*:196: Error: extended GPR cannot be used as base/index for `vrcpps'
-.*:197: Error: extended GPR cannot be used as base/index for `vrcpss'
+.*:112: Error: no EVEX encoding for `vaesimc'
+.*:113: Error: no EVEX encoding for `vaeskeygenassist'
+.*:114: Error: no EVEX encoding for `vblendpd'
+.*:115: Error: no EVEX encoding for `vblendpd'
+.*:116: Error: no EVEX encoding for `vblendps'
+.*:117: Error: no EVEX encoding for `vblendps'
+.*:118: Error: no EVEX encoding for `vblendvpd'
+.*:119: Error: no EVEX encoding for `vblendvpd'
+.*:120: Error: no EVEX encoding for `vblendvps'
+.*:121: Error: no EVEX encoding for `vblendvps'
+.*:122: Error: no EVEX encoding for `vdppd'
+.*:123: Error: no EVEX encoding for `vdpps'
+.*:124: Error: no EVEX encoding for `vdpps'
+.*:125: Error: no EVEX encoding for `vhaddpd'
+.*:126: Error: no EVEX encoding for `vhaddpd'
+.*:127: Error: no EVEX encoding for `vhsubps'
+.*:128: Error: no EVEX encoding for `vhsubps'
+.*:129: Error: no EVEX encoding for `vlddqu'
+.*:130: Error: no EVEX encoding for `vlddqu'
+.*:131: Error: no EVEX encoding for `vldmxcsr'
+.*:132: Error: no EVEX encoding for `vmaskmovpd'
+.*:133: Error: no EVEX encoding for `vmaskmovpd'
+.*:134: Error: no EVEX encoding for `vmaskmovpd'
+.*:135: Error: no EVEX encoding for `vmaskmovpd'
+.*:136: Error: no EVEX encoding for `vmaskmovps'
+.*:137: Error: no EVEX encoding for `vmaskmovps'
+.*:138: Error: no EVEX encoding for `vmaskmovps'
+.*:139: Error: no EVEX encoding for `vmaskmovps'
+.*:140: Error: no EVEX encoding for `vmovmskpd'
+.*:141: Error: no EVEX encoding for `vmovmskpd'
+.*:142: Error: no EVEX encoding for `vmovmskps'
+.*:143: Error: no EVEX encoding for `vmovmskps'
+.*:144: Error: no EVEX encoding for `vpblendd'
+.*:145: Error: no EVEX encoding for `vpblendd'
+.*:146: Error: no EVEX encoding for `vpblendvb'
+.*:147: Error: no EVEX encoding for `vpblendvb'
+.*:148: Error: no EVEX encoding for `vpblendw'
+.*:149: Error: no EVEX encoding for `vpblendw'
+.*:150: Error: no EVEX encoding for `vpcmpeqb'
+.*:151: Error: no EVEX encoding for `vpcmpeqd'
+.*:152: Error: no EVEX encoding for `vpcmpeqq'
+.*:153: Error: no EVEX encoding for `vpcmpeqw'
+.*:154: Error: no EVEX encoding for `vpcmpestri'
+.*:155: Error: no EVEX encoding for `vpcmpestrm'
+.*:156: Error: no EVEX encoding for `vpcmpgtb'
+.*:157: Error: no EVEX encoding for `vpcmpgtd'
+.*:158: Error: no EVEX encoding for `vpcmpgtq'
+.*:159: Error: no EVEX encoding for `vpcmpgtw'
+.*:160: Error: no EVEX encoding for `vpcmpistri'
+.*:161: Error: no EVEX encoding for `vpcmpistrm'
+.*:162: Error: no EVEX encoding for `vperm2f128'
+.*:163: Error: no EVEX encoding for `vperm2i128'
+.*:164: Error: no EVEX encoding for `vphaddd'
+.*:165: Error: no EVEX encoding for `vphaddd'
+.*:166: Error: no EVEX encoding for `vphaddsw'
+.*:167: Error: no EVEX encoding for `vphaddsw'
+.*:168: Error: no EVEX encoding for `vphaddw'
+.*:169: Error: no EVEX encoding for `vphaddw'
+.*:170: Error: no EVEX encoding for `vphminposuw'
+.*:171: Error: no EVEX encoding for `vphsubd'
+.*:172: Error: no EVEX encoding for `vphsubd'
+.*:173: Error: no EVEX encoding for `vphsubsw'
+.*:174: Error: no EVEX encoding for `vphsubsw'
+.*:175: Error: no EVEX encoding for `vphsubw'
+.*:176: Error: no EVEX encoding for `vphsubw'
+.*:177: Error: no EVEX encoding for `vpmaskmovd'
+.*:178: Error: no EVEX encoding for `vpmaskmovd'
+.*:179: Error: no EVEX encoding for `vpmaskmovd'
+.*:180: Error: no EVEX encoding for `vpmaskmovd'
+.*:181: Error: no EVEX encoding for `vpmaskmovq'
+.*:182: Error: no EVEX encoding for `vpmaskmovq'
+.*:183: Error: no EVEX encoding for `vpmaskmovq'
+.*:184: Error: no EVEX encoding for `vpmaskmovq'
+.*:185: Error: no EVEX encoding for `vpmovmskb'
+.*:186: Error: no EVEX encoding for `vpmovmskb'
+.*:187: Error: no EVEX encoding for `vpsignb'
+.*:188: Error: no EVEX encoding for `vpsignb'
+.*:189: Error: no EVEX encoding for `vpsignd'
+.*:190: Error: no EVEX encoding for `vpsignd'
+.*:191: Error: no EVEX encoding for `vpsignw'
+.*:192: Error: no EVEX encoding for `vpsignw'
+.*:193: Error: no EVEX encoding for `vptest'
+.*:194: Error: no EVEX encoding for `vptest'
+.*:195: Error: no EVEX encoding for `vrcpps'
+.*:196: Error: no EVEX encoding for `vrcpps'
+.*:197: Error: no EVEX encoding for `vrcpss'
.*:198: Error: .* 4 bits for `vroundpd'
.*:199: Error: .* 4 bits for `vroundps'
.*:200: Error: .* 4 bits for `vroundsd'
.*:201: Error: .* 4 bits for `vroundss'
-.*:202: Error: extended GPR cannot be used as base/index for `vrsqrtps'
-.*:203: Error: extended GPR cannot be used as base/index for `vrsqrtps'
-.*:204: Error: extended GPR cannot be used as base/index for `vrsqrtss'
-.*:205: Error: extended GPR cannot be used as base/index for `vstmxcsr'
-.*:206: Error: extended GPR cannot be used as base/index for `vtestpd'
-.*:207: Error: extended GPR cannot be used as base/index for `vtestpd'
-.*:208: Error: extended GPR cannot be used as base/index for `vtestps'
-.*:209: Error: extended GPR cannot be used as base/index for `vtestps'
+.*:202: Error: no EVEX encoding for `vrsqrtps'
+.*:203: Error: no EVEX encoding for `vrsqrtps'
+.*:204: Error: no EVEX encoding for `vrsqrtss'
+.*:205: Error: no EVEX encoding for `vstmxcsr'
+.*:206: Error: no EVEX encoding for `vtestpd'
+.*:207: Error: no EVEX encoding for `vtestpd'
+.*:208: Error: no EVEX encoding for `vtestps'
+.*:209: Error: no EVEX encoding for `vtestps'
+.*:211: Error: no VEX/XOP encoding for `and'
+.*:212: Error: no VEX/XOP encoding for `and'
+.*:213: Error: .* `and'
+.*:214: Error: no VEX/XOP encoding for `and'
+.*:215: Error: no VEX/XOP encoding for `and'
+.*:216: Error: .* `and'
+.*:219: Error: .* `andn'
#pass
--- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s
@@ -207,3 +207,13 @@
vtestpd (%r27),%ymm6
vtestps (%r27),%xmm6
vtestps (%r27),%ymm6
+# {vex}
+ {vex} and %eax, %eax
+ {vex} and %r8, %r8
+ {vex} and %r16, %r16
+ {vex} and %eax, %eax, %eax
+ {vex} and %r8, %r8, %r8
+ {vex} and %r16, %r16, %r16
+ {vex} andn %eax, %eax, %eax # This one's valid.
+ {vex} andn %r8, %r8, %r8 # And this.
+ {vex} andn %r16, %r16, %r16
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] x86/APX: correct .insn opcode space determination when REX2 is needed
2024-02-23 11:10 [PATCH v2 0/4] x86/APX: misc adjustments Jan Beulich
2024-02-23 11:11 ` [PATCH v2 1/4] x86/APX: respect {vex}/{vex3} Jan Beulich
@ 2024-02-23 11:12 ` Jan Beulich
2024-02-23 11:12 ` [PATCH v2 3/4] x86/APX: optimize certain XOR and SUB forms Jan Beulich
2024-02-23 11:13 ` [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns Jan Beulich
3 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2024-02-23 11:12 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu, Lili Cui
In this case spaces 0f38 and 0f3a may not be put in place. To achieve
the intended effect, operand parsing (but not operand processing) needs
pulling ahead, so we know whether eGRP-s are in use.
---
v2: Add --divide for new testcase.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -12849,13 +12849,43 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
}
}
+ /* Parse operands, if any, before evaluating encoding space. */
+ if (*line == ',')
+ {
+ i.memshift = -1;
+
+ ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
+ this_operand = -1;
+ if (!ptr)
+ goto bad;
+ line = ptr;
+
+ if (!i.operands)
+ {
+ as_bad (_("expecting operand after ','; got nothing"));
+ goto done;
+ }
+
+ if (i.mem_operands > 1)
+ {
+ as_bad (_("too many memory references for `%s'"),
+ &i386_mnemonics[MN__insn]);
+ goto done;
+ }
+
+ /* No need to distinguish encoding_evex and encoding_evex512. */
+ if (i.encoding == encoding_evex512)
+ i.encoding = encoding_evex;
+ }
+
/* Trim off encoding space. */
if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
{
uint8_t byte = val >> ((--j - 1) * 8);
i.insn_opcode_space = SPACE_0F;
- switch (byte & -(j > 1))
+ switch (byte & -(j > 1 && !i.rex2_encoding
+ && (i.encoding != encoding_egpr || evex)))
{
case 0x38:
i.insn_opcode_space = SPACE_0F38;
@@ -12878,42 +12908,17 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
if (j > 2)
{
as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
- goto bad;
+ goto done;
}
i.opcode_length = j;
/* Handle operands, if any. */
- if (*line == ',')
+ if (i.operands)
{
i386_operand_type combined;
expressionS *disp_exp = NULL;
bool changed;
- i.memshift = -1;
-
- ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
- this_operand = -1;
- if (!ptr)
- goto bad;
- line = ptr;
-
- if (!i.operands)
- {
- as_bad (_("expecting operand after ','; got nothing"));
- goto done;
- }
-
- if (i.mem_operands > 1)
- {
- as_bad (_("too many memory references for `%s'"),
- &i386_mnemonics[MN__insn]);
- goto done;
- }
-
- /* No need to distinguish encoding_evex and encoding_evex512. */
- if (i.encoding == encoding_evex512)
- i.encoding = encoding_evex;
-
if (i.encoding == encoding_egpr)
{
if (vex || xop)
--- /dev/null
+++ b/gas/testsuite/gas/i386/insn-rex2.l
@@ -0,0 +1,38 @@
+[ ]*[0-9]+[ ]+\.text
+[ ]*[0-9]+[ ]+insn_rex2:
+[ ]*[0-9]+ .... D58001C0[ ]+\.insn \{rex2\} 0x0f01/0, %eax
+[ ]*[0-9]+ .... D58038C0[ ]+\.insn \{rex2\} 0x0f38/0, %eax
+[ ]*[0-9]+ .... D5803801[ ]+\.insn \{rex2\} 0x0f3801/0, %eax
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5803901[ ]+\.insn \{rex2\} 0x0f3901/0, %eax
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5803A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %eax
+[ ]*[0-9]+ +C0CC
+[ ]*[0-9]+[ ]+
+[ ]*[0-9]+ .... D58801C0[ ]+\.insn \{rex2\} 0x0f01/0, %rax
+[ ]*[0-9]+ .... D58838C0[ ]+\.insn \{rex2\} 0x0f38/0, %rax
+[ ]*[0-9]+ .... D5883801[ ]+\.insn \{rex2\} 0x0f3801/0, %rax
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5883901[ ]+\.insn \{rex2\} 0x0f3901/0, %rax
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5883A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %rax
+[ ]*[0-9]+ +C0CC
+[ ]*[0-9]+[ ]+
+[ ]*[0-9]+ .... D58901C0[ ]+\.insn \{rex2\} 0x0f01/0, %r8
+[ ]*[0-9]+ .... D58938C0[ ]+\.insn \{rex2\} 0x0f38/0, %r8
+[ ]*[0-9]+ .... D5893801[ ]+\.insn \{rex2\} 0x0f3801/0, %r8
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5893901[ ]+\.insn \{rex2\} 0x0f3901/0, %r8
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5893A01[ ]+\.insn \{rex2\} 0x0f3a01/0, \$0xCC, %r8
+[ ]*[0-9]+ +C0CC
+[ ]*[0-9]+[ ]+
+[ ]*[0-9]+ .... D59801C0[ ]+\.insn 0x0f01/0, %r16
+[ ]*[0-9]+ .... D59838C0[ ]+\.insn 0x0f38/0, %r16
+[ ]*[0-9]+ .... D5983801[ ]+\.insn 0x0f3801/0, %r16
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5983901[ ]+\.insn 0x0f3901/0, %r16
+[ ]*[0-9]+ +C0
+[ ]*[0-9]+ .... D5983A01[ ]+\.insn 0x0f3a01/0, \$0xCC, %r16
+[ ]*[0-9]+[ ]+C0CC
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/insn-rex2.s
@@ -0,0 +1,25 @@
+ .text
+insn_rex2:
+ .insn {rex2} 0x0f01/0, %eax
+ .insn {rex2} 0x0f38/0, %eax
+ .insn {rex2} 0x0f3801/0, %eax
+ .insn {rex2} 0x0f3901/0, %eax
+ .insn {rex2} 0x0f3a01/0, $0xCC, %eax
+
+ .insn {rex2} 0x0f01/0, %rax
+ .insn {rex2} 0x0f38/0, %rax
+ .insn {rex2} 0x0f3801/0, %rax
+ .insn {rex2} 0x0f3901/0, %rax
+ .insn {rex2} 0x0f3a01/0, $0xCC, %rax
+
+ .insn {rex2} 0x0f01/0, %r8
+ .insn {rex2} 0x0f38/0, %r8
+ .insn {rex2} 0x0f3801/0, %r8
+ .insn {rex2} 0x0f3901/0, %r8
+ .insn {rex2} 0x0f3a01/0, $0xCC, %r8
+
+ .insn 0x0f01/0, %r16
+ .insn 0x0f38/0, %r16
+ .insn 0x0f3801/0, %r16
+ .insn 0x0f3901/0, %r16
+ .insn 0x0f3a01/0, $0xCC, %r16
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -126,6 +126,7 @@ run_dump_test "x86-64-sysenter-mixed"
run_dump_test "x86-64-sysenter-amd"
run_list_test "x86-64-sysenter-amd" "-mamd64"
run_dump_test "insn-64"
+run_list_test "insn-rex2" "-aln --divide"
run_dump_test "noreg64"
run_list_test "noreg64"
run_dump_test "noreg64-data16"
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] x86/APX: optimize certain XOR and SUB forms
2024-02-23 11:10 [PATCH v2 0/4] x86/APX: misc adjustments Jan Beulich
2024-02-23 11:11 ` [PATCH v2 1/4] x86/APX: respect {vex}/{vex3} Jan Beulich
2024-02-23 11:12 ` [PATCH v2 2/4] x86/APX: correct .insn opcode space determination when REX2 is needed Jan Beulich
@ 2024-02-23 11:12 ` Jan Beulich
2024-02-23 11:13 ` [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns Jan Beulich
3 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2024-02-23 11:12 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu, Lili Cui
While most logic in optimize_encoding() is already covering APX by way
of the earlier NDD->REX2 conversion, there's a remaining set of cases
which wants handling separately.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4693,6 +4693,34 @@ optimize_encoding (void)
}
}
}
+ else if (i.reg_operands == 3
+ && i.op[0].regs == i.op[1].regs
+ && i.encoding != encoding_evex
+ && (i.tm.mnem_off == MN_xor
+ || i.tm.mnem_off == MN_sub))
+ {
+ /* Optimize: -O:
+ xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd
+ xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd
+ xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd
+ xorq %rN, %rN, %rM -> xorl %rMd, %rMd
+ subb %rNb, %rNb, %rMb -> subl %rMd, %rMd
+ subw %rNw, %rNw, %rMw -> subl %rMd, %rMd
+ subl %rNd, %rNd, %rMd -> subl %rMd, %rMd
+ subq %rN, %rN, %rM -> subl %rMd, %rMd
+ */
+ i.tm.opcode_space = SPACE_BASE;
+ i.tm.opcode_modifier.evex = 0;
+ i.tm.opcode_modifier.size = SIZE32;
+ i.types[0].bitfield.byte = 0;
+ i.types[0].bitfield.word = 0;
+ i.types[0].bitfield.dword = 1;
+ i.types[0].bitfield.qword = 0;
+ i.op[0].regs = i.op[2].regs;
+ i.types[1] = i.types[0];
+ i.op[1].regs = i.op[2].regs;
+ i.reg_operands = 2;
+ }
else if (optimize > 1
&& !optimize_for_space
&& i.reg_operands == 2
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.d
@@ -71,4 +71,28 @@ Disassembly of section .text:
+[a-f0-9]+: 48 0f ba f0 1f btr \$0x1f,%rax
+[a-f0-9]+: 66 0f ba e8 0f bts \$0xf,%ax
+[a-f0-9]+: 48 0f ba e8 1f bts \$0x1f,%rax
+ +[a-f0-9]+: 31 c9 xor %ecx,%ecx
+ +[a-f0-9]+: 48 31 d1 xor %rdx,%rcx
+ +[a-f0-9]+: 31 c9 xor %ecx,%ecx
+ +[a-f0-9]+: 29 c9 sub %ecx,%ecx
+ +[a-f0-9]+: 48 29 d1 sub %rdx,%rcx
+ +[a-f0-9]+: 29 c9 sub %ecx,%ecx
+ +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d
+ +[a-f0-9]+: d5 58 31 d1 xor %r18,%r17
+ +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d
+ +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d
+ +[a-f0-9]+: d5 58 29 d1 sub %r18,%r17
+ +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d
+ +[a-f0-9]+: 31 c9 xor %ecx,%ecx
+ +[a-f0-9]+: 62 f4 75 18 31 d1 xor %dx,%cx,%cx
+ +[a-f0-9]+: 31 c9 xor %ecx,%ecx
+ +[a-f0-9]+: 29 c9 sub %ecx,%ecx
+ +[a-f0-9]+: 62 f4 75 18 29 d1 sub %dx,%cx,%cx
+ +[a-f0-9]+: 29 c9 sub %ecx,%ecx
+ +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d
+ +[a-f0-9]+: 62 ec 74 10 30 d1 xor %r18b,%r17b,%r17b
+ +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d
+ +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d
+ +[a-f0-9]+: 62 ec 74 10 28 d1 sub %r18b,%r17b,%r17b
+ +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d
#pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.s
@@ -65,3 +65,27 @@ _start:
btr $31, %rax
bts $15, %ax
bts $31, %rax
+ xor %rcx, %rcx, %rcx
+ xor %rdx, %rcx, %rcx
+ xor %rdx, %rdx, %rcx
+ sub %rcx, %rcx, %rcx
+ sub %rdx, %rcx, %rcx
+ sub %rdx, %rdx, %rcx
+ xor %r17, %r17, %r17
+ xor %r18, %r17, %r17
+ xor %r18, %r18, %r17
+ sub %r17, %r17, %r17
+ sub %r18, %r17, %r17
+ sub %r18, %r18, %r17
+ xor %cx, %cx, %cx
+ xor %dx, %cx, %cx
+ xor %dx, %dx, %cx
+ sub %cx, %cx, %cx
+ sub %dx, %cx, %cx
+ sub %dx, %dx, %cx
+ xor %r17b, %r17b, %r17b
+ xor %r18b, %r17b, %r17b
+ xor %r18b, %r18b, %r17b
+ sub %r17b, %r17b, %r17b
+ sub %r18b, %r17b, %r17b
+ sub %r18b, %r18b, %r17b
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -320,7 +320,7 @@ inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf
inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
+sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
sub, 0x83/5, APX_F, Modrm|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
@@ -366,7 +366,7 @@ or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm3
or, 0x80/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
xor, 0x83/6, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns
2024-02-23 11:10 [PATCH v2 0/4] x86/APX: misc adjustments Jan Beulich
` (2 preceding siblings ...)
2024-02-23 11:12 ` [PATCH v2 3/4] x86/APX: optimize certain XOR and SUB forms Jan Beulich
@ 2024-02-23 11:13 ` Jan Beulich
2024-02-26 10:42 ` Cui, Lili
3 siblings, 1 reply; 6+ messages in thread
From: Jan Beulich @ 2024-02-23 11:13 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu, Lili Cui
These uniformly ignore EVEX.W, and hence what we emit ought to be
controllable by the command line option.
---
While doing the adjustment right after install_template() seems
desirable, there's still the question whether this might better be done
in process_operands(). This is in particular because when non-NDD EVEX
insns / forms of various insns are added (so far only ADCX and ADOX are
there, which have neither memory destinations nor byte variants), the
destination operand isn't the only one that will need considering here:
An unsized memory destination would require inspecting an earlier
operand (if any) or the suffix (which, just to mention it, must not be
taken into consideration for CRC32, but that allows for memory source
only anyway). Otoh process_operands() is also used by .insn handling,
and we may not do such an adjustment there.
---
v2: New.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -9103,6 +9103,15 @@ match_template (char mnem_suffix)
i.tm.operand_types[addr_prefix_disp]
= operand_types[addr_prefix_disp];
+ /* APX insns acting on byte operands are WIG, yet that can't be expressed
+ in the templates (they're also covering word/dword/qword operands). */
+ if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw &&
+ i.types[i.operands - 1].bitfield.byte)
+ {
+ gas_assert (t->opcode_modifier.w);
+ i.tm.opcode_modifier.vexw = VEXWIG;
+ }
+
switch (found_reverse_match)
{
case 0:
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-wig.d
@@ -0,0 +1,161 @@
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86-64 APX NDD instructions w/ EVEX prefix and -mevexwig=1
+#source: x86-64-apx-ndd.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 d0 34 12 adc \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 10 f9 adc %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 12 04 07 adc \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 13 04 07 adc \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 14 83 11 adc \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*62 54 6d 10 66 c7 adcx %r15d,%r8d,%r18d
+[ ]*[a-f0-9]+:[ ]*62 14 f9 08 66 04 3f adcx \(%r15,%r31,1\),%r8
+[ ]*[a-f0-9]+:[ ]*62 14 69 10 66 04 3f adcx \(%r15,%r31,1\),%r8d,%r18d
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 c0 34 12 add \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 d4 fc 10 81 c7 33 44 34 12 add \$0x12344433,%r15,%r16
+[ ]*[a-f0-9]+:[ ]*62 d4 f4 10 80 c5 34 add \$0x34,%r13b,%r17b
+[ ]*[a-f0-9]+:[ ]*62 f4 bc 18 81 c0 11 22 33 f4 add \$0xfffffffff4332211,%rax,%r8
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 38 add %r31,\(%r8\),%r16
+[ ]*[a-f0-9]+:[ ]*62 44 f8 10 01 3c c0 add %r31,\(%r8,%r16,8\),%r16
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 00 f8 add %r31b,%r8b,%r16b
+[ ]*[a-f0-9]+:[ ]*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
+[ ]*[a-f0-9]+:[ ]*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
+[ ]*[a-f0-9]+:[ ]*62 5c fc 10 03 07 add \(%r31\),%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 5c f8 10 03 84 07 90 90 00 00 add 0x9090\(%r31,%r16,1\),%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 00 f8 add %r31b,%r8b,%r16b
+[ ]*[a-f0-9]+:[ ]*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 04 83 11 add \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 d4 fc 10 81 04 8f 33 44 34 12 add \$0x12344433,\(%r15,%rcx,4\),%r16
+[ ]*[a-f0-9]+:[ ]*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
+[ ]*[a-f0-9]+:[ ]*62 54 6e 10 66 c7 adox %r15d,%r8d,%r18d
+[ ]*[a-f0-9]+:[ ]*62 5c fc 10 03 c7 add %r31,%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
+[ ]*[a-f0-9]+:[ ]*62 14 fa 08 66 04 3f adox \(%r15,%r31,1\),%r8
+[ ]*[a-f0-9]+:[ ]*62 14 6a 10 66 04 3f adox \(%r15,%r31,1\),%r8d,%r18d
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 e0 34 12 and \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 20 f9 and %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 22 04 07 and \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 23 04 07 and \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 24 83 11 and \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 47 90 90 90 90 90 cmova -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 43 90 90 90 90 90 cmovae -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 42 90 90 90 90 90 cmovb -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 46 90 90 90 90 90 cmovbe -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 44 90 90 90 90 90 cmove -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4d 90 90 90 90 90 cmovge -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4c 90 90 90 90 90 cmovl -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4e 90 90 90 90 90 cmovle -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 45 90 90 90 90 90 cmovne -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 41 90 90 90 90 90 cmovno -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 49 90 90 90 90 90 cmovns -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 40 90 90 90 90 90 cmovo -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 48 90 90 90 90 90 cmovs -0x6f6f6f70\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 ff c8 dec %rax,%r17
+[ ]*[a-f0-9]+:[ ]*62 9c bc 18 fe 0c 27 dec \(%r31,%r12,1\),%r8b
+[ ]*[a-f0-9]+:[ ]*62 b4 b0 10 af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx,%r25
+[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 af 90 09 09 09 00 imul 0x90909\(%eax\),%edx,%r8d
+[ ]*[a-f0-9]+:[ ]*62 dc fc 10 ff c7 inc %r31,%r16
+[ ]*[a-f0-9]+:[ ]*62 dc bc 18 ff c7 inc %r31,%r8
+[ ]*[a-f0-9]+:[ ]*62 f4 e4 18 ff c0 inc %rax,%rbx
+[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 f7 d8 neg %rax,%r17
+[ ]*[a-f0-9]+:[ ]*62 9c bc 18 f6 1c 27 neg \(%r31,%r12,1\),%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 f7 d0 not %rax,%r17
+[ ]*[a-f0-9]+:[ ]*62 9c bc 18 f6 14 27 not \(%r31,%r12,1\),%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 c8 34 12 or \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 08 f9 or %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 0a 04 07 or \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 0b 04 07 or \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 0c 83 11 or \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 d4 02 rcl \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 d0 rcl %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 10 rcl \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 10 02 rcl \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 10 rcl \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 14 83 rcl %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 dc 02 rcr \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 d8 rcr %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 18 rcr \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 18 02 rcr \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 18 rcr \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 1c 83 rcr %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 c4 02 rol \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 c0 rol %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 00 rol \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 00 02 rol \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 00 rol \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 04 83 rol %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 cc 02 ror \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 c8 ror %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 08 ror \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 08 02 ror \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 08 ror \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 0c 83 ror %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 fc 02 sar \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 f8 sar %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 38 sar \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 38 02 sar \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 38 sar \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 3c 83 sar %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 d8 34 12 sbb \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 18 f9 sbb %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 1a 04 07 sbb \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 1b 04 07 sbb \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 1c 83 11 sbb \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 e4 02 shl \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 e4 02 shl \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e0 shl %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e0 shl %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 20 shl \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 20 shl \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 74 84 10 24 20 01 shld \$0x1,%r12,\(%rax\),%r31
+[ ]*[a-f0-9]+:[ ]*62 74 04 10 24 38 02 shld \$0x2,%r15d,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 54 05 10 24 c4 02 shld \$0x2,%r8w,%r12w,%r31w
+[ ]*[a-f0-9]+:[ ]*62 7c bc 18 a5 e0 shld %cl,%r12,%r16,%r8
+[ ]*[a-f0-9]+:[ ]*62 7c 05 10 a5 2c 83 shld %cl,%r13w,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 74 05 10 a5 08 shld %cl,%r9w,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 20 02 shl \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 20 02 shl \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 20 shl \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 20 shl \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 24 83 shl %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 24 83 shl %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 ec 02 shr \$0x2,%r12b,%r31b
+[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e8 shr %cl,%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 28 shr \$1,\(%rax\),%r31b
+[ ]*[a-f0-9]+:[ ]*62 74 84 10 2c 20 01 shrd \$0x1,%r12,\(%rax\),%r31
+[ ]*[a-f0-9]+:[ ]*62 74 04 10 2c 38 02 shrd \$0x2,%r15d,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 54 05 10 2c c4 02 shrd \$0x2,%r8w,%r12w,%r31w
+[ ]*[a-f0-9]+:[ ]*62 7c bc 18 ad e0 shrd %cl,%r12,%r16,%r8
+[ ]*[a-f0-9]+:[ ]*62 7c 05 10 ad 2c 83 shrd %cl,%r13w,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 74 05 10 ad 08 shrd %cl,%r9w,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 28 02 shr \$0x2,\(%rax\),%r31d
+[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 28 shr \$1,\(%rax\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 2c 83 shr %cl,\(%r19,%rax,4\),%r31w
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 e8 34 12 sub \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 28 f9 sub %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 2a 04 07 sub \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 2b 04 07 sub \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 2c 83 11 sub \$0x11,\(%r19,%rax,4\),%r20d
+[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 f0 34 12 xor \$0x1234,%ax,%r30w
+[ ]*[a-f0-9]+:[ ]*62 7c ec 10 30 f9 xor %r15b,%r17b,%r18b
+[ ]*[a-f0-9]+:[ ]*62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d
+[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 32 04 07 xor \(%r15,%rax,1\),%r16b,%r8b
+[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 33 04 07 xor \(%r15,%rax,1\),%r16w,%r8w
+[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 34 83 11 xor \$0x11,\(%r19,%rax,4\),%r20d
+#pass
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -381,6 +381,7 @@ run_dump_test "x86-64-apx-evex-promoted-
run_dump_test "x86-64-apx-evex-promoted-wig"
run_dump_test "x86-64-apx-evex-egpr"
run_dump_test "x86-64-apx-ndd"
+run_dump_test "x86-64-apx-ndd-wig"
run_dump_test "x86-64-apx-jmpabs"
run_dump_test "x86-64-apx-jmpabs-intel"
run_dump_test "x86-64-apx-jmpabs-inval"
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns
2024-02-23 11:13 ` [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns Jan Beulich
@ 2024-02-26 10:42 ` Cui, Lili
0 siblings, 0 replies; 6+ messages in thread
From: Cui, Lili @ 2024-02-26 10:42 UTC (permalink / raw)
To: Beulich, Jan, Binutils; +Cc: H.J. Lu
> These uniformly ignore EVEX.W, and hence what we emit ought to be
> controllable by the command line option.
> ---
> While doing the adjustment right after install_template() seems desirable,
> there's still the question whether this might better be done in
> process_operands(). This is in particular because when non-NDD EVEX insns /
> forms of various insns are added (so far only ADCX and ADOX are there, which
> have neither memory destinations nor byte variants), the destination operand
> isn't the only one that will need considering here:
> An unsized memory destination would require inspecting an earlier operand (if
> any) or the suffix (which, just to mention it, must not be taken into
> consideration for CRC32, but that allows for memory source only anyway).
> Otoh process_operands() is also used by .insn handling, and we may not do
> such an adjustment there.
> ---
> v2: New.
I was just thinking about how to handle the IGNORE for the APX byte-size and then see your patch, thanks.
Lili.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -9103,6 +9103,15 @@ match_template (char mnem_suffix)
> i.tm.operand_types[addr_prefix_disp]
> = operand_types[addr_prefix_disp];
>
> + /* APX insns acting on byte operands are WIG, yet that can't be expressed
> + in the templates (they're also covering word/dword/qword
> + operands). */ if (t->opcode_space == SPACE_EVEXMAP4 && !t-
> >opcode_modifier.vexw &&
> + i.types[i.operands - 1].bitfield.byte)
> + {
> + gas_assert (t->opcode_modifier.w);
> + i.tm.opcode_modifier.vexw = VEXWIG;
> + }
> +
> switch (found_reverse_match)
> {
> case 0:
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-wig.d
> @@ -0,0 +1,161 @@
> +#as: -mevexwig=1
> +#objdump: -dw
> +#name: x86-64 APX NDD instructions w/ EVEX prefix and -mevexwig=1
> +#source: x86-64-apx-ndd.s
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 d0 34 12 adc
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 10 f9 adc %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 12 04 07 adc
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 13 04 07 adc
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 14 83 11 adc
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*62 54 6d 10 66 c7 adcx %r15d,%r8d,%r18d
> +[ ]*[a-f0-9]+:[ ]*62 14 f9 08 66 04 3f adcx \(%r15,%r31,1\),%r8
> +[ ]*[a-f0-9]+:[ ]*62 14 69 10 66 04 3f adcx
> \(%r15,%r31,1\),%r8d,%r18d
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 c0 34 12 add
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 d4 fc 10 81 c7 33 44 34 12 add
> \$0x12344433,%r15,%r16
> +[ ]*[a-f0-9]+:[ ]*62 d4 f4 10 80 c5 34 add \$0x34,%r13b,%r17b
> +[ ]*[a-f0-9]+:[ ]*62 f4 bc 18 81 c0 11 22 33 f4 add
> \$0xfffffffff4332211,%rax,%r8
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 38 add %r31,\(%r8\),%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 f8 10 01 3c c0
> add %r31,\(%r8,%r16,8\),%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 00 f8 add %r31b,%r8b,%r16b
> +[ ]*[a-f0-9]+:[ ]*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
> +[ ]*[a-f0-9]+:[ ]*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
> +[ ]*[a-f0-9]+:[ ]*62 5c fc 10 03 07 add \(%r31\),%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 5c f8 10 03 84 07 90 90 00 00 add
> 0x9090\(%r31,%r16,1\),%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 00 f8 add %r31b,%r8b,%r16b
> +[ ]*[a-f0-9]+:[ ]*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 04 83 11 add
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 d4 fc 10 81 04 8f 33 44 34 12 add
> \$0x12344433,\(%r15,%rcx,4\),%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
> +[ ]*[a-f0-9]+:[ ]*62 54 6e 10 66 c7 adox %r15d,%r8d,%r18d
> +[ ]*[a-f0-9]+:[ ]*62 5c fc 10 03 c7 add %r31,%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 44 fc 10 01 f8 add %r31,%r8,%r16
> +[ ]*[a-f0-9]+:[ ]*62 14 fa 08 66 04 3f adox \(%r15,%r31,1\),%r8
> +[ ]*[a-f0-9]+:[ ]*62 14 6a 10 66 04 3f adox
> \(%r15,%r31,1\),%r8d,%r18d
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 e0 34 12 and
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 20 f9 and %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 22 04 07 and
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 23 04 07 and
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 24 83 11 and
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 47 90 90 90 90 90 cmova -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 43 90 90 90 90 90 cmovae -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 42 90 90 90 90 90 cmovb -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 46 90 90 90 90 90 cmovbe -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 44 90 90 90 90 90 cmove -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4d 90 90 90 90 90 cmovge -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4c 90 90 90 90 90 cmovl -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4e 90 90 90 90 90 cmovle -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 45 90 90 90 90 90 cmovne -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 41 90 90 90 90 90 cmovno -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4b 90 90 90 90 90 cmovnp -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 49 90 90 90 90 90 cmovns -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 40 90 90 90 90 90 cmovo -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 4a 90 90 90 90 90 cmovp -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 48 90 90 90 90 90 cmovs -
> 0x6f6f6f70\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 ff c8 dec %rax,%r17
> +[ ]*[a-f0-9]+:[ ]*62 9c bc 18 fe 0c 27 dec \(%r31,%r12,1\),%r8b
> +[ ]*[a-f0-9]+:[ ]*62 b4 b0 10 af 94 f8 09 09 00 00 imul
> 0x909\(%rax,%r31,8\),%rdx,%r25
> +[ ]*[a-f0-9]+:[ ]*67 62 f4 3c 18 af 90 09 09 09 00 imul
> 0x90909\(%eax\),%edx,%r8d
> +[ ]*[a-f0-9]+:[ ]*62 dc fc 10 ff c7 inc %r31,%r16
> +[ ]*[a-f0-9]+:[ ]*62 dc bc 18 ff c7 inc %r31,%r8
> +[ ]*[a-f0-9]+:[ ]*62 f4 e4 18 ff c0 inc %rax,%rbx
> +[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 f7 d8 neg %rax,%r17
> +[ ]*[a-f0-9]+:[ ]*62 9c bc 18 f6 1c 27 neg \(%r31,%r12,1\),%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 f4 10 f7 d0 not %rax,%r17
> +[ ]*[a-f0-9]+:[ ]*62 9c bc 18 f6 14 27 not \(%r31,%r12,1\),%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 c8 34 12 or
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 08 f9 or %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 0a 04 07 or
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 0b 04 07 or
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 0c 83 11 or
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 d4 02 rcl
> \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 d0 rcl %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 10 rcl \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 10 02 rcl \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 10 rcl \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 14 83
> rcl %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 dc 02 rcr \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 d8 rcr %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 18 rcr \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 18 02 rcr \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 18 rcr \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 1c 83
> rcr %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 c4 02 rol \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 c0 rol %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 00 rol \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 00 02 rol \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 00 rol \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 04 83
> rol %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 cc 02 ror \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 c8 ror %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 08 ror \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 08 02 ror \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 08 ror \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 0c 83
> ror %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 fc 02 sar \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 f8 sar %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 38 sar \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 38 02 sar \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 38 sar \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 3c 83
> sar %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 d8 34 12 sbb
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 18 f9 sbb %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 1a 04 07 sbb
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 1b 04 07 sbb
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 1c 83 11 sbb
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 e4 02 shl \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 e4 02 shl \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e0 shl %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e0 shl %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 20 shl \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 20 shl \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 74 84 10 24 20 01 shld
> \$0x1,%r12,\(%rax\),%r31
> +[ ]*[a-f0-9]+:[ ]*62 74 04 10 24 38 02 shld
> \$0x2,%r15d,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 54 05 10 24 c4 02 shld
> \$0x2,%r8w,%r12w,%r31w
> +[ ]*[a-f0-9]+:[ ]*62 7c bc 18 a5 e0 shld %cl,%r12,%r16,%r8
> +[ ]*[a-f0-9]+:[ ]*62 7c 05 10 a5 2c 83
> shld %cl,%r13w,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 74 05 10 a5 08
> shld %cl,%r9w,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 20 02 shl \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 20 02 shl \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 20 shl \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 20 shl \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 24 83
> shl %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 24 83
> shl %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 d4 84 10 c0 ec 02 shr \$0x2,%r12b,%r31b
> +[ ]*[a-f0-9]+:[ ]*62 fc bc 18 d2 e8 shr %cl,%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 f4 84 10 d0 28 shr \$1,\(%rax\),%r31b
> +[ ]*[a-f0-9]+:[ ]*62 74 84 10 2c 20 01 shrd
> \$0x1,%r12,\(%rax\),%r31
> +[ ]*[a-f0-9]+:[ ]*62 74 04 10 2c 38 02 shrd
> \$0x2,%r15d,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 54 05 10 2c c4 02 shrd
> \$0x2,%r8w,%r12w,%r31w
> +[ ]*[a-f0-9]+:[ ]*62 7c bc 18 ad e0 shrd %cl,%r12,%r16,%r8
> +[ ]*[a-f0-9]+:[ ]*62 7c 05 10 ad 2c 83
> shrd %cl,%r13w,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 74 05 10 ad 08
> shrd %cl,%r9w,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 f4 04 10 c1 28 02 shr \$0x2,\(%rax\),%r31d
> +[ ]*[a-f0-9]+:[ ]*62 f4 05 10 d1 28 shr \$1,\(%rax\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 fc 05 10 d3 2c 83
> shr %cl,\(%r19,%rax,4\),%r31w
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 e8 34 12 sub
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 28 f9 sub %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 2a 04 07 sub
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 2b 04 07 sub
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 2c 83 11 sub
> \$0x11,\(%r19,%rax,4\),%r20d
> +[ ]*[a-f0-9]+:[ ]*62 f4 0d 10 81 f0 34 12 xor
> \$0x1234,%ax,%r30w
> +[ ]*[a-f0-9]+:[ ]*62 7c ec 10 30 f9 xor %r15b,%r17b,%r18b
> +[ ]*[a-f0-9]+:[ ]*62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d
> +[ ]*[a-f0-9]+:[ ]*62 c4 bc 18 32 04 07 xor
> \(%r15,%rax,1\),%r16b,%r8b
> +[ ]*[a-f0-9]+:[ ]*62 c4 3d 18 33 04 07 xor
> \(%r15,%rax,1\),%r16w,%r8w
> +[ ]*[a-f0-9]+:[ ]*62 fc 5c 10 83 34 83 11 xor
> \$0x11,\(%r19,%rax,4\),%r20d
> +#pass
> --- a/gas/testsuite/gas/i386/x86-64.exp
> +++ b/gas/testsuite/gas/i386/x86-64.exp
> @@ -381,6 +381,7 @@ run_dump_test "x86-64-apx-evex-promoted-
> run_dump_test "x86-64-apx-evex-promoted-wig"
> run_dump_test "x86-64-apx-evex-egpr"
> run_dump_test "x86-64-apx-ndd"
> +run_dump_test "x86-64-apx-ndd-wig"
> run_dump_test "x86-64-apx-jmpabs"
> run_dump_test "x86-64-apx-jmpabs-intel"
> run_dump_test "x86-64-apx-jmpabs-inval"
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-02-26 10:42 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-23 11:10 [PATCH v2 0/4] x86/APX: misc adjustments Jan Beulich
2024-02-23 11:11 ` [PATCH v2 1/4] x86/APX: respect {vex}/{vex3} Jan Beulich
2024-02-23 11:12 ` [PATCH v2 2/4] x86/APX: correct .insn opcode space determination when REX2 is needed Jan Beulich
2024-02-23 11:12 ` [PATCH v2 3/4] x86/APX: optimize certain XOR and SUB forms Jan Beulich
2024-02-23 11:13 ` [PATCH v2 4/4] x86/APX: honor -mevexwig= for byte-size insns Jan Beulich
2024-02-26 10:42 ` Cui, Lili
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