RE: [PATCH][v6] Support Intel USER_MSR

["Hu, Lin1" <lin1.hu@intel.com>]

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, November 14, 2023 3:15 PM
> To: Hu, Lin1 <lin1.hu@intel.com>; Cui, Lili <lili.cui@intel.com>
> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org
> Subject: Re: [PATCH][v6] Support Intel USER_MSR
> 
> On 31.10.2023 03:14, Hu, Lin1 wrote:
> > @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {}  eretu,
> > 0xf30f01ca, FRED|x64, NoSuf, {}
> >
> >  // FRED instructions end.
> > +
> > +// USER_MSR instructions.
> > +
> > +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64,
> > +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64,
> > +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr,
> > +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
> > +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf,
> {
> > +Reg64, Imm32 }
> 
> Actually I think the choice of Reg64 here for the operand specifying the MSR
> index is misleading, even if in line with what the doc presently says in the
> Opcode / Instruction column. For both insns the description says that only the
> low 32 bits are used (and the Exceptions section confirms this). Such operands,
> however, are expressed as Reg32 everywhere else. I'd like to suggest that the
> spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts?

Can you give some examples about such operands are expressed as Reg32.  I can go ahead and discuss it internally. May need to wait for HJ for final confirmation.

BRs,
Lin