* gcc-4.5 build fixes
@ 2023-05-16 23:54 Alan Modra
0 siblings, 0 replies; only message in thread
From: Alan Modra @ 2023-05-16 23:54 UTC (permalink / raw)
To: binutils
Trying to build binutils with an older gcc currently fails. Working
around these gcc bugs is not onerous so let's fix them.
bfd/
* elf32-csky.c (csky_elf_size_dynamic_sections): Don't type-pun
pointer.
* elf32-rl78.c (rl78_compute_complex_reloc): Rename "stat"
variable to "status".
gas/
* compress-debug.c (compress_finish): Supply all fields in
ZSTD_inBuffer initialisation.
include/
* xtensa-dynconfig.h (xtensa_isa_internal): Delete unnecessary
forward declaration.
opcodes/
* loongarch-opc.c: Supply all fields of zero struct initialisation
in various opcode tables.
diff --git a/bfd/elf32-csky.c b/bfd/elf32-csky.c
index 76567c722bb..40d776169f2 100644
--- a/bfd/elf32-csky.c
+++ b/bfd/elf32-csky.c
@@ -1942,8 +1942,7 @@ csky_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
{
struct elf_dyn_relocs *p;
- for (p = *((struct elf_dyn_relocs **)
- &elf_section_data (s)->local_dynrel);
+ for (p = elf_section_data (s)->local_dynrel;
p != NULL;
p = p->next)
{
diff --git a/bfd/elf32-rl78.c b/bfd/elf32-rl78.c
index c7a94f2a280..c8b767ea166 100644
--- a/bfd/elf32-rl78.c
+++ b/bfd/elf32-rl78.c
@@ -396,18 +396,18 @@ rl78_compute_complex_reloc (unsigned long r_type,
{
int32_t tmp1, tmp2;
bfd_vma relocation = 0;
- bfd_reloc_status_type stat = bfd_reloc_ok;
+ bfd_reloc_status_type status = bfd_reloc_ok;
switch (r_type)
{
default:
- stat = bfd_reloc_notsupported;
+ status = bfd_reloc_notsupported;
break;
case R_RL78_ABS24S_PCREL:
case R_RL78_ABS16S_PCREL:
case R_RL78_ABS8S_PCREL:
- relocation = rl78_stack_pop (&stat);
+ relocation = rl78_stack_pop (&status);
relocation -= input_section->output_section->vma + input_section->output_offset;
break;
@@ -420,141 +420,141 @@ rl78_compute_complex_reloc (unsigned long r_type,
case R_RL78_ABS8:
case R_RL78_ABS8U:
case R_RL78_ABS8S:
- relocation = rl78_stack_pop (&stat);
+ relocation = rl78_stack_pop (&status);
break;
case R_RL78_ABS16UL:
case R_RL78_ABS8UL:
- relocation = rl78_stack_pop (&stat) >> 2;
+ relocation = rl78_stack_pop (&status) >> 2;
break;;
case R_RL78_ABS16UW:
case R_RL78_ABS8UW:
- relocation = rl78_stack_pop (&stat) >> 1;
+ relocation = rl78_stack_pop (&status) >> 1;
break;
/* The rest of the relocs compute values and then push them onto the stack. */
case R_RL78_OPramtop:
case R_RL78_OPromtop:
case R_RL78_SYM:
- rl78_stack_push (symval, &stat);
+ rl78_stack_push (symval, &status);
break;
case R_RL78_OPneg:
- tmp1 = rl78_stack_pop (&stat);
+ tmp1 = rl78_stack_pop (&status);
tmp1 = - tmp1;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPadd:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 += tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPsub:
/* For the expression "A - B", the assembler pushes A,
then B, then OPSUB. So the first op we pop is B, not A. */
- tmp2 = rl78_stack_pop (&stat); /* B */
- tmp1 = rl78_stack_pop (&stat); /* A */
+ tmp2 = rl78_stack_pop (&status); /* B */
+ tmp1 = rl78_stack_pop (&status); /* A */
tmp1 -= tmp2; /* A - B */
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPmul:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 *= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPdiv:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
if (tmp2 != 0)
tmp1 /= tmp2;
else
{
tmp1 = 0;
- stat = bfd_reloc_overflow;
+ status = bfd_reloc_overflow;
}
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPshla:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 <<= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPshra:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 >>= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPsctsize:
- rl78_stack_push (input_section->size, &stat);
+ rl78_stack_push (input_section->size, &status);
break;
case R_RL78_OPscttop:
- rl78_stack_push (input_section->output_section->vma, &stat);
+ rl78_stack_push (input_section->output_section->vma, &status);
break;
case R_RL78_OPand:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 &= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPor:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 |= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPxor:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
tmp1 ^= tmp2;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPnot:
- tmp1 = rl78_stack_pop (&stat);
+ tmp1 = rl78_stack_pop (&status);
tmp1 = ~ tmp1;
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
case R_RL78_OPmod:
- tmp2 = rl78_stack_pop (&stat);
- tmp1 = rl78_stack_pop (&stat);
+ tmp2 = rl78_stack_pop (&status);
+ tmp1 = rl78_stack_pop (&status);
if (tmp2 != 0)
tmp1 %= tmp2;
else
{
tmp1 = 0;
- stat = bfd_reloc_overflow;
+ status = bfd_reloc_overflow;
}
- rl78_stack_push (tmp1, &stat);
+ rl78_stack_push (tmp1, &status);
break;
}
if (r)
{
- if (stat == bfd_reloc_dangerous)
+ if (status == bfd_reloc_dangerous)
*error_message = (_("RL78 reloc stack overflow/underflow"));
- else if (stat == bfd_reloc_overflow)
+ else if (status == bfd_reloc_overflow)
{
- stat = bfd_reloc_dangerous;
+ status = bfd_reloc_dangerous;
*error_message = (_("RL78 reloc divide by zero"));
}
- *r = stat;
+ *r = status;
}
return relocation;
}
diff --git a/gas/compress-debug.c b/gas/compress-debug.c
index 174c70e65d5..28b8b003f2e 100644
--- a/gas/compress-debug.c
+++ b/gas/compress-debug.c
@@ -100,7 +100,7 @@ compress_finish (bool use_zstd, void *ctx, char **next_out,
{
#if HAVE_ZSTD
ZSTD_outBuffer ob = { *next_out, *avail_out, 0 };
- ZSTD_inBuffer ib = { 0 };
+ ZSTD_inBuffer ib = { 0, 0, 0 };
size_t ret = ZSTD_compressStream2 (ctx, &ob, &ib, ZSTD_e_end);
*out_size = ob.pos;
*next_out += ob.pos;
diff --git a/include/xtensa-dynconfig.h b/include/xtensa-dynconfig.h
index bb72d6ab22d..b6b02186413 100644
--- a/include/xtensa-dynconfig.h
+++ b/include/xtensa-dynconfig.h
@@ -104,8 +104,6 @@ struct xtensa_config_v2
int xtensa_march_earliest;
};
-typedef struct xtensa_isa_internal_struct xtensa_isa_internal;
-
extern const void *xtensa_load_config (const char *name,
const void *no_plugin_def,
const void *no_name_def);
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 32f73075bad..39d724a3398 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -328,7 +328,7 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
{ 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 },
{ 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_fix_opcodes[] =
@@ -428,7 +428,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
{ 0x00608000, 0xffe08000, "bstrpick.w", "r0:5,r5:5,u16:5,u10:5", 0, 0, 0, 0 },
{ 0x00800000, 0xffc00000, "bstrins.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 },
{ 0x00c00000, 0xffc00000, "bstrpick.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_single_float_opcodes[] =
@@ -475,7 +475,7 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] =
{ 0x011d1000, 0xfffffc00, "ffint.s.w", "f0:5,f5:5", 0, 0, 0, 0 },
{ 0x011d1800, 0xfffffc00, "ffint.s.l", "f0:5,f5:5", 0, 0, 0, 0 },
{ 0x011e4400, 0xfffffc00, "frint.s", "f0:5,f5:5", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_double_float_opcodes[] =
{
@@ -515,7 +515,7 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] =
{ 0x011d2000, 0xfffffc00, "ffint.d.w", "f0:5,f5:5", 0, 0, 0, 0 },
{ 0x011d2800, 0xfffffc00, "ffint.d.l", "f0:5,f5:5", 0, 0, 0, 0 },
{ 0x011e4800, 0xfffffc00, "frint.d", "f0:5,f5:5", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_imm_opcodes[] =
@@ -537,7 +537,7 @@ static struct loongarch_opcode loongarch_imm_opcodes[] =
{ 0x1a000000, 0xfe000000, "pcalau12i", "r0:5,s5:20", 0, 0, 0, 0 },
{ 0x1c000000, 0xfe000000, "pcaddu12i", "r0:5,s5:20", 0, 0, 0, 0 },
{ 0x1e000000, 0xfe000000, "pcaddu18i", "r0:5,s5:20", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_privilege_opcodes[] =
@@ -566,7 +566,7 @@ static struct loongarch_opcode loongarch_privilege_opcodes[] =
{ 0x06483800, 0xffffffff, "ertn", "", 0, 0, 0, 0 },
{ 0x06488000, 0xffff8000, "idle", "u0:15", 0, 0, 0, 0 },
{ 0x06498000, 0xffff8000, "invtlb", "u0:5,r5:5,r10:5", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_4opt_single_float_opcodes[] =
@@ -603,7 +603,7 @@ static struct loongarch_opcode loongarch_4opt_single_float_opcodes[] =
{ 0x0c1c0000, 0xffff8018, "fcmp.cune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
{ 0x0c1c8000, 0xffff8018, "fcmp.sune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
{ 0x0d000000, 0xfffc0000, "fsel", "f0:5,f5:5,f10:5,c15:3", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
@@ -639,7 +639,7 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
{ 0x0c2a8000, 0xffff8018, "fcmp.sor.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
{ 0x0c2c0000, 0xffff8018, "fcmp.cune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
{ 0x0c2c8000, 0xffff8018, "fcmp.sune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_load_store_opcodes[] =
@@ -767,7 +767,7 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
{ 0x387e8000, 0xffff8000, "stle.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x387f0000, 0xffff8000, "stle.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x387f8000, 0xffff8000, "stle.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
@@ -781,7 +781,7 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
{ 0x38750000, 0xffff8000, "fldle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38760000, 0xffff8000, "fstgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38770000, 0xffff8000, "fstle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
@@ -795,7 +795,7 @@ static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
{ 0x38758000, 0xffff8000, "fldle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38768000, 0xffff8000, "fstgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38778000, 0xffff8000, "fstle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_float_jmp_opcodes[] =
@@ -804,7 +804,7 @@ static struct loongarch_opcode loongarch_float_jmp_opcodes[] =
{ 0x48000000, 0xfc000300, "bceqz", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "bcnez", "c,la", "bcnez %1,%%b21(%2)", 0, 0, 0 },
{ 0x48000100, 0xfc000300, "bcnez", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
static struct loongarch_opcode loongarch_jmp_opcodes[] =
@@ -842,7 +842,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
{ 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 },
{ 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 },
{ 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 },
- { 0 } /* Terminate the list. */
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
struct loongarch_ase loongarch_ASEs[] =
@@ -860,5 +860,5 @@ struct loongarch_ase loongarch_ASEs[] =
{ &LARCH_opts.ase_df, loongarch_4opt_double_float_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_sf, loongarch_single_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_df, loongarch_double_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
- { 0 },
+ { 0, 0, 0, 0, { 0 }, 0, 0 },
};
--
Alan Modra
Australia Development Lab, IBM
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