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From: WANG Xuerui <i.swmail@xen0n.name>
To: Feiyang Chen <chris.chenfeiyang@gmail.com>,
	WANG Xuerui <i.swmail@xen0n.name>
Cc: Feiyang Chen <chenfeiyang@loongson.cn>,
	liuzhensong@loongson.cn, xuchenghua@loongson.cn,
	chenhuacai@loongson.cn, binutils@sourceware.org
Subject: Re: [PATCH] LoongArch: Add fcsr register names support
Date: Fri, 16 Jun 2023 17:20:20 +0800	[thread overview]
Message-ID: <aee37443-c363-61bd-1aac-290024564934@xen0n.name> (raw)
In-Reply-To: <CACWXhKnZSzuPw+MhgMUuKAjrxNEdJ-TUzk9XhG+mS0OQ4_f2AA@mail.gmail.com>

Hi,

On 6/14/23 12:27, Feiyang Chen wrote:
> On Tue, Jun 13, 2023 at 5:49 PM WANG Xuerui <i.swmail@xen0n.name> wrote:
>>
>>
>> On 2023/6/12 16:36, Feiyang Chen wrote:
>> [snip]
>>> @@ -142,7 +144,19 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
>>>          info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]);
>>>          break;
>>>        case 'f':
>>> -      info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]);
>>> +      switch (esc2)
>>> +     {
>>> +     case 'c':
>>> +       if (u_imm < 4)
>>> +         info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]);
>>> +       else
>>> +         /* For backward compatibility.  Display using general purpose
>>> +            register names if out of range.  */
>>> +         info->fprintf_func (info->stream, "%s", loongarch_r_normal_name[u_imm]);
>> I don't think it's proper to call *any* of the FCSRs "GPR" (or actually,
>> aliases to FCSR0, but that doesn't matter). What concrete scenario are
>> you trying to keep compatible with? A test case may explain it.
>>
> I agree with you, but the previous method of decoding treated "fcsr"
> as "gr." Therefore, to ensure proper compilation of the possible old
> code, I also need to consider "gr" as "fcsr." If you have a better
> solution, please inform me.
> For example, we may encounter the instruction "movgr2fcsr $r0, $r0,"
> and it is essential to parse it correctly. On another note, I am not
> experienced in creating test cases. Could you please assist me with
> that?
Sorry for the late reply. I meant not disallowing the old forms when 
assembling, but rather removing the workaround when disassembling -- I 
can't see a reason why FCSR0 ~ FCSR3 could be displayed as-is, but other 
unassigned but possible FCSR numbers still get displayed as GPRs; is it 
that you're following the ISA manual's exact wording that says there are 
only 4 FCSRs? In any case I find the special treatment a surprise and 
not very pleasant.

  reply	other threads:[~2023-06-16  9:20 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-12  8:36 Feiyang Chen
2023-06-13  1:05 ` Chenghua Xu
2023-06-13  9:49 ` WANG Xuerui
2023-06-14  4:27   ` Feiyang Chen
2023-06-16  9:20     ` WANG Xuerui [this message]
2023-06-16  9:30       ` Xi Ruoyao
2023-06-14  3:33 ` mengqinggang
2023-06-14  4:14   ` Feiyang Chen
2023-06-14  7:07 ` mengqinggang
2023-06-14  7:28   ` Feiyang Chen
2023-06-14  8:39     ` mengqinggang
2023-06-14  9:27       ` Feiyang Chen

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