From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: jbeulich@suse.com, Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
nelson@rivosinc.com, Nick Clifton <nickc@redhat.com>,
binutils@sourceware.org
Subject: Re: [PATCH] gas/RISC-V: adjust assembler for opcode table re-ordering
Date: Mon, 9 Jan 2023 21:59:34 +0000 (GMT) [thread overview]
Message-ID: <alpine.DEB.2.21.2301092144270.65308@angie.orcam.me.uk> (raw)
In-Reply-To: <mhng-da78c63b-1a53-4a49-8adc-e0e97b9c9259@palmer-ri-x1c9a>
On Mon, 9 Jan 2023, Palmer Dabbelt wrote:
> > > > The similar workaround in my_getSmallExpression() actually looks
> > > > suspicious to me: I expect that it would get in the way of using equates
> > > > "shadowing" names of GPRs.
> > > >
> > > > --- a/gas/config/tc-riscv.c
> > > > +++ b/gas/config/tc-riscv.c
> > > > @@ -3266,6 +3266,17 @@ riscv_ip (char *str, struct riscv_cl_ins
> > > > continue;
> > > >
> > > > case 'a': /* 20-bit PC-relative offset. */
> > > > + /* Like in my_getSmallExpression() we need to avoid emitting
> > > > + a stray undefined symbol if the 1st JAL entry doesn't match,
> > > > + but the 2nd (with 2 operands) might. */
> > > > + if (oparg == insn->args)
> > > > + {
> > > > + asargStart = asarg;
> > > > + if (reg_lookup (&asarg, RCLASS_GPR, NULL)
> > > > + && (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] ==
> > > > ',')))
> > > > + break;
> > > > + asarg = asargStart;
> > > > + }
> > > > jump:
> > > > my_getExpression (imm_expr, asarg);
> > > > asarg = expr_end;
> > >
> > > Thanks for the patch. I have tested it and confirmed it fix the problem
> > > I reported.
> >
> > With 2.40 scheduled to be cut in less than a week, may I ask for an arch
> > maintainer's view here?
>
> Thanks for fixing this. I don't have any issues with what's there, but looks
> like I'm also getting some failures (glibc/multilib errno related stuff). I'm
> trying to bisect those so I can't really get a proper test up now, I'll try to
> do so ASAP as it's really late to have stuff broken.
I wonder why the RISC-V port needs such a hack while the MIPS one
doesn't.
Maciej
next prev parent reply other threads:[~2023-01-09 21:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 12:34 Jan Beulich
2023-01-07 23:29 ` Aurelien Jarno
2023-01-09 17:07 ` Jan Beulich
2023-01-09 19:07 ` Palmer Dabbelt
2023-01-09 21:59 ` Maciej W. Rozycki [this message]
2023-01-10 9:25 ` Jan Beulich
2023-01-10 22:58 ` Maciej W. Rozycki
2023-01-11 9:28 ` Jan Beulich
2023-01-12 1:28 ` Maciej W. Rozycki
2023-01-12 8:26 ` Jan Beulich
2023-01-12 8:40 ` Andrew Waterman
2023-01-10 12:31 ` Nick Clifton
2023-01-10 20:14 ` Palmer Dabbelt
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