From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>
Cc: binutils@sourceware.org
Subject: [PATCH 0/1] RISC-V: Remove RV128-only fmv instructions
Date: Fri, 20 May 2022 20:51:48 +0900 [thread overview]
Message-ID: <cover.1653047503.git.research_trasio@irq.a4lg.com> (raw)
Hello,
While I'm reviewing my Zfinx-related fixes (PATCH v2), I found something
different. There are two RV128-only instructions enabled on RV64!
1. fmv.x.q
2. fmv.q.x
Those instructions will be RV128-only instructions that transfer 128-bit
floating point values between a GPR and a FPR. As RV64 only has 64-bit
general purpose registers, they should not be valid (64-bit transfer
instructions, fmv.x.d and fmv.d.x are, on the other hand, valid).
This patchset is simple. It just removes those instructions and makes
sure that they are invalid on RV64.
Tsukasa OI (1):
RISC-V: Remove RV128-only fmv instructions
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s | 2 ++
include/opcode/riscv-opc.h | 6 ------
opcodes/riscv-opc.c | 2 --
5 files changed, 8 insertions(+), 8 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
base-commit: ef5d515048ba13a06815c8fccc420e6e8098da03
--
2.34.1
next reply other threads:[~2022-05-20 11:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 11:51 Tsukasa OI [this message]
2022-05-20 11:51 ` [PATCH 1/1] " Tsukasa OI
2022-05-20 14:26 ` Nelson Chu
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