* [PATCH 0/1] RISC-V: Remove RV128-only fmv instructions
@ 2022-05-20 11:51 Tsukasa OI
2022-05-20 11:51 ` [PATCH 1/1] " Tsukasa OI
0 siblings, 1 reply; 3+ messages in thread
From: Tsukasa OI @ 2022-05-20 11:51 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Kito Cheng; +Cc: binutils
Hello,
While I'm reviewing my Zfinx-related fixes (PATCH v2), I found something
different. There are two RV128-only instructions enabled on RV64!
1. fmv.x.q
2. fmv.q.x
Those instructions will be RV128-only instructions that transfer 128-bit
floating point values between a GPR and a FPR. As RV64 only has 64-bit
general purpose registers, they should not be valid (64-bit transfer
instructions, fmv.x.d and fmv.d.x are, on the other hand, valid).
This patchset is simple. It just removes those instructions and makes
sure that they are invalid on RV64.
Tsukasa OI (1):
RISC-V: Remove RV128-only fmv instructions
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s | 2 ++
include/opcode/riscv-opc.h | 6 ------
opcodes/riscv-opc.c | 2 --
5 files changed, 8 insertions(+), 8 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
base-commit: ef5d515048ba13a06815c8fccc420e6e8098da03
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1] RISC-V: Remove RV128-only fmv instructions
2022-05-20 11:51 [PATCH 0/1] RISC-V: Remove RV128-only fmv instructions Tsukasa OI
@ 2022-05-20 11:51 ` Tsukasa OI
2022-05-20 14:26 ` Nelson Chu
0 siblings, 1 reply; 3+ messages in thread
From: Tsukasa OI @ 2022-05-20 11:51 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Kito Cheng; +Cc: binutils
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.
gas/ChangeLog:
* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
---
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l | 3 +++
gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s | 2 ++
include/opcode/riscv-opc.h | 6 ------
opcodes/riscv-opc.c | 2 --
5 files changed, 8 insertions(+), 8 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
new file mode 100644
index 00000000000..2913a1adc14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64iq
+#source: fmv.x.q-rv64-fail.s
+#error_output: fmv.x.q-rv64-fail.l
diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
new file mode 100644
index 00000000000..9fb1f8c390e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*Error: unrecognized opcode `fmv\.x\.q a0,fa0'
+.*Error: unrecognized opcode `fmv\.q\.x fa0,a0'
diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
new file mode 100644
index 00000000000..320a5575afc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
@@ -0,0 +1,2 @@
+fmv.x.q a0, fa0
+fmv.q.x fa0, a0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ecbb8b8487b..2e867965e12 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -389,8 +389,6 @@
#define MASK_FCVT_L_Q 0xfff0007f
#define MATCH_FCVT_LU_Q 0xc6300053
#define MASK_FCVT_LU_Q 0xfff0007f
-#define MATCH_FMV_X_Q 0xe6000053
-#define MASK_FMV_X_Q 0xfff0707f
#define MATCH_FCLASS_Q 0xe6001053
#define MASK_FCLASS_Q 0xfff0707f
#define MATCH_FCVT_S_W 0xd0000053
@@ -421,8 +419,6 @@
#define MASK_FCVT_Q_L 0xfff0007f
#define MATCH_FCVT_Q_LU 0xd6300053
#define MASK_FCVT_Q_LU 0xfff0007f
-#define MATCH_FMV_Q_X 0xf6000053
-#define MASK_FMV_Q_X 0xfff0707f
#define MATCH_CLZ 0x60001013
#define MASK_CLZ 0xfff0707f
#define MATCH_CTZ 0x60101013
@@ -2650,7 +2646,6 @@ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
-DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
@@ -2666,7 +2661,6 @@ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
-DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7524be7feae..eaba3cb46cc 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -825,8 +825,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
-{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] RISC-V: Remove RV128-only fmv instructions
2022-05-20 11:51 ` [PATCH 1/1] " Tsukasa OI
@ 2022-05-20 14:26 ` Nelson Chu
0 siblings, 0 replies; 3+ messages in thread
From: Nelson Chu @ 2022-05-20 14:26 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Palmer Dabbelt, Kito Cheng, Binutils
In general we won't delete instructions. But I think the instructions
you mentioned shouldn't be used until we have rv128 support. So LGTM,
committed.
Thanks
Nelson
On Fri, May 20, 2022 at 7:52 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
> it should be removed until RV128 support for GNU Binutils is required
> again.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
> * testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
> * testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
> MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
> ---
> gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d | 3 +++
> gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l | 3 +++
> gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s | 2 ++
> include/opcode/riscv-opc.h | 6 ------
> opcodes/riscv-opc.c | 2 --
> 5 files changed, 8 insertions(+), 8 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
> create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
> create mode 100644 gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
>
> diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
> new file mode 100644
> index 00000000000..2913a1adc14
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64iq
> +#source: fmv.x.q-rv64-fail.s
> +#error_output: fmv.x.q-rv64-fail.l
> diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
> new file mode 100644
> index 00000000000..9fb1f8c390e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*Error: unrecognized opcode `fmv\.x\.q a0,fa0'
> +.*Error: unrecognized opcode `fmv\.q\.x fa0,a0'
> diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
> new file mode 100644
> index 00000000000..320a5575afc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
> @@ -0,0 +1,2 @@
> +fmv.x.q a0, fa0
> +fmv.q.x fa0, a0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index ecbb8b8487b..2e867965e12 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -389,8 +389,6 @@
> #define MASK_FCVT_L_Q 0xfff0007f
> #define MATCH_FCVT_LU_Q 0xc6300053
> #define MASK_FCVT_LU_Q 0xfff0007f
> -#define MATCH_FMV_X_Q 0xe6000053
> -#define MASK_FMV_X_Q 0xfff0707f
> #define MATCH_FCLASS_Q 0xe6001053
> #define MASK_FCLASS_Q 0xfff0707f
> #define MATCH_FCVT_S_W 0xd0000053
> @@ -421,8 +419,6 @@
> #define MASK_FCVT_Q_L 0xfff0007f
> #define MATCH_FCVT_Q_LU 0xd6300053
> #define MASK_FCVT_Q_LU 0xfff0007f
> -#define MATCH_FMV_Q_X 0xf6000053
> -#define MASK_FMV_Q_X 0xfff0707f
> #define MATCH_CLZ 0x60001013
> #define MASK_CLZ 0xfff0707f
> #define MATCH_CTZ 0x60101013
> @@ -2650,7 +2646,6 @@ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
> DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
> DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
> DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
> -DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
> DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
> DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
> DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
> @@ -2666,7 +2661,6 @@ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
> DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
> DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
> DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
> -DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
> DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
> DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
> DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 7524be7feae..eaba3cb46cc 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -825,8 +825,6 @@ const struct riscv_opcode riscv_opcodes[] =
> {"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> {"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> {"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> -{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
> -{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
> {"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-05-20 11:51 [PATCH 0/1] RISC-V: Remove RV128-only fmv instructions Tsukasa OI
2022-05-20 11:51 ` [PATCH 1/1] " Tsukasa OI
2022-05-20 14:26 ` Nelson Chu
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