public inbox for binutils@sourceware.org
 help / color / mirror / Atom feed
From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson.chu@sifive.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [RFC PATCH 0/5] RISC-V: Support mapping symbols with ISA string
Date: Thu, 11 Aug 2022 16:00:48 +0900	[thread overview]
Message-ID: <cover.1660201178.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <1659692183-5682-1-git-send-email-nelson.chu@sifive.com>

Hello,

After a detailed analysis of Nelson's patch, I made my own version based
on it.  It clearly lacks proper attribution (Signed-Off-By lines) and
should be considered as RFC.  Nelson, I would like to hear your thoughts.

Nelson's original patch:
<https://sourceware.org/pipermail/binutils/2022-August/122220.html>
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_mapping_sym_with_arch>

    Also see:

    [1] Proposal: Extend .option directive for control enabled extensions
    on specific code region,
    <https://github.com/riscv-non-isa/riscv-asm-manual/pull/67>

    [2] Proposal: Add mapping symbol,
    <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196>



I found two issues on his patch:

(1) "$x" is the start of instructions with the default architecture.
Nelson's patch effectively handled it as a change to code but with no ISA
changes and this is clearly against Kito's proposal:

<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196/files#diff-361ae9d87b1e297413d1551ec0743e2e893217198eac78e95568a3718be26fb1R805>

> an instruction mapping symobl
> without ISA string means using ISA configuration from ELF attribute.

In my version, "$x" is emitted if no architecture string is changed by
.option directives and such.  Even if the arch is changed to revert the
original, it's not the same:

    # Example
    # (we have default architecture here such as RV32I)
    .option arch, +c
    .option arch, -c
    # (not default, even if the resulting ISA string is the same)

The only exception is when we use ".option push" before the architecture is
changed and that state is restored by ".option pop".

    # Example
    # (we have default architecture here)
    .option push
    # (now we can make changes to the architecture)
    .option arch, +c
    # (... then restore it)
    .option pop
    # (now we have the default architecture, again)

This also applies to the disassembler.  If we meet the "$x" mapping symbol,
we need to revert to the default architecture.  Since we need to save the
default architecture, the disassembler part is a bit more complex than
Nelson's implementation.


(2) Also, the mapping symbols are handled per section but "current"
architecture as managed by the assembler is not.  It did work previously
because we didn't have to keep track of the architecture (ISA string) but
we have to explicitly handle that now.

So, the first instruction after the section change requires emitting the
mapping symbol if necessary.  Still, to do that, looking up the last
mapping symbol is sufficient (saving RISC-V preset list is not required).


My changes made MAP_INSN_ARCH not necessary so I removed it.


I also added four test cases (mapping-{05..08}) whether we are handling
complex situations correctly.  Note that mapping-{05,06,08} will fail on
Nelson's implementation.



p.s.

Nelson, are you going to upstream this feature now or wait until the
proposal by Kito is approved?  If your answer is the latter, I will submit
my disassembler changes first (to make the disassembler support of this
feature cleaner).



Thanks,
Tsukasa




Tsukasa OI (5):
  RISC-V: Use bool on riscv_set_options members
  gas: Copyediting on tc-riscv.c
  RISC-V: Mapping symbols with ISA string on assembler
  RISC-V: Mapping symbols with ISA string on disassembler
  RISC-V: New testcases for mapping symbols w/ ISA

 gas/config/tc-riscv.c                         | 67 +++++++++++++++----
 gas/config/tc-riscv.h                         |  5 ++
 gas/testsuite/gas/riscv/mapping-01a.d         |  4 +-
 gas/testsuite/gas/riscv/mapping-02a.d         |  4 +-
 gas/testsuite/gas/riscv/mapping-03a.d         | 10 +--
 gas/testsuite/gas/riscv/mapping-04a.d         |  4 +-
 gas/testsuite/gas/riscv/mapping-05.s          | 11 +++
 gas/testsuite/gas/riscv/mapping-05a.d         | 14 ++++
 gas/testsuite/gas/riscv/mapping-05b.d         | 14 ++++
 gas/testsuite/gas/riscv/mapping-06.s          | 11 +++
 gas/testsuite/gas/riscv/mapping-06a.d         | 14 ++++
 gas/testsuite/gas/riscv/mapping-06b.d         | 14 ++++
 gas/testsuite/gas/riscv/mapping-07.s          | 12 ++++
 gas/testsuite/gas/riscv/mapping-07a.d         | 14 ++++
 gas/testsuite/gas/riscv/mapping-07b.d         | 21 ++++++
 gas/testsuite/gas/riscv/mapping-08.s          | 34 ++++++++++
 gas/testsuite/gas/riscv/mapping-08a.d         | 18 +++++
 gas/testsuite/gas/riscv/mapping-08b.d         | 23 +++++++
 gas/testsuite/gas/riscv/mapping-norelax-03a.d | 10 +--
 gas/testsuite/gas/riscv/mapping-norelax-04a.d |  4 +-
 gas/testsuite/gas/riscv/option-arch-01a.d     |  2 +-
 opcodes/riscv-dis.c                           | 44 ++++++++++--
 22 files changed, 317 insertions(+), 37 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/mapping-05.s
 create mode 100644 gas/testsuite/gas/riscv/mapping-05a.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-05b.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-06.s
 create mode 100644 gas/testsuite/gas/riscv/mapping-06a.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-06b.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-07.s
 create mode 100644 gas/testsuite/gas/riscv/mapping-07a.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-07b.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-08.s
 create mode 100644 gas/testsuite/gas/riscv/mapping-08a.d
 create mode 100644 gas/testsuite/gas/riscv/mapping-08b.d


base-commit: 453595283c323e106a60b229999756b45ae6b2d8
-- 
2.34.1


  parent reply	other threads:[~2022-08-11  7:01 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-05  9:36 [PATCH] RISC-V: Output mapping symbols with ISA string once .option arch is used Nelson Chu
2022-08-05 10:31 ` Tsukasa OI
2022-08-11  7:00 ` Tsukasa OI [this message]
2022-08-11  7:00   ` [RFC PATCH 1/5] RISC-V: Use bool on riscv_set_options members Tsukasa OI
2022-08-11  7:00   ` [RFC PATCH 2/5] gas: Copyediting on tc-riscv.c Tsukasa OI
2022-08-11  7:00   ` [RFC PATCH 3/5] RISC-V: Mapping symbols with ISA string on assembler Tsukasa OI
2022-08-11  7:31     ` Jan Beulich
2022-08-11 11:43       ` Tsukasa OI
2022-08-11 12:12         ` Jan Beulich
2022-08-11  7:00   ` [RFC PATCH 4/5] RISC-V: Mapping symbols with ISA string on disassembler Tsukasa OI
2022-08-11  7:00   ` [RFC PATCH 5/5] RISC-V: New testcases for mapping symbols w/ ISA Tsukasa OI

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1660201178.git.research_trasio@irq.a4lg.com \
    --to=research_trasio@irq.a4lg.com \
    --cc=binutils@sourceware.org \
    --cc=kito.cheng@sifive.com \
    --cc=nelson.chu@sifive.com \
    --cc=palmer@dabbelt.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).