From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 0/1] RISC-V: RISC-V: Move standard hints before all instructions
Date: Sat, 8 Oct 2022 04:31:14 +0000 [thread overview]
Message-ID: <cover.1665203441.git.research_trasio@irq.a4lg.com> (raw)
Hello,
GitHub tracker:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_opcode_tidying_hints_1>
This is another small tidying patchset.
Because of the scanning process of the RISC-V disassembler, all standard
hints must be placed before corresponding instruction.
In the past, "prefetch.[irw]" (from 'Zicbop') hints are placed just before
ORI and "pause" (from 'Zihintpause') is placed just before FENCE. It's not
bad but will force the developer to "taint" basic instructions section.
Considering upcoming 'Zihintntl' standard hints will be a bit more complex
than the current hints (some can be a part of either "ADD" or "C.ADD") and
the disassembler is fine as long as a hint instruction is placed before the
base instruction (no need them to be adjacent), I think moving all standard
hints before all real instructions might improve the readability and won't
disrupt the indentation of basic instructions anymore.
Thanks,
Tsukasa
Tsukasa OI (1):
RISC-V: Move standard hints before all instructions
opcodes/riscv-opc.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
--
2.34.1
next reply other threads:[~2022-10-08 4:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-08 4:31 Tsukasa OI [this message]
2022-10-08 4:31 ` [PATCH 1/1] " Tsukasa OI
2022-10-14 1:37 ` Nelson Chu
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