[REVIEW ONLY 0/4] UNRATIFIED RISC-V: Add support for BFloat16 extensions

[REVIEW ONLY 0/4] UNRATIFIED RISC-V: Add support for BFloat16 extensions

[Tsukasa OI]

Hello,

This patch set implements three extensions in the RISC-V BF16 Extensions
specification:
<https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999>

Each patch implements following extensions one by one (PATCH 1-3/4).

1.  'Zfbfmin' (scalar BF16 conversion extension)
2.  'Zvfbfmin' (vector BF16 narrowing/widening conversion-only extension)
3.  'Zvfbfwma' (vector BF16 widening multiply-accumlate extension)

The extension versions are set to "0.8" as in the documentation
(not final "1.0").

Although it's small, it covers some of important machine learning workloads
(especially 'Zvfbfwma' extension).  I hope this patch set helps testing
this draft extension on the simulator.

PATCH 4/4 is a tentative support of an assembler directive: ".bfloat16".
Although not included in the RISC-V Assembly Programmer's Manual, the final
assembler directive will be likely ".bfloat16" (like x86 and AArch64).
Test cases are ported from AArch64.

Thanks,
Tsukasa




Tsukasa OI (4):
  UNRATIFIED RISC-V: Add 'Zfbfmin' extension
  UNRATIFIED RISC-V: Add 'Zvfbfmin' extension
  UNRATIFIED RISC-V: Add 'Zvfbfwma' extension
  RISC-V: Tentative ".bfloat16" assembly support

 bfd/elfxx-riscv.c                     | 24 ++++++++++++++++++++++--
 gas/config/tc-riscv.c                 |  3 ++-
 gas/testsuite/gas/riscv/bfloat16-be.d | 10 ++++++++++
 gas/testsuite/gas/riscv/bfloat16-le.d | 10 ++++++++++
 gas/testsuite/gas/riscv/bfloat16.s    | 19 +++++++++++++++++++
 gas/testsuite/gas/riscv/zfbfmin.d     | 15 +++++++++++++++
 gas/testsuite/gas/riscv/zfbfmin.s     | 10 ++++++++++
 gas/testsuite/gas/riscv/zvfbfmin.d    | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfmin.s    |  5 +++++
 gas/testsuite/gas/riscv/zvfbfwma.d    | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfwma.s    |  5 +++++
 include/opcode/riscv-opc.h            | 24 ++++++++++++++++++++++++
 include/opcode/riscv.h                |  3 +++
 opcodes/riscv-opc.c                   | 13 +++++++++++++
 14 files changed, 162 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/bfloat16-be.d
 create mode 100644 gas/testsuite/gas/riscv/bfloat16-le.d
 create mode 100644 gas/testsuite/gas/riscv/bfloat16.s
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s
 create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s


base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
-- 
2.41.0

[REVIEW ONLY 1/4] UNRATIFIED RISC-V: Add 'Zfbfmin' extension

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zfbfmin' extension, the scalar BF16
conversion extension.  It consists of two new instructions and four
previously 'Zfhmin'-only instructions.

This commit is based on the following specification:
<https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets) Add 'Zfbfmin' -> 'F'.
	(riscv_supported_std_z_ext): Add 'Zfbfmin'.
	(riscv_multi_subset_supports): Recategory INSN_CLASS_ZFHMIN to mean
	'Zfhmin' or 'Zfbfmin'.  Add support to INSN_CLASS_ZFBFMIN.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zfbfmin.s: New test.
	* testsuite/gas/riscv/zfbfmin.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S,
	MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zfbfmin'-only instructions.
---
 bfd/elfxx-riscv.c                 | 11 +++++++++--
 gas/testsuite/gas/riscv/zfbfmin.d | 15 +++++++++++++++
 gas/testsuite/gas/riscv/zfbfmin.s | 10 ++++++++++
 include/opcode/riscv-opc.h        |  8 ++++++++
 include/opcode/riscv.h            |  1 +
 opcodes/riscv-opc.c               |  5 +++++
 6 files changed, 48 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ba5165766b2b..edc2b17f5d3a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1136,6 +1136,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcf", "f",		check_implicit_always},
   {"zfa", "f",		check_implicit_always},
   {"d", "f",		check_implicit_always},
+  {"zfbfmin", "f",	check_implicit_always},
   {"zfh", "zfhmin",	check_implicit_always},
   {"zfhmin", "f",	check_implicit_always},
   {"f", "zicsr",	check_implicit_always},
@@ -1254,6 +1255,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
+  {"zfbfmin",		ISA_SPEC_CLASS_DRAFT,		0, 8,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2422,11 +2424,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_Q_INX:
       return (riscv_subset_supports (rps, "q")
 	      || riscv_subset_supports (rps, "zqinx"));
+    case INSN_CLASS_ZFBFMIN:
+      return riscv_subset_supports (rps, "zfbfmin");
     case INSN_CLASS_ZFH_INX:
       return (riscv_subset_supports (rps, "zfh")
 	      || riscv_subset_supports (rps, "zhinx"));
     case INSN_CLASS_ZFHMIN:
-      return riscv_subset_supports (rps, "zfhmin");
+      return (riscv_subset_supports (rps, "zfhmin")
+	      || riscv_subset_supports (rps, "zfbfmin"));
     case INSN_CLASS_ZFHMIN_INX:
       return (riscv_subset_supports (rps, "zfhmin")
 	      || riscv_subset_supports (rps, "zhinxmin"));
@@ -2625,10 +2630,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("d' or `zdinx");
     case INSN_CLASS_Q_INX:
       return _("q' or `zqinx");
+    case INSN_CLASS_ZFBFMIN:
+      return "zfbfmin";
     case INSN_CLASS_ZFH_INX:
       return _("zfh' or `zhinx");
     case INSN_CLASS_ZFHMIN:
-      return "zfhmin";
+      return _("zfhmin' or `zfbfmin");
     case INSN_CLASS_ZFHMIN_INX:
       return _("zfhmin' or `zhinxmin");
     case INSN_CLASS_ZFHMIN_AND_D_INX:
diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d
new file mode 100644
index 000000000000..28675457a0a9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_zfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4485f553[ 	]+fcvt\.bf16\.s[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44859553[ 	]+fcvt\.bf16\.s[ 	]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+40658553[ 	]+fcvt\.s\.bf16[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+00059507[ 	]+flh[ 	]+fa0,0\(a1\)
+[ 	]+[0-9a-f]+:[ 	]+00a59027[ 	]+fsh[ 	]+fa0,0\(a1\)
+[ 	]+[0-9a-f]+:[ 	]+e4058553[ 	]+fmv\.x\.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+f4058553[ 	]+fmv\.h\.x[ 	]+fa0,a1
diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s
new file mode 100644
index 000000000000..a0670a33ce69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.s
@@ -0,0 +1,10 @@
+target:
+	# Zfbfmin only instructions
+	fcvt.bf16.s	fa0, fa1
+	fcvt.bf16.s	fa0, fa1, rtz
+	fcvt.s.bf16	fa0, fa1
+	# Instructions shared with Zfhmin
+	flh		fa0, 0(a1)
+	fsh		fa0, 0(a1)
+	fmv.x.h		a0, fa1
+	fmv.h.x		fa0, a1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 53f5f2005085..864faddcc6a5 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2121,6 +2121,11 @@
 #define MASK_VDOTUVV  0xfc00707f
 #define MATCH_VFDOTVV  0xe4001057
 #define MASK_VFDOTVV  0xfc00707f
+/* Zfbfmin instructions.  */
+#define MATCH_FCVT_BF16_S 0x44800053
+#define MASK_FCVT_BF16_S 0xfff0007f
+#define MATCH_FCVT_S_BF16 0x40600053
+#define MASK_FCVT_S_BF16 0xfff0007f
 /* Zvbb instructions.  */
 #define MATCH_VANDN_VV 0x4000057
 #define MASK_VANDN_VV 0xfc00707f
@@ -3344,6 +3349,9 @@ DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zfbfmin instructions.  */
+DECLARE_INSN(fcvt_bf16_s, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
+DECLARE_INSN(fcvt_s_bf16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
 /* Zvbb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 808f36573030..4db29287ebe9 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -398,6 +398,7 @@ enum riscv_insn_class
   INSN_CLASS_F_INX,
   INSN_CLASS_D_INX,
   INSN_CLASS_Q_INX,
+  INSN_CLASS_ZFBFMIN,
   INSN_CLASS_ZFH_INX,
   INSN_CLASS_ZFHMIN,
   INSN_CLASS_ZFHMIN_INX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6a854736fec0..5c9809c3c4f7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -974,6 +974,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
 
+/* Zfbfmin instructions.  */
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN,     "D,S",   MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN,     "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
+{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN,     "D,S",   MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
+
 /* Zfa instructions.  */
 {"fli.s",       0, INSN_CLASS_ZFA,         "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },
 {"fli.d",       0, INSN_CLASS_D_AND_ZFA,   "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 },
-- 
2.41.0

[REVIEW ONLY 2/4] UNRATIFIED RISC-V: Add 'Zvfbfmin' extension

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zvfbfmin' extension, the vector BF16
conversion only extension, consisting of two narrowing / widening conversion
instructions between BF16 and FP32.

This commit is based on the following specification:
<https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets) Add implications 'Zvfbfmin'
	-> 'Zfbfmin' and 'Zve32f'.
	(riscv_supported_std_z_ext): Add 'Zvfbfmin'.
	(riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFMIN.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvfbfmin.s: New test.
	* testsuite/gas/riscv/zvfbfmin.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W,
	MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZVFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zvfbfmin' instructions.
---
 bfd/elfxx-riscv.c                  |  7 +++++++
 gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfmin.s |  5 +++++
 include/opcode/riscv-opc.h         |  8 ++++++++
 include/opcode/riscv.h             |  1 +
 opcodes/riscv-opc.c                |  4 ++++
 6 files changed, 37 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index edc2b17f5d3a..daf60010640a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1110,6 +1110,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
+  {"zvfbfmin", "zfbfmin",	check_implicit_always},
+  {"zvfbfmin", "zve32f",	check_implicit_always},
   {"zve64d", "d",	check_implicit_always},
   {"zve64d", "zve64f",	check_implicit_always},
   {"zve64f", "zve32f",	check_implicit_always},
@@ -1288,6 +1290,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		0, 8,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkng",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2502,6 +2505,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVFBFMIN:
+      return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_ZVKNED:
@@ -2722,6 +2727,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
+    case INSN_CLASS_ZVFBFMIN:
+      return "zvfbfmin";
     case INSN_CLASS_ZVBC:
       return _("zvbc");
     case INSN_CLASS_ZVKG:
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d
new file mode 100644
index 000000000000..b15cff818716
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zvfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4a8e9257[ 	]+vfncvtbf16\.f\.f\.w[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+488e9257[ 	]+vfncvtbf16\.f\.f\.w[ 	]+v4,v8,v0\.t
+[ 	]+[0-9a-f]+:[ 	]+4a869257[ 	]+vfwcvtbf16\.f\.f\.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48869257[ 	]+vfwcvtbf16\.f\.f\.v[ 	]+v4,v8,v0\.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s
new file mode 100644
index 000000000000..e732e6ba99b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.s
@@ -0,0 +1,5 @@
+target:
+	vfncvtbf16.f.f.w v4, v8
+	vfncvtbf16.f.f.w v4, v8, v0.t
+	vfwcvtbf16.f.f.v v4, v8
+	vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 864faddcc6a5..2a631a871ecd 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2168,6 +2168,11 @@
 #define MASK_VCLMULH_VV 0xfc00707f
 #define MATCH_VCLMULH_VX 0x34006057
 #define MASK_VCLMULH_VX 0xfc00707f
+/* Zvfbfmin instructions.  */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
 /* Zvkg instructions.  */
 #define MATCH_VGHSH_VV 0xb2002077
 #define MASK_VGHSH_VV 0xfe00707f
@@ -3374,6 +3379,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
 DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
 DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
 DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvfbfmin instructions.  */
+DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 4db29287ebe9..44105ba8698b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -427,6 +427,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 5c9809c3c4f7..c2f90c900bd1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1926,6 +1926,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
 {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
 
+/* Zvfbfmin instructions.  */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
 /* Zvkg instructions.  */
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
-- 
2.41.0

[REVIEW ONLY 3/4] UNRATIFIED RISC-V: Add 'Zvfbfwma' extension

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zvfbfwma' extension, the vector BF16
multiply then FP32 accumlation extension, consisting of two widening
multiply-accumulate instructions.

This commit is based on the following specification:
<https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets) Add 'Zvfbfwma'
	-> 'Zvfbfmin' implication.
	(riscv_supported_std_z_ext): Add 'Zvfbfwma'.
	(riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFWMA.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvfbfwma.s: New test.
	* testsuite/gas/riscv/zvfbfwma.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF,
	MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV) New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZVFBFWMA.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zvfbfwma' instructions.
---
 bfd/elfxx-riscv.c                  |  6 ++++++
 gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfwma.s |  5 +++++
 include/opcode/riscv-opc.h         |  8 ++++++++
 include/opcode/riscv.h             |  1 +
 opcodes/riscv-opc.c                |  4 ++++
 6 files changed, 36 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index daf60010640a..57bbc82f7f7f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1110,6 +1110,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
+  {"zvfbfwma", "zvfbfmin",	check_implicit_always},
   {"zvfbfmin", "zfbfmin",	check_implicit_always},
   {"zvfbfmin", "zve32f",	check_implicit_always},
   {"zve64d", "d",	check_implicit_always},
@@ -1291,6 +1292,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		0, 8,  0 },
+  {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		0, 8,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkng",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2507,6 +2509,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_ZVFBFMIN:
       return riscv_subset_supports (rps, "zvfbfmin");
+    case INSN_CLASS_ZVFBFWMA:
+      return riscv_subset_supports (rps, "zvfbfwma");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_ZVKNED:
@@ -2729,6 +2733,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbb");
     case INSN_CLASS_ZVFBFMIN:
       return "zvfbfmin";
+    case INSN_CLASS_ZVFBFWMA:
+      return "zvfbfwma";
     case INSN_CLASS_ZVBC:
       return _("zvbc");
     case INSN_CLASS_ZVKG:
diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d
new file mode 100644
index 000000000000..3597bde0e4af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zvfbfwma
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+ee861257[ 	]+vfwmaccbf16.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ee865257[ 	]+vfwmaccbf16.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+ec861257[ 	]+vfwmaccbf16.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ec865257[ 	]+vfwmaccbf16.vf[ 	]+v4,v8,fa2,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s
new file mode 100644
index 000000000000..d44c09c27f10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.s
@@ -0,0 +1,5 @@
+target:
+	vfwmaccbf16.vv v4, v8, v12
+	vfwmaccbf16.vf v4, v8, fa2
+	vfwmaccbf16.vv v4, v8, v12, v0.t
+	vfwmaccbf16.vf v4, v8, fa2, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2a631a871ecd..f57aca4c6498 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2173,6 +2173,11 @@
 #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
 #define MATCH_VFWCVTBF16_F_F_V 0x48069057
 #define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
+/* Zvfbfwma instructions.  */
+#define MATCH_VFWMACCBF16_VF 0xec005057
+#define MASK_VFWMACCBF16_VF 0xfc00707f
+#define MATCH_VFWMACCBF16_VV 0xec001057
+#define MASK_VFWMACCBF16_VV 0xfc00707f
 /* Zvkg instructions.  */
 #define MATCH_VGHSH_VV 0xb2002077
 #define MASK_VGHSH_VV 0xfe00707f
@@ -3382,6 +3387,9 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Zvfbfmin instructions.  */
 DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
 DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
+/* Zvfbfwma instructions.  */
+DECLARE_INSN(vfwmaccbf16_vf, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
+DECLARE_INSN(vfwmaccbf16_vv, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 44105ba8698b..9fbe5392a45e 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -428,6 +428,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
+  INSN_CLASS_ZVFBFWMA,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c2f90c900bd1..f8001b601d90 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1930,6 +1930,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
 {"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
 
+/* Zvfbfwma instructions.  */
+{"vfwmaccbf16.vv",   0, INSN_CLASS_ZVFBFWMA, "Vd,Vt,VsVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
+{"vfwmaccbf16.vf",   0, INSN_CLASS_ZVFBFWMA, "Vd,Vt,SVm", MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
+
 /* Zvkg instructions.  */
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
-- 
2.41.0

[REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit adds an assembler directive ".bfloat16" to help BFloat16
extensions ('Zfbfmin', 'Zvfbfmin' and 'Zvfbfwma') users.

gas/ChangeLog:

	* config/tc-riscv.c (FLT_CHARS): Add BFloat16 'b' to supported
	floating point formats.
	(riscv_pseudo_table) Add ".bfloat16" directive.
	* testsuite/gas/riscv/bfloat16.s: Copied from
	testsuite/gas/aarch64/bfloat16-directive.s.
	* testsuite/gas/riscv/bfloat16-be.d: New test ported from
	testsuite/gas/aarch64/bfloat16-directive-be.d and float16-be.d.
	* testsuite/gas/riscv/bfloat16-le.d: New test ported from
	testsuite/gas/aarch64/bfloat16-directive-le.d and float16-le.d.
---
 gas/config/tc-riscv.c                 |  3 ++-
 gas/testsuite/gas/riscv/bfloat16-be.d | 10 ++++++++++
 gas/testsuite/gas/riscv/bfloat16-le.d | 10 ++++++++++
 gas/testsuite/gas/riscv/bfloat16.s    | 19 +++++++++++++++++++
 4 files changed, 41 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/bfloat16-be.d
 create mode 100644 gas/testsuite/gas/riscv/bfloat16-le.d
 create mode 100644 gas/testsuite/gas/riscv/bfloat16.s

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index aaf8b9be64fd..9f15233c7b99 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant.
    As in 0f12.456 or 0d1.2345e12.  */
-const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
+const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
 
 /* Indicate we are already assemble any instructions or not.  */
 static bool start_assemble = false;
@@ -5178,6 +5178,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
   {"attribute", s_riscv_attribute, 0},
   {"variant_cc", s_variant_cc, 0},
   {"float16", float_cons, 'h'},
+  {"bfloat16", float_cons, 'b'},
 
   { NULL, NULL, 0 },
 };
diff --git a/gas/testsuite/gas/riscv/bfloat16-be.d b/gas/testsuite/gas/riscv/bfloat16-be.d
new file mode 100644
index 000000000000..8775ab035f6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bfloat16-be.d
@@ -0,0 +1,10 @@
+# source: bfloat16.s
+# objdump: -sj .data
+# as: -mbig-endian
+
+.*: +file format .*
+
+Contents of section \.data:
+ 0000 41403dfc 000042f7 8000c2f7 7fff7f80  .*
+ 0010 ff807f7f ff7f0080 80800001 8001007f  .*
+ 0020 807f3f80 bf804000 c000.*
diff --git a/gas/testsuite/gas/riscv/bfloat16-le.d b/gas/testsuite/gas/riscv/bfloat16-le.d
new file mode 100644
index 000000000000..4de8b2fed68b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bfloat16-le.d
@@ -0,0 +1,10 @@
+# source: bfloat16.s
+# objdump: -sj .data
+# as: -mlittle-endian
+
+.*: +file format .*
+
+Contents of section \.data:
+ 0000 4041fc3d 0000f742 0080f7c2 ff7f807f  .*
+ 0010 80ff7f7f 7fff8000 80800100 01807f00  .*
+ 0020 7f80803f 80bf0040 00c0.*
diff --git a/gas/testsuite/gas/riscv/bfloat16.s b/gas/testsuite/gas/riscv/bfloat16.s
new file mode 100644
index 000000000000..66e17e4fc7da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bfloat16.s
@@ -0,0 +1,19 @@
+.data
+	.bfloat16 12.0
+	.bfloat16 0.123
+	.bfloat16 +0.0
+	.bfloat16 123.4
+	.bfloat16 -0.0
+	.bfloat16 -123.4
+	.bfloat16 NaN
+	.bfloat16 Inf
+	.bfloat16 -Inf
+	.bfloat16 3.390e+38
+	.bfloat16 -3.390e+38
+	.bfloat16 1.175e-38
+	.bfloat16 -1.175e-38
+	.bfloat16 9.194e-41
+	.bfloat16 -9.194e-41
+	.bfloat16 1.167e-38
+	.bfloat16 -1.167e-38
+	.bfloat16 1.0, -1, 2.0, -2
-- 
2.41.0

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Jan Beulich]

On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>  
>  /* Chars that mean this number is a floating point constant.
>     As in 0f12.456 or 0d1.2345e12.  */
> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";

I realize Arm64 also has it this way (x86 doesn't), but are you sure
about only adding 'b' and not also 'B'? Aiui this introduces a needless
special case of case sensitivity.

Jan

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Tsukasa OI]

On 2023/08/03 15:47, Jan Beulich wrote:
> On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
>> +++ b/gas/config/tc-riscv.c
>> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>>  
>>  /* Chars that mean this number is a floating point constant.
>>     As in 0f12.456 or 0d1.2345e12.  */
>> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
>> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
> 
> I realize Arm64 also has it this way (x86 doesn't), but are you sure
> about only adding 'b' and not also 'B'? Aiui this introduces a needless
> special case of case sensitivity.
> 
> Jan
> 

I'm not sure (the only reason I did so is because what I saw is AArch64
code).  So, I'll investigate whether introducing additional character
will benefit (I think there's not so many cases but there might be at
least one).

Tsukasa

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Tsukasa OI]

On 2023/08/03 16:17, Tsukasa OI via Binutils wrote:
> 
> 
> On 2023/08/03 15:47, Jan Beulich wrote:
>> On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
>>> +++ b/gas/config/tc-riscv.c
>>> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>>>  
>>>  /* Chars that mean this number is a floating point constant.
>>>     As in 0f12.456 or 0d1.2345e12.  */
>>> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
>>> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
>>
>> I realize Arm64 also has it this way (x86 doesn't), but are you sure
>> about only adding 'b' and not also 'B'? Aiui this introduces a needless
>> special case of case sensitivity.
>>
>> Jan
>>
> 
> I'm not sure (the only reason I did so is because what I saw is AArch64
> code).  So, I'll investigate whether introducing additional character
> will benefit (I think there's not so many cases but there might be at
> least one).
> 
> Tsukasa
> 

I checked the code and actually, no code is affected by lacking 'B'.  I
first thought something like 0B:1234 (raw hexadecimal representation as
float) is affected but in a floating number literal, any 0[a-zA-Z]:1234
turns to a 16-bit word 0x1234, reinterpreted as a floating point number
(and the second character is just ignored and the length is checked
against another parameter).

So, lacking 'B' here is no problem for us and adding 'B' will be rather
confusing (than just 'b').

Thanks,
Tsukasa

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Jan Beulich]

On 03.08.2023 09:51, Tsukasa OI wrote:
> On 2023/08/03 16:17, Tsukasa OI via Binutils wrote:
>>
>>
>> On 2023/08/03 15:47, Jan Beulich wrote:
>>> On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
>>>> +++ b/gas/config/tc-riscv.c
>>>> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>>>>  
>>>>  /* Chars that mean this number is a floating point constant.
>>>>     As in 0f12.456 or 0d1.2345e12.  */
>>>> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
>>>> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
>>>
>>> I realize Arm64 also has it this way (x86 doesn't), but are you sure
>>> about only adding 'b' and not also 'B'? Aiui this introduces a needless
>>> special case of case sensitivity.
>>
>> I'm not sure (the only reason I did so is because what I saw is AArch64
>> code).  So, I'll investigate whether introducing additional character
>> will benefit (I think there's not so many cases but there might be at
>> least one).
> 
> I checked the code and actually, no code is affected by lacking 'B'.  I
> first thought something like 0B:1234 (raw hexadecimal representation as
> float) is affected but in a floating number literal, any 0[a-zA-Z]:1234
> turns to a 16-bit word 0x1234, reinterpreted as a floating point number
> (and the second character is just ignored and the length is checked
> against another parameter).

I'm actually questioning that overly lax check; IOW I wonder whether it
shouldn't consult FLT_CHARS[].

Jan

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Tsukasa OI]

On 2023/08/03 17:00, Jan Beulich via Binutils wrote:
> On 03.08.2023 09:51, Tsukasa OI wrote:
>> On 2023/08/03 16:17, Tsukasa OI via Binutils wrote:
>>>
>>>
>>> On 2023/08/03 15:47, Jan Beulich wrote:
>>>> On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
>>>>> +++ b/gas/config/tc-riscv.c
>>>>> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>>>>>  
>>>>>  /* Chars that mean this number is a floating point constant.
>>>>>     As in 0f12.456 or 0d1.2345e12.  */
>>>>> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
>>>>> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
>>>>
>>>> I realize Arm64 also has it this way (x86 doesn't), but are you sure
>>>> about only adding 'b' and not also 'B'? Aiui this introduces a needless
>>>> special case of case sensitivity.
>>>
>>> I'm not sure (the only reason I did so is because what I saw is AArch64
>>> code).  So, I'll investigate whether introducing additional character
>>> will benefit (I think there's not so many cases but there might be at
>>> least one).
>>
>> I checked the code and actually, no code is affected by lacking 'B'.  I
>> first thought something like 0B:1234 (raw hexadecimal representation as
>> float) is affected but in a floating number literal, any 0[a-zA-Z]:1234
>> turns to a 16-bit word 0x1234, reinterpreted as a floating point number
>> (and the second character is just ignored and the length is checked
>> against another parameter).
> 
> I'm actually questioning that overly lax check; IOW I wonder whether it
> shouldn't consult FLT_CHARS[].
> 
> Jan
> 

Hmm, I'm tempted to say "don't ask me".  I mean, that overly lax check
is in the portable portion of GAS and not RISC-V-specific.  I will start
digging if I'm interested... but currently... I'm not quite sure.

Regards,
Tsukasa

Re: [REVIEW ONLY 4/4] RISC-V: Tentative ".bfloat16" assembly support

[Jan Beulich]

On 03.08.2023 10:21, Tsukasa OI wrote:
> On 2023/08/03 17:00, Jan Beulich via Binutils wrote:
>> On 03.08.2023 09:51, Tsukasa OI wrote:
>>> On 2023/08/03 16:17, Tsukasa OI via Binutils wrote:
>>>>
>>>>
>>>> On 2023/08/03 15:47, Jan Beulich wrote:
>>>>> On 03.08.2023 02:04, Tsukasa OI via Binutils wrote:> --- a/gas/config/tc-riscv.c
>>>>>> +++ b/gas/config/tc-riscv.c
>>>>>> @@ -437,7 +437,7 @@ const char EXP_CHARS[] = "eE";
>>>>>>  
>>>>>>  /* Chars that mean this number is a floating point constant.
>>>>>>     As in 0f12.456 or 0d1.2345e12.  */
>>>>>> -const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
>>>>>> +const char FLT_CHARS[] = "rRsSfFdDxXpPhHb";
>>>>>
>>>>> I realize Arm64 also has it this way (x86 doesn't), but are you sure
>>>>> about only adding 'b' and not also 'B'? Aiui this introduces a needless
>>>>> special case of case sensitivity.
>>>>
>>>> I'm not sure (the only reason I did so is because what I saw is AArch64
>>>> code).  So, I'll investigate whether introducing additional character
>>>> will benefit (I think there's not so many cases but there might be at
>>>> least one).
>>>
>>> I checked the code and actually, no code is affected by lacking 'B'.  I
>>> first thought something like 0B:1234 (raw hexadecimal representation as
>>> float) is affected but in a floating number literal, any 0[a-zA-Z]:1234
>>> turns to a 16-bit word 0x1234, reinterpreted as a floating point number
>>> (and the second character is just ignored and the length is checked
>>> against another parameter).
>>
>> I'm actually questioning that overly lax check; IOW I wonder whether it
>> shouldn't consult FLT_CHARS[].
> 
> Hmm, I'm tempted to say "don't ask me".  I mean, that overly lax check
> is in the portable portion of GAS and not RISC-V-specific.

Of course. My remark went towards: Wouldn't it be better if targets weren't
dependent on that overlay lax check? (Interestingly Arm32, despite
supporting bfloat16, looks to have neither b nor B in it FLT_CHARS[], and
is - for now - still getting away with that.)

Jan