* [PATCH 0/2] x86: assembly dialect tidying
@ 2023-12-01 13:30 Jan Beulich
2023-12-01 13:31 ` [PATCH 1/2] x86: Intel syntax implies Intel mnemonics Jan Beulich
2023-12-01 13:31 ` [PATCH 2/2] x86: fold assembly dialect attributes Jan Beulich
0 siblings, 2 replies; 3+ messages in thread
From: Jan Beulich @ 2023-12-01 13:30 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
1: Intel syntax implies Intel mnemonics
2: fold assembly dialect attributes
Jan
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] x86: Intel syntax implies Intel mnemonics
2023-12-01 13:30 [PATCH 0/2] x86: assembly dialect tidying Jan Beulich
@ 2023-12-01 13:31 ` Jan Beulich
2023-12-01 13:31 ` [PATCH 2/2] x86: fold assembly dialect attributes Jan Beulich
1 sibling, 0 replies; 3+ messages in thread
From: Jan Beulich @ 2023-12-01 13:31 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
As noted in the context of d53e6b98a259 ("x86/Intel: correct disassembly
of fsub*/fdiv*") there's no such thing as Intel syntax without Intel
mnemonics. Enforce this on the assembler side, and disentangle command
line option handling on the disassembler side accordingly.
As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes
redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and
remove the then no longer accessible templates.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7052,13 +7052,14 @@ match_template (char mnem_suffix)
/* Check AT&T mnemonic. */
specific_error = progress (unsupported_with_intel_mnemonic);
- if (intel_mnemonic && t->opcode_modifier.attmnemonic)
+ if (!intel_syntax && intel_mnemonic && t->opcode_modifier.attmnemonic)
continue;
/* Check AT&T/Intel syntax. */
specific_error = progress (unsupported_syntax);
- if ((intel_syntax && t->opcode_modifier.attsyntax)
- || (!intel_syntax && t->opcode_modifier.intelsyntax))
+ if (intel_syntax
+ ? t->opcode_modifier.attsyntax || t->opcode_modifier.attmnemonic
+ : t->opcode_modifier.intelsyntax)
continue;
/* Check Intel64/AMD64 ISA. */
@@ -15221,7 +15222,7 @@ md_show_usage (FILE *stream)
else
fprintf (stream, _("(default: intel)\n"));
fprintf (stream, _("\
- use AT&T/Intel mnemonic\n"));
+ use AT&T/Intel mnemonic (AT&T syntax only)\n"));
fprintf (stream, _("\
-msyntax=[att|intel] (default: att)\n\
use AT&T/Intel syntax\n"));
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -824,7 +824,9 @@ i386_intel_operand (char *operand_string
unsigned int op = t->operands - 1 - this_operand;
/* Easy checks to skip templates which won't match anyway. */
- if (this_operand >= t->operands || t->opcode_modifier.attsyntax)
+ if (this_operand >= t->operands
+ || t->opcode_modifier.attsyntax
+ || t->opcode_modifier.attmnemonic)
continue;
switch (suffix)
--- a/gas/testsuite/gas/i386/compat-intel.d
+++ b/gas/testsuite/gas/i386/compat-intel.d
@@ -1,4 +1,4 @@
-#as: -mmnemonic=att
+#as: -mmnemonic=intel
#objdump: -d -Mintel-mnemonic
#name: i386 float Intel mnemonic
#source: compat.s
@@ -8,24 +8,24 @@
Disassembly of section .text:
0+ <.text>:
-[ ]*[a-f0-9]+: dc e3 fsubr st\(3\),st
-[ ]*[a-f0-9]+: d8 e3 fsub st,st\(3\)
-[ ]*[a-f0-9]+: de e1 fsubrp st\(1\),st
-[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
-[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
-[ ]*[a-f0-9]+: dc eb fsub st\(3\),st
-[ ]*[a-f0-9]+: d8 eb fsubr st,st\(3\)
-[ ]*[a-f0-9]+: de e9 fsubp st\(1\),st
-[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
-[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
-[ ]*[a-f0-9]+: dc f3 fdivr st\(3\),st
-[ ]*[a-f0-9]+: d8 f3 fdiv st,st\(3\)
-[ ]*[a-f0-9]+: de f1 fdivrp st\(1\),st
-[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
-[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
-[ ]*[a-f0-9]+: dc fb fdiv st\(3\),st
-[ ]*[a-f0-9]+: d8 fb fdivr st,st\(3\)
-[ ]*[a-f0-9]+: de f9 fdivp st\(1\),st
-[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
-[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
+[ ]*[a-f0-9]+: dc eb fsub %st,%st\(3\)
+[ ]*[a-f0-9]+: d8 e3 fsub %st\(3\),%st
+[ ]*[a-f0-9]+: de e9 fsubp %st,%st\(1\)
+[ ]*[a-f0-9]+: de eb fsubp %st,%st\(3\)
+[ ]*[a-f0-9]+: de eb fsubp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc e3 fsubr %st,%st\(3\)
+[ ]*[a-f0-9]+: d8 eb fsubr %st\(3\),%st
+[ ]*[a-f0-9]+: de e1 fsubrp %st,%st\(1\)
+[ ]*[a-f0-9]+: de e3 fsubrp %st,%st\(3\)
+[ ]*[a-f0-9]+: de e3 fsubrp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc fb fdiv %st,%st\(3\)
+[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
+[ ]*[a-f0-9]+: de f9 fdivp %st,%st\(1\)
+[ ]*[a-f0-9]+: de fb fdivp %st,%st\(3\)
+[ ]*[a-f0-9]+: de fb fdivp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc f3 fdivr %st,%st\(3\)
+[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
+[ ]*[a-f0-9]+: de f1 fdivrp %st,%st\(1\)
+[ ]*[a-f0-9]+: de f3 fdivrp %st,%st\(3\)
+[ ]*[a-f0-9]+: de f3 fdivrp %st,%st\(3\)
#pass
--- a/gas/testsuite/gas/i386/compat-intel2.d
+++ b/gas/testsuite/gas/i386/compat-intel2.d
@@ -1,5 +1,5 @@
#as: -mmnemonic=intel
-#objdump: -d -Mintel-mnemonic
+#objdump: -d -Mintel
#name: i386 float Intel mnemonic (2)
#source: compat.s
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -1,7 +1,6 @@
#as: -J
#objdump: -dw
#name: i386 intel (AT&T disassembly)
-#warning_output: intel.e
.*: +file format .*
@@ -634,7 +633,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: b3 47 [ ]*mov \$0x47,%bl
[ ]*[a-f0-9]+: 0f ad d0 [ ]*shrd %cl,%edx,%eax
[ ]*[a-f0-9]+: 0f a5 d0 [ ]*shld %cl,%edx,%eax
-[ ]*[a-f0-9]+: de c1 faddp %st,%st\(1\)
[ ]*[a-f0-9]+: d8 c3 fadd %st\(3\),%st
[ ]*[a-f0-9]+: d8 c3 fadd %st\(3\),%st
[ ]*[a-f0-9]+: dc c3 fadd %st,%st\(3\)
@@ -643,7 +641,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de c1 faddp %st,%st\(1\)
[ ]*[a-f0-9]+: de c3 faddp %st,%st\(3\)
[ ]*[a-f0-9]+: de c3 faddp %st,%st\(3\)
-[ ]*[a-f0-9]+: de f9 fdivrp %st,%st\(1\)
[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
[ ]*[a-f0-9]+: dc fb fdivr %st,%st\(3\)
@@ -653,7 +650,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
-[ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
[ ]*[a-f0-9]+: dc f3 fdiv %st,%st\(3\)
@@ -663,7 +659,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
-[ ]*[a-f0-9]+: de c9 fmulp %st,%st\(1\)
[ ]*[a-f0-9]+: d8 cb fmul %st\(3\),%st
[ ]*[a-f0-9]+: d8 cb fmul %st\(3\),%st
[ ]*[a-f0-9]+: dc cb fmul %st,%st\(3\)
@@ -672,8 +667,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de c9 fmulp %st,%st\(1\)
[ ]*[a-f0-9]+: de cb fmulp %st,%st\(3\)
[ ]*[a-f0-9]+: de cb fmulp %st,%st\(3\)
-[ ]*[a-f0-9]+: de e9 fsubrp %st,%st\(1\)
-[ ]*[a-f0-9]+: de e1 fsubp %st,%st\(1\)
[ ]*[a-f0-9]+: d8 e3 fsub %st\(3\),%st
[ ]*[a-f0-9]+: d8 e3 fsub %st\(3\),%st
[ ]*[a-f0-9]+: dc eb fsubr %st,%st\(3\)
--- a/gas/testsuite/gas/i386/intel.e
+++ /dev/null
@@ -1,7 +0,0 @@
-.*: Assembler messages:
-.*:635: Warning: translating to `faddp'
-.*:644: Warning: translating to `fdivp'
-.*:654: Warning: translating to `fdivrp'
-.*:664: Warning: translating to `fmulp'
-.*:673: Warning: translating to `fsubp'
-.*:674: Warning: translating to `fsubrp'
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -632,7 +632,6 @@ rot5:
shrd eax, edx, cl
shld eax, edx, cl
-fadd
fadd st(3)
fadd st,st(3)
fadd st(3),st
@@ -641,7 +640,6 @@ fadd QWORD PTR [ebx]
faddp
faddp st(3)
faddp st(3),st
-fdiv
fdiv st(3)
fdiv st,st(3)
fdiv st(3),st
@@ -651,7 +649,6 @@ fdivp
fdivp st(3)
fdivp st(3),st
fdiv st,st(3)
-fdivr
fdivr st(3)
fdivr st,st(3)
fdivr st(3),st
@@ -661,7 +658,6 @@ fdivrp
fdivrp st(3)
fdivrp st(3),st
fdivr st,st(3)
-fmul
fmul st(3)
fmul st,st(3)
fmul st(3),st
@@ -670,8 +666,6 @@ fmul QWORD PTR [ebx]
fmulp
fmulp st(3)
fmulp st(3),st
-fsub
-fsubr
fsub st(3)
fsub st,st(3)
fsub st(3),st
--- a/gas/testsuite/gas/i386/intel-intel.d
+++ b/gas/testsuite/gas/i386/intel-intel.d
@@ -2,7 +2,6 @@
#objdump: -dwMintel
#name: i386 intel
#source: intel.s
-#warning_output: intel.e
.*: +file format .*
@@ -635,7 +634,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: b3 47 + mov bl,0x47
[ ]*[a-f0-9]+: 0f ad d0 + shrd eax,edx,cl
[ ]*[a-f0-9]+: 0f a5 d0 + shld eax,edx,cl
-[ ]*[a-f0-9]+: de c1 + faddp st\(1\),st
[ ]*[a-f0-9]+: d8 c3 + fadd st,st\(3\)
[ ]*[a-f0-9]+: d8 c3 + fadd st,st\(3\)
[ ]*[a-f0-9]+: dc c3 + fadd st\(3\),st
@@ -644,7 +642,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de c1 + faddp st\(1\),st
[ ]*[a-f0-9]+: de c3 + faddp st\(3\),st
[ ]*[a-f0-9]+: de c3 + faddp st\(3\),st
-[ ]*[a-f0-9]+: de f9 + fdivp st\(1\),st
[ ]*[a-f0-9]+: d8 f3 + fdiv st,st\(3\)
[ ]*[a-f0-9]+: d8 f3 + fdiv st,st\(3\)
[ ]*[a-f0-9]+: dc fb + fdiv st\(3\),st
@@ -654,7 +651,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de fb + fdivp st\(3\),st
[ ]*[a-f0-9]+: de fb + fdivp st\(3\),st
[ ]*[a-f0-9]+: d8 f3 + fdiv st,st\(3\)
-[ ]*[a-f0-9]+: de f1 + fdivrp st\(1\),st
[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
[ ]*[a-f0-9]+: dc f3 + fdivr st\(3\),st
@@ -664,7 +660,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de f3 + fdivrp st\(3\),st
[ ]*[a-f0-9]+: de f3 + fdivrp st\(3\),st
[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
-[ ]*[a-f0-9]+: de c9 + fmulp st\(1\),st
[ ]*[a-f0-9]+: d8 cb + fmul st,st\(3\)
[ ]*[a-f0-9]+: d8 cb + fmul st,st\(3\)
[ ]*[a-f0-9]+: dc cb + fmul st\(3\),st
@@ -673,8 +668,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de c9 + fmulp st\(1\),st
[ ]*[a-f0-9]+: de cb + fmulp st\(3\),st
[ ]*[a-f0-9]+: de cb + fmulp st\(3\),st
-[ ]*[a-f0-9]+: de e9 + fsubp st\(1\),st
-[ ]*[a-f0-9]+: de e1 + fsubrp st\(1\),st
[ ]*[a-f0-9]+: d8 e3 + fsub st,st\(3\)
[ ]*[a-f0-9]+: d8 e3 + fsub st,st\(3\)
[ ]*[a-f0-9]+: dc eb + fsub st\(3\),st
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -8571,10 +8571,10 @@ with the -M switch (multiple options sho
fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
- fprintf (stream, _(" att-mnemonic\n"
- " Display instruction in AT&T mnemonic\n"));
- fprintf (stream, _(" intel-mnemonic\n"
- " Display instruction in Intel mnemonic\n"));
+ fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n"
+ " Display instruction with AT&T mnemonic\n"));
+ fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n"
+ " Display instruction with Intel mnemonic\n"));
fprintf (stream, _(" addr64 Assume 64bit address size\n"));
fprintf (stream, _(" addr32 Assume 32bit address size\n"));
fprintf (stream, _(" addr16 Assume 16bit address size\n"));
@@ -9241,9 +9241,10 @@ print_insn (bfd_vma pc, disassemble_info
}
else if (startswith (p, "intel"))
{
- ins.intel_syntax = 1;
if (startswith (p + 5, "-mnemonic"))
ins.intel_mnemonic = true;
+ else
+ ins.intel_syntax = 1;
}
else if (startswith (p, "att"))
{
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -704,14 +704,13 @@ faddp, 0xdec1, FP, NoSuf, {}
fsub, 0xd8/4, FP, Modrm|NoSuf, { FloatReg }
fsub, 0xd8/4, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc }
// alias for fsubp
-fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsub, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {}
+fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {}
fsub, 0xd8/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
fisub, 0xde/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubp, 0xdee1, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg }
+fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg }
+fsubp, 0xdee1, FP, NoSuf|ATTMnemonic, {}
fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatAcc, FloatReg }
fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatReg }
fsubp, 0xdee9, FP, NoSuf, {}
@@ -720,14 +719,13 @@ fsubp, 0xdee9, FP, NoSuf, {}
fsubr, 0xd8/5, FP, Modrm|NoSuf, { FloatReg }
fsubr, 0xd8/5, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc }
// alias for fsubrp
-fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsubr, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {}
+fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {}
fsubr, 0xd8/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
fisubr, 0xde/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg }
+fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg }
+fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic, {}
fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatAcc, FloatReg }
fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatReg }
fsubrp, 0xdee1, FP, NoSuf, {}
@@ -749,14 +747,13 @@ fmulp, 0xdec9, FP, NoSuf, {}
fdiv, 0xd8/6, FP, Modrm|NoSuf, { FloatReg }
fdiv, 0xd8/6, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc }
// alias for fdivp
-fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdiv, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {}
+fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {}
fdiv, 0xd8/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
fidiv, 0xde/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivp, 0xdef1, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg }
+fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg }
+fdivp, 0xdef1, FP, NoSuf|ATTMnemonic, {}
fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatAcc, FloatReg }
fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatReg }
fdivp, 0xdef9, FP, NoSuf, {}
@@ -765,14 +762,13 @@ fdivp, 0xdef9, FP, NoSuf, {}
fdivr, 0xd8/7, FP, Modrm|NoSuf, { FloatReg }
fdivr, 0xd8/7, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc }
// alias for fdivrp
-fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdivr, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {}
+fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {}
fdivr, 0xd8/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
fidivr, 0xde/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg }
+fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg }
+fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic, {}
fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatAcc, FloatReg }
fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatReg }
fdivrp, 0xdef1, FP, NoSuf, {}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/2] x86: fold assembly dialect attributes
2023-12-01 13:30 [PATCH 0/2] x86: assembly dialect tidying Jan Beulich
2023-12-01 13:31 ` [PATCH 1/2] x86: Intel syntax implies Intel mnemonics Jan Beulich
@ 2023-12-01 13:31 ` Jan Beulich
1 sibling, 0 replies; 3+ messages in thread
From: Jan Beulich @ 2023-12-01 13:31 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
Now that ATTSyntax and ATTMnemonic aren't use in combination anymore,
fold them and IntelSyntax into a single, enum-like attribute. Note that
this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's
not for long, seeing in-flight additions for APX).
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7052,14 +7052,15 @@ match_template (char mnem_suffix)
/* Check AT&T mnemonic. */
specific_error = progress (unsupported_with_intel_mnemonic);
- if (!intel_syntax && intel_mnemonic && t->opcode_modifier.attmnemonic)
+ if (!intel_syntax && intel_mnemonic
+ && t->opcode_modifier.dialect == ATT_MNEMONIC)
continue;
/* Check AT&T/Intel syntax. */
specific_error = progress (unsupported_syntax);
if (intel_syntax
- ? t->opcode_modifier.attsyntax || t->opcode_modifier.attmnemonic
- : t->opcode_modifier.intelsyntax)
+ ? t->opcode_modifier.dialect >= ATT_SYNTAX
+ : t->opcode_modifier.dialect == INTEL_SYNTAX)
continue;
/* Check Intel64/AMD64 ISA. */
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -825,8 +825,7 @@ i386_intel_operand (char *operand_string
/* Easy checks to skip templates which won't match anyway. */
if (this_operand >= t->operands
- || t->opcode_modifier.attsyntax
- || t->opcode_modifier.attmnemonic)
+ || t->opcode_modifier.dialect >= ATT_SYNTAX)
continue;
switch (suffix)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -482,9 +482,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (Disp8MemShift),
BITFIELD (Vsz),
BITFIELD (Optimize),
- BITFIELD (ATTMnemonic),
- BITFIELD (ATTSyntax),
- BITFIELD (IntelSyntax),
+ BITFIELD (Dialect),
BITFIELD (ISA64),
};
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -729,12 +729,12 @@ enum
/* Support encoding optimization. */
Optimize,
- /* AT&T mnemonic. */
- ATTMnemonic,
- /* AT&T syntax. */
- ATTSyntax,
- /* Intel syntax. */
- IntelSyntax,
+ /* Language dialect. NOTE: Order matters! */
+#define INTEL_SYNTAX 1
+#define ATT_SYNTAX 2
+#define ATT_MNEMONIC 3
+ Dialect,
+
/* ISA64: Don't change the order without other code adjustments.
0: Common to AMD64 and Intel64.
1: AMD64.
@@ -788,9 +788,7 @@ typedef struct i386_opcode_modifier
unsigned int disp8memshift:3;
unsigned int vsz:3;
unsigned int optimize:1;
- unsigned int attmnemonic:1;
- unsigned int attsyntax:1;
- unsigned int intelsyntax:1;
+ unsigned int dialect:2;
unsigned int isa64:2;
} i386_opcode_modifier;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -86,6 +86,10 @@
#define SwapSources OperandConstraint=SWAP_SOURCES
#define Ugh OperandConstraint=UGH
+#define ATTSyntax Dialect=ATT_SYNTAX
+#define ATTMnemonic Dialect=ATT_MNEMONIC
+#define IntelSyntax Dialect=INTEL_SYNTAX
+
#define IgnoreSize MnemonicSize=IGNORESIZE
#define DefaultSize MnemonicSize=DEFAULTSIZE
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-12-01 13:31 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-01 13:30 [PATCH 0/2] x86: assembly dialect tidying Jan Beulich
2023-12-01 13:31 ` [PATCH 1/2] x86: Intel syntax implies Intel mnemonics Jan Beulich
2023-12-01 13:31 ` [PATCH 2/2] x86: fold assembly dialect attributes Jan Beulich
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