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* [PATCH] x86: FMA insns aren't eligible to VEX2 encoding
@ 2024-01-05  9:05 Jan Beulich
  0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2024-01-05  9:05 UTC (permalink / raw)
  To: Binutils; +Cc: H.J. Lu

PR gas/31178

In da0784f961d8 ("x86: fold FMA VEX and EVEX templates") I overlooked
that C aliases StaticRounding, and hence build_vex_prefix() now needs to
be aware of that aliasing. Disambiguation is easy, as StaticRounding is
only ever used together with SAE (hence why the overlaying works in the
first place).

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3802,6 +3802,8 @@ build_vex_prefix (const insn_template *t
       && i.reg_operands == i.operands - i.imm_operands
       && i.tm.opcode_modifier.vex
       && i.tm.opcode_modifier.commutative
+      /* .commutative aliases .staticrounding; disambiguate.  */
+      && !i.tm.opcode_modifier.sae
       && (i.tm.opcode_modifier.sse2avx
 	  || (optimize > 1 && !i.no_optimize))
       && i.rex == REX_B
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -222,4 +222,5 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 .*	pxor   %xmm12,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
 #pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.s
@@ -248,3 +248,6 @@ _start:
 	pcmpgtq		%xmm12, %xmm12
 	vpcmpgtq	%xmm2, %xmm2, %xmm8
 	vpcmpgtq	%ymm12, %ymm12, %ymm1
+
+	# PR gas/31178
+	vfnmadd231sd	%xmm9, %xmm2, %xmm0
--- a/gas/testsuite/gas/i386/x86-64-optimize-2a.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2a.d
@@ -223,4 +223,5 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 .*	pxor   %xmm12,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
 #pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-2b.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2b.d
@@ -222,4 +222,5 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 .*	pxor   %xmm12,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
 #pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-2c.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2c.d
@@ -223,4 +223,5 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 .*	vpxor  %xmm0,%xmm0,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
 #pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-5.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -222,6 +222,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 .*	pxor   %xmm12,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
  +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 7d 28 6f d1    	vmovdqa32 %ymm1,%ymm2
--- a/gas/testsuite/gas/i386/x86-64-optimize-6.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -222,6 +222,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 .*	pxor   %xmm12,%xmm12
  +[a-f0-9]+:	c5 .*	vpxor  %xmm2,%xmm2,%xmm8
  +[a-f0-9]+:	c5 .*	vpxor  %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+:	c4 .*	vfnmadd231sd %xmm9,%xmm2,%xmm0
  +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 7d 28 6f d1    	vmovdqa32 %ymm1,%ymm2

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2024-01-05  9:05 [PATCH] x86: FMA insns aren't eligible to VEX2 encoding Jan Beulich

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