* [PATCH 1/3] CSKY: Refine literals pool dump process and float register parser.
@ 2020-09-02 6:04 Cooper Qu
2020-09-02 6:05 ` [PATCH 2/3] CSKY: Fix Encode of mulsws Cooper Qu
2020-09-02 6:06 ` [PATCH 3/3] CSKY: Add CPU CK803r3 Cooper Qu
0 siblings, 2 replies; 4+ messages in thread
From: Cooper Qu @ 2020-09-02 6:04 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
gas/
* config/tc-csky.c (struct literal): New member bignum.
(dump_literals): Handle big constant.
(enter_literal): Likewise.
(parse_type_freg): Handle vector register.
---
gas/ChangeLog | 7 ++++++
gas/config/tc-csky.c | 54 +++++++++++++++++++++++++++++++++++++++++---
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 24320b3523e..0e2434f9862 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (struct literal): New member bignum.
+ (dump_literals): Handle big constant.
+ (enter_literal): Likewise.
+ (parse_type_freg): Handle vector register.
+
2020-09-01 H.J. Lu <hongjiu.lu@intel.com>
* doc/as.texi: Document the .tls_common directive.
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 01f1d516600..f85c44ddb05 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -302,6 +302,7 @@ struct literal
struct tls_addend tls_addend;
unsigned char isdouble;
uint64_t dbnum;
+ LITTLENUM_TYPE bignum[SIZE_OF_LARGE_NUMBER + 6];
};
static void csky_idly (void);
@@ -1660,7 +1661,7 @@ dump_literals (int isforce)
colon (S_GET_NAME (poolsym));
- for (i = 0, p = litpool; i < poolsize; i += (p->isdouble ? 2 : 1), p++)
+ for (i = 0, p = litpool; i < poolsize; p++)
{
insn_reloc = p->r_type;
if (insn_reloc == BFD_RELOC_CKCORE_TLS_IE32
@@ -1684,8 +1685,18 @@ dump_literals (int isforce)
emit_expr (& p->e, 4);
}
}
+ else if (p->e.X_op == O_big)
+ {
+ memcpy (generic_bignum, p->bignum, sizeof (p->bignum));
+ emit_expr (& p->e, p->e.X_add_number * CHARS_PER_LITTLENUM);
+ }
else
emit_expr (& p->e, 4);
+
+ if (p->e.X_op == O_big)
+ i += ((p->e.X_add_number * CHARS_PER_LITTLENUM) >> 2);
+ else
+ i += (p->isdouble ? 2 : 1);
}
if (isforce && IS_CSKY_ARCH_V2 (mach_flag))
@@ -1739,7 +1750,7 @@ enter_literal (expressionS *e,
}
/* Search pool for value so we don't have duplicates. */
- for (p = litpool, i = 0; i < poolsize; i += (p->isdouble ? 2 : 1), p++)
+ for (p = litpool,i = 0; i < poolsize; p++)
{
if (e->X_op == p->e.X_op
&& e->X_add_symbol == p->e.X_add_symbol
@@ -1751,11 +1762,21 @@ enter_literal (expressionS *e,
&& insn_reloc != BFD_RELOC_CKCORE_TLS_LDM32
&& insn_reloc != BFD_RELOC_CKCORE_TLS_LDO32
&& insn_reloc != BFD_RELOC_CKCORE_TLS_IE32
- && insn_reloc != BFD_RELOC_CKCORE_TLS_LE32)
+ && insn_reloc != BFD_RELOC_CKCORE_TLS_LE32
+ && (e->X_op != O_big
+ || (memcmp (generic_bignum, p->bignum,
+ p->e.X_add_number * sizeof (LITTLENUM_TYPE)) == 0)))
{
p->refcnt ++;
return i;
}
+ if (p->e.X_op == O_big)
+ {
+ i += (p->e.X_add_number >> 1);
+ i += (p->e.X_add_number & 0x1);
+ }
+ else
+ i += (p->isdouble ? 2 : 1);
}
p->refcnt = 1;
p->ispcrel = ispcrel;
@@ -1764,6 +1785,8 @@ enter_literal (expressionS *e,
p->isdouble = isdouble;
if (isdouble)
p->dbnum = dbnum;
+ if (e->X_op == O_big)
+ memcpy (p->bignum, generic_bignum, sizeof (p->bignum));
if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32
|| insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32
@@ -1773,7 +1796,12 @@ enter_literal (expressionS *e,
p->tls_addend.offset = csky_insn.output - frag_now->fr_literal;
literal_insn_offset = p;
}
+ if (p->e.X_op == O_big) {
+ poolsize += (p->e.X_add_number >> 1);
+ poolsize += (p->e.X_add_number & 0x1);
+ } else
poolsize += (p->isdouble ? 2 : 1);
+
return i;
}
@@ -2956,6 +2984,26 @@ parse_type_freg (char** oper, int even)
SET_ERROR_STRING (ERROR_EXP_EVEN_FREG, NULL);
return FALSE;
}
+
+ if (IS_CSKY_V2 (mach_flag)
+ && (csky_insn.opcode->isa_flag32 & CSKY_ISA_VDSP_2)
+ && reg > 15)
+ {
+ if ((csky_insn.opcode->isa_flag32 & CSKY_ISA_VDSP_2))
+ {
+ SET_ERROR_INTEGER (ERROR_VREG_OVER_RANGE, reg);
+ }
+ else
+ {
+ SET_ERROR_INTEGER (ERROR_FREG_OVER_RANGE, reg);
+ }
+ return FALSE;
+ }
+ /* TODO: recognize vreg or freg. */
+ if (reg > 31)
+ {
+ SET_ERROR_INTEGER (ERROR_VREG_OVER_RANGE, reg);
+ }
csky_insn.val[csky_insn.idx++] = reg;
return TRUE;
}
--
2.26.2
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/3] CSKY: Fix Encode of mulsws.
2020-09-02 6:04 [PATCH 1/3] CSKY: Refine literals pool dump process and float register parser Cooper Qu
@ 2020-09-02 6:05 ` Cooper Qu
2020-09-02 6:06 ` [PATCH 3/3] CSKY: Add CPU CK803r3 Cooper Qu
1 sibling, 0 replies; 4+ messages in thread
From: Cooper Qu @ 2020-09-02 6:05 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
gas/
* testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
opcodes/
* csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
---
gas/ChangeLog | 4 ++++
gas/testsuite/gas/csky/cskyv2_dsp.d | 2 +-
opcodes/ChangeLog | 4 ++++
opcodes/csky-opc.h | 2 +-
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0e2434f9862..303a332a0a4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
+
2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
* config/tc-csky.c (struct literal): New member bignum.
diff --git a/gas/testsuite/gas/csky/cskyv2_dsp.d b/gas/testsuite/gas/csky/cskyv2_dsp.d
index 3bc52fee8c3..54845a9c32a 100644
--- a/gas/testsuite/gas/csky/cskyv2_dsp.d
+++ b/gas/testsuite/gas/csky/cskyv2_dsp.d
@@ -15,5 +15,5 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*c6689040\s*mulsha\s*r8,\s*r19
\s*[0-9a-f]*:\s*c4319080\s*mulshs\s*r17,\s*r1
\s*[0-9a-f]*:\s*c6ec9440\s*mulswa\s*r12,\s*r23
-\s*[0-9a-f]*:\s*c4a39480\s*mulsws\s*r3,\s*r5
+\s*[0-9a-f]*:\s*c4a39500\s*mulsws\s*r3,\s*r5
#...
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 719cf05a3ef..a4e95aea5e4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
+
2020-09-01 Alan Modra <amodra@gmail.com>
* mep-ibld.c: Regenerate.
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 0a0b138fac7..54203aaab7e 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -2634,7 +2634,7 @@ const struct csky_opcode csky_v2_opcodes[] =
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulsws",
- OPCODE_INFO2 (0xc4009480,
+ OPCODE_INFO2 (0xc4009500,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
--
2.26.2
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] CSKY: Add CPU CK803r3.
2020-09-02 6:04 [PATCH 1/3] CSKY: Refine literals pool dump process and float register parser Cooper Qu
2020-09-02 6:05 ` [PATCH 2/3] CSKY: Fix Encode of mulsws Cooper Qu
@ 2020-09-02 6:06 ` Cooper Qu
2020-09-02 6:25 ` Lifang Xia
1 sibling, 1 reply; 4+ messages in thread
From: Cooper Qu @ 2020-09-02 6:06 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
---
gas/ChangeLog | 6 ++++++
gas/config/tc-csky.c | 38 +++++++++++++++++++++-----------------
include/ChangeLog | 4 ++++
include/opcode/csky.h | 1 +
opcodes/ChangeLog | 5 +++++
opcodes/csky-opc.h | 4 ++--
6 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 303a332a0a4..167f357febb 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (csky_cpus): Add ck803r3.
+ (CSKY_ISA_803R3): Define.
+ (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
+
2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
* testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index f85c44ddb05..0ed39e46e73 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -620,8 +620,8 @@ const struct csky_cpu_info csky_cpus[] =
/* CK803 series. */
#define CSKY_ISA_803 (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP)
#define CSKY_ISA_803R1 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1)
-#define CSKY_ISA_803R2 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1 | CSKYV2_ISA_3E3R2)
#define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3)
+#define CSKY_ISA_EDSP (CSKYV2_ISA_3E3R3 | CSKY_ISA_DSP_ENHANCE)
{"ck803", CSKY_ARCH_803, CSKY_ISA_803 },
{"ck803h", CSKY_ARCH_803, CSKY_ISA_803 },
{"ck803t", CSKY_ARCH_803, CSKY_ISA_803 | CSKY_ISA_TRUST},
@@ -643,31 +643,35 @@ const struct csky_cpu_info csky_cpus[] =
{"ck803htr1", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST},
{"ck803fr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
{"ck803fhr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
- {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
- {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
- {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
- {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
- {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
- {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
+ {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
+ {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
+ {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+ {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+ {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
+ {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
{"ck803ftr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
- {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
- {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+ {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+ {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+#define CSKY_ISA_803R2 (CSKY_ISA_803R1 | CSKYV2_ISA_3E3R2)
{"ck803r2", CSKY_ARCH_803, CSKY_ISA_803R2},
{"ck803hr2", CSKY_ARCH_803, CSKY_ISA_803R2},
{"ck803tr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
{"ck803htr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
{"ck803fr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
{"ck803fhr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
- {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
- {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
- {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
- {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
- {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
- {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
+ {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
+ {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
+ {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+ {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
+ {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
+ {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
{"ck803ftr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
- {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
- {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+ {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+ {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
+
+#define CSKY_ISA_803R3 (CSKY_ISA_803R2 | CSKYV2_ISA_3E3R3)
+ {"ck803r3", CSKY_ARCH_803, CSKY_ISA_803R3},
{"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 },
{"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP},
diff --git a/include/ChangeLog b/include/ChangeLog
index 9daa866d725..c6f00b35d69 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
+
2020-08-31 Alan Modra <amodra@gmail.com>
PR 26493
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index 493e822a5a3..ab2b2109271 100644
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -31,6 +31,7 @@
#define CSKYV2_ISA_3E3R1 (1L << 6)
#define CSKYV2_ISA_3E3R2 (1L << 7)
#define CSKYV2_ISA_10E60 (1L << 8)
+#define CSKYV2_ISA_3E3R3 (1L << 9)
#define CSKY_ISA_TRUST (1L << 11)
#define CSKY_ISA_CACHE (1L << 12)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a4e95aea5e4..8481a13e08b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Move divul and divsl
+ to CSKYV2_ISA_3E3R3 instruction set.
+
2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 54203aaab7e..5e2f1a58695 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -5321,13 +5321,13 @@ const struct csky_opcode csky_v2_opcodes[] =
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKY_ISA_DSP_ENHANCE),
+ CSKYV2_ISA_3E3R3),
OP32 ("divsl",
OPCODE_INFO3 (0xf800e2e0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKY_ISA_DSP_ENHANCE),
+ CSKYV2_ISA_3E3R3),
OP32 ("mulaca.s8",
OPCODE_INFO3 (0xf800e4c0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
--
2.26.2
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] CSKY: Add CPU CK803r3.
2020-09-02 6:06 ` [PATCH 3/3] CSKY: Add CPU CK803r3 Cooper Qu
@ 2020-09-02 6:25 ` Lifang Xia
0 siblings, 0 replies; 4+ messages in thread
From: Lifang Xia @ 2020-09-02 6:25 UTC (permalink / raw)
To: Cooper Qu, binutils
all of the 3 patch are merged.
On 2020/9/2 14:06, Cooper Qu wrote:
> Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
> enabled by ck803r3, and it's still a part of enhance DSP instruction
> set.
>
> gas/
> * config/tc-csky.c (csky_cpus): Add ck803r3.
> (CSKY_ISA_803R3): Define.
> (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
>
> include/
> * opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
>
> opcodes/
> * csky-opc.h (csky_v2_opcodes): Move divul and divsl
> to CSKYV2_ISA_3E3R3 instruction set.
>
> ---
> gas/ChangeLog | 6 ++++++
> gas/config/tc-csky.c | 38 +++++++++++++++++++++-----------------
> include/ChangeLog | 4 ++++
> include/opcode/csky.h | 1 +
> opcodes/ChangeLog | 5 +++++
> opcodes/csky-opc.h | 4 ++--
> 6 files changed, 39 insertions(+), 19 deletions(-)
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index 303a332a0a4..167f357febb 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,9 @@
> +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * config/tc-csky.c (csky_cpus): Add ck803r3.
> + (CSKY_ISA_803R3): Define.
> + (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
> +
> 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
>
> * testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
> diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
> index f85c44ddb05..0ed39e46e73 100644
> --- a/gas/config/tc-csky.c
> +++ b/gas/config/tc-csky.c
> @@ -620,8 +620,8 @@ const struct csky_cpu_info csky_cpus[] =
> /* CK803 series. */
> #define CSKY_ISA_803 (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP)
> #define CSKY_ISA_803R1 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1)
> -#define CSKY_ISA_803R2 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1 | CSKYV2_ISA_3E3R2)
> #define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3)
> +#define CSKY_ISA_EDSP (CSKYV2_ISA_3E3R3 | CSKY_ISA_DSP_ENHANCE)
> {"ck803", CSKY_ARCH_803, CSKY_ISA_803 },
> {"ck803h", CSKY_ARCH_803, CSKY_ISA_803 },
> {"ck803t", CSKY_ARCH_803, CSKY_ISA_803 | CSKY_ISA_TRUST},
> @@ -643,31 +643,35 @@ const struct csky_cpu_info csky_cpus[] =
> {"ck803htr1", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST},
> {"ck803fr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
> {"ck803fhr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803},
> - {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
> - {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE},
> - {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> - {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> - {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> - {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> + {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
> + {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP},
> + {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
> + {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
> + {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
> + {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
> {"ck803ftr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> - {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> - {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
>
> +#define CSKY_ISA_803R2 (CSKY_ISA_803R1 | CSKYV2_ISA_3E3R2)
> {"ck803r2", CSKY_ARCH_803, CSKY_ISA_803R2},
> {"ck803hr2", CSKY_ARCH_803, CSKY_ISA_803R2},
> {"ck803tr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
> {"ck803htr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
> {"ck803fr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
> {"ck803fhr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
> - {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
> - {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
> - {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> - {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> - {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> - {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> + {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
> + {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP},
> + {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
> + {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_TRUST},
> + {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
> + {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803},
> {"ck803ftr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> - {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> - {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_EDSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> +
> +#define CSKY_ISA_803R3 (CSKY_ISA_803R2 | CSKYV2_ISA_3E3R3)
> + {"ck803r3", CSKY_ARCH_803, CSKY_ISA_803R3},
>
> {"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 },
> {"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP},
> diff --git a/include/ChangeLog b/include/ChangeLog
> index 9daa866d725..c6f00b35d69 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,3 +1,7 @@
> +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
> +
> 2020-08-31 Alan Modra <amodra@gmail.com>
>
> PR 26493
> diff --git a/include/opcode/csky.h b/include/opcode/csky.h
> index 493e822a5a3..ab2b2109271 100644
> --- a/include/opcode/csky.h
> +++ b/include/opcode/csky.h
> @@ -31,6 +31,7 @@
> #define CSKYV2_ISA_3E3R1 (1L << 6)
> #define CSKYV2_ISA_3E3R2 (1L << 7)
> #define CSKYV2_ISA_10E60 (1L << 8)
> +#define CSKYV2_ISA_3E3R3 (1L << 9)
>
> #define CSKY_ISA_TRUST (1L << 11)
> #define CSKY_ISA_CACHE (1L << 12)
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index a4e95aea5e4..8481a13e08b 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,3 +1,8 @@
> +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * csky-opc.h (csky_v2_opcodes): Move divul and divsl
> + to CSKYV2_ISA_3E3R3 instruction set.
> +
> 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
>
> * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
> diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
> index 54203aaab7e..5e2f1a58695 100644
> --- a/opcodes/csky-opc.h
> +++ b/opcodes/csky-opc.h
> @@ -5321,13 +5321,13 @@ const struct csky_opcode csky_v2_opcodes[] =
> (0_4, AREG, OPRND_SHIFT_0_BIT),
> (16_20, AREG, OPRND_SHIFT_0_BIT),
> (21_25, AREG, OPRND_SHIFT_0_BIT)),
> - CSKY_ISA_DSP_ENHANCE),
> + CSKYV2_ISA_3E3R3),
> OP32 ("divsl",
> OPCODE_INFO3 (0xf800e2e0,
> (0_4, AREG, OPRND_SHIFT_0_BIT),
> (16_20, AREG, OPRND_SHIFT_0_BIT),
> (21_25, AREG, OPRND_SHIFT_0_BIT)),
> - CSKY_ISA_DSP_ENHANCE),
> + CSKYV2_ISA_3E3R3),
> OP32 ("mulaca.s8",
> OPCODE_INFO3 (0xf800e4c0,
> (0_4, AREG, OPRND_SHIFT_0_BIT),
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-02 6:25 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-02 6:04 [PATCH 1/3] CSKY: Refine literals pool dump process and float register parser Cooper Qu
2020-09-02 6:05 ` [PATCH 2/3] CSKY: Fix Encode of mulsws Cooper Qu
2020-09-02 6:06 ` [PATCH 3/3] CSKY: Add CPU CK803r3 Cooper Qu
2020-09-02 6:25 ` Lifang Xia
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