From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 1/2] RISC-V: Make `zip'/`unzip' on Zbkb non-aliases
Date: Sat, 9 Jul 2022 12:50:14 +0900 [thread overview]
Message-ID: <f03aba326e9639bbed7df54156a73bdc81275023.1657338599.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1657338599.git.research_trasio@irq.a4lg.com>
`zip'/`unzip' are specialized forms of `shfli'/`unshfli' instructions
respectively. However, because both `shfli' and `unshfli' are not
ratified (in generalized forms), disassembling `zip'/`unzip' on
RV32_Zbkb with `-M no-aliases' option makes disassembly dumps with
`.4byte' (an unrecognized instruction), not `zip'/`unzip'.
This commit makes `zip'/`unzip' non-aliases until generalized forms of
`shfli' and `unshfli' are ratified.
gas/ChangeLog:
* testsuite/gas/riscv/zbkb-32.d: Make sure that all instructions
in RV32_Zbkb are non-aliases and disassembled correctly.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Make `zip'/`unzip' instructions
on RV32_Zbkb non-aliases to fix a disassembler issue.
---
gas/testsuite/gas/riscv/zbkb-32.d | 2 +-
opcodes/riscv-opc.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
index c2718a0965a..c3fd09f9274 100644
--- a/gas/testsuite/gas/riscv/zbkb-32.d
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -1,6 +1,6 @@
#as: -march=rv32i_zbkb
#source: zbkb-32.s
-#objdump: -d
+#objdump: -d -M no-aliases
.*:[ ]+file format .*
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa930..6c5b2eaf524 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -942,8 +942,8 @@ const struct riscv_opcode riscv_opcodes[] =
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
-{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
--
2.34.1
next prev parent reply other threads:[~2022-07-09 3:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 3:50 [PATCH 0/2] RISC-V: Make some instruction non-aliases to fix a disassembler issue Tsukasa OI
2022-07-09 3:50 ` Tsukasa OI [this message]
2022-07-09 3:50 ` [PATCH 2/2] RISC-V: Make `fence.tso' a non-alias Tsukasa OI
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