* [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1
2024-02-29 17:33 [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Andrew Carlotti
@ 2024-02-29 17:35 ` Andrew Carlotti
2024-03-01 17:11 ` Richard Earnshaw (lists)
2024-02-29 17:36 ` [PATCH 2/3] [2.42 Backport] aarch64: Remove SVE2p1 Andrew Carlotti
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Andrew Carlotti @ 2024-02-29 17:35 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, Nick Clifton, Jan Beulich
Support for this extension is almost entirely missing in the 2.42
branch. This patch removes the flags and documentation, to avoid
any further suggestion that this support exists.
diff --git a/gas/NEWS b/gas/NEWS
index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -6,8 +6,6 @@ Changes in 2.42:
* Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
-* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
-
* Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
(B16B16).
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"d128", AARCH64_FEATURE (D128),
AARCH64_FEATURE (LSE128)},
{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
- {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -263,8 +263,6 @@ automatically cause those extensions to be disabled.
@tab Enable SME I16I64 Extension.
@item @code{sme2} @tab @code{sme}
@tab Enable SME2.
-@item @code{sme2p1} @tab @code{sme2}
- @tab Enable SME2.1.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{sve} @tab @code{fcma}
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
deleted file mode 100644
index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sme2p1-1.d
+++ /dev/null
@@ -1,42 +0,0 @@
-#name: Test of SME2.1 movaz instructions.
-#as: -march=armv9.4-a+sme2p1
-#objdump: -dr
-
-[^:]+: file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
-.*: c046c260 movaz {z0.h-z1.h}, za0v.h \[w14, 6:7\]
-.*: c086c220 movaz {z0.s-z1.s}, za0v.s \[w14, 2:3\]
-.*: c0c6c200 movaz {z0.d-z1.d}, za0v.d \[w14, 0:1\]
-.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
-.*: c0462260 movaz {z0.h-z1.h}, za0h.h \[w13, 6:7\]
-.*: c0864220 movaz {z0.s-z1.s}, za0h.s \[w14, 2:3\]
-.*: c0c66200 movaz {z0.d-z1.d}, za0h.d \[w15, 0:1\]
-.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
-.*: c046c2e0 movaz {z0.h-z1.h}, za1v.h \[w14, 6:7\]
-.*: c086c2a0 movaz {z0.s-z1.s}, za2v.s \[w14, 2:3\]
-.*: c0c6c260 movaz {z0.d-z1.d}, za3v.d \[w14, 0:1\]
-.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
-.*: c04622e0 movaz {z0.h-z1.h}, za1h.h \[w13, 6:7\]
-.*: c08642a0 movaz {z0.s-z1.s}, za2h.s \[w14, 2:3\]
-.*: c0c66260 movaz {z0.d-z1.d}, za3h.d \[w15, 0:1\]
-.*: c006c660 movaz {z0.b-z3.b}, za0v.b \[w14, 12:15\]
-.*: c046c620 movaz {z0.h-z3.h}, za0v.h \[w14, 4:7\]
-.*: c086c600 movaz {z0.s-z3.s}, za0v.s \[w14, 0:3\]
-.*: c0c6c600 movaz {z0.d-z3.d}, za0v.d \[w14, 0:3\]
-.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
-.*: c0462620 movaz {z0.h-z3.h}, za0h.h \[w13, 4:7\]
-.*: c0864600 movaz {z0.s-z3.s}, za0h.s \[w14, 0:3\]
-.*: c0c66600 movaz {z0.d-z3.d}, za0h.d \[w15, 0:3\]
-.*: c006c640 movaz {z0.b-z3.b}, za0v.b \[w14, 8:11\]
-.*: c046c660 movaz {z0.h-z3.h}, za1v.h \[w14, 4:7\]
-.*: c086c640 movaz {z0.s-z3.s}, za2v.s \[w14, 0:3\]
-.*: c0c6c660 movaz {z0.d-z3.d}, za3v.d \[w14, 0:3\]
-.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
-.*: c0462660 movaz {z0.h-z3.h}, za1h.h \[w13, 4:7\]
-.*: c0864640 movaz {z0.s-z3.s}, za2h.s \[w14, 0:3\]
-.*: c0c66660 movaz {z0.d-z3.d}, za3h.d \[w15, 0:3\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
deleted file mode 100644
index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sme2p1-1.s
+++ /dev/null
@@ -1,39 +0,0 @@
- movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
- movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
- movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
- movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
-
- movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
- movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
- movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
- movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
-
- movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
- movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
- movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
- movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
-
- movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
- movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
- movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
- movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
-
- movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
- movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
- movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
- movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
-
- movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
- movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
- movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
- movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
-
- movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
- movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
- movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
- movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
-
- movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
- movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
- movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
- movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,8 +222,6 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SEBEP,
/* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
AARCH64_FEATURE_B16B16,
- /* SME2.1 instructions. */
- AARCH64_FEATURE_SME2p1,
/* SVE2.1 instructions. */
AARCH64_FEATURE_SVE2p1,
/* RCPC3 instructions. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
static const aarch64_feature_set aarch64_feature_b16b16 =
AARCH64_FEATURE (B16B16);
-static const aarch64_feature_set aarch64_feature_sme2p1 =
- AARCH64_FEATURE (SME2p1);
static const aarch64_feature_set aarch64_feature_sve2p1 =
AARCH64_FEATURE (SVE2p1);
static const aarch64_feature_set aarch64_feature_rcpc3 =
@@ -2713,7 +2711,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
#define B16B16 &aarch64_feature_b16b16
-#define SME2p1 &aarch64_feature_sme2p1
#define SVE2p1 &aarch64_feature_sve2p1
#define RCPC3 &aarch64_feature_rcpc3
@@ -2782,9 +2779,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
-#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
- FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
@@ -6348,17 +6342,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-/* SME2.1 movaz instructions. */
- SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
- SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
- SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
- SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
-
- SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
- SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
- SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
- SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
-
/* SVE2p1 Instructions. */
SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1
2024-02-29 17:35 ` [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1 Andrew Carlotti
@ 2024-03-01 17:11 ` Richard Earnshaw (lists)
2024-03-01 17:33 ` Andrew Carlotti
0 siblings, 1 reply; 7+ messages in thread
From: Richard Earnshaw (lists) @ 2024-03-01 17:11 UTC (permalink / raw)
To: Andrew Carlotti, binutils; +Cc: Nick Clifton, Jan Beulich
On 29/02/2024 17:35, Andrew Carlotti wrote:
> Support for this extension is almost entirely missing in the 2.42
> branch. This patch removes the flags and documentation, to avoid
> any further suggestion that this support exists.
I'm uncertain whether or not to completely remove this code. Would it be better to just disable (comment out) the feature flag and then xfail the relevant tests?
Adding:
#xfail *-*-*
to the affected .d files would achieve the latter.
R.
>
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -6,8 +6,6 @@ Changes in 2.42:
>
> * Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
>
> -* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
> -
> * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
> (B16B16).
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"d128", AARCH64_FEATURE (D128),
> AARCH64_FEATURE (LSE128)},
> {"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
> - {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
> {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
> {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
> {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -263,8 +263,6 @@ automatically cause those extensions to be disabled.
> @tab Enable SME I16I64 Extension.
> @item @code{sme2} @tab @code{sme}
> @tab Enable SME2.
> -@item @code{sme2p1} @tab @code{sme2}
> - @tab Enable SME2.1.
> @item @code{ssbs} @tab
> @tab Enable Speculative Store Bypassing Safe state read and write.
> @item @code{sve} @tab @code{fcma}
> diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
> deleted file mode 100644
> index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
> --- a/gas/testsuite/gas/aarch64/sme2p1-1.d
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -#name: Test of SME2.1 movaz instructions.
> -#as: -march=armv9.4-a+sme2p1
> -#objdump: -dr
> -
> -[^:]+: file format .*
> -
> -
> -[^:]+:
> -
> -[^:]+:
> -.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
> -.*: c046c260 movaz {z0.h-z1.h}, za0v.h \[w14, 6:7\]
> -.*: c086c220 movaz {z0.s-z1.s}, za0v.s \[w14, 2:3\]
> -.*: c0c6c200 movaz {z0.d-z1.d}, za0v.d \[w14, 0:1\]
> -.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
> -.*: c0462260 movaz {z0.h-z1.h}, za0h.h \[w13, 6:7\]
> -.*: c0864220 movaz {z0.s-z1.s}, za0h.s \[w14, 2:3\]
> -.*: c0c66200 movaz {z0.d-z1.d}, za0h.d \[w15, 0:1\]
> -.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
> -.*: c046c2e0 movaz {z0.h-z1.h}, za1v.h \[w14, 6:7\]
> -.*: c086c2a0 movaz {z0.s-z1.s}, za2v.s \[w14, 2:3\]
> -.*: c0c6c260 movaz {z0.d-z1.d}, za3v.d \[w14, 0:1\]
> -.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
> -.*: c04622e0 movaz {z0.h-z1.h}, za1h.h \[w13, 6:7\]
> -.*: c08642a0 movaz {z0.s-z1.s}, za2h.s \[w14, 2:3\]
> -.*: c0c66260 movaz {z0.d-z1.d}, za3h.d \[w15, 0:1\]
> -.*: c006c660 movaz {z0.b-z3.b}, za0v.b \[w14, 12:15\]
> -.*: c046c620 movaz {z0.h-z3.h}, za0v.h \[w14, 4:7\]
> -.*: c086c600 movaz {z0.s-z3.s}, za0v.s \[w14, 0:3\]
> -.*: c0c6c600 movaz {z0.d-z3.d}, za0v.d \[w14, 0:3\]
> -.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
> -.*: c0462620 movaz {z0.h-z3.h}, za0h.h \[w13, 4:7\]
> -.*: c0864600 movaz {z0.s-z3.s}, za0h.s \[w14, 0:3\]
> -.*: c0c66600 movaz {z0.d-z3.d}, za0h.d \[w15, 0:3\]
> -.*: c006c640 movaz {z0.b-z3.b}, za0v.b \[w14, 8:11\]
> -.*: c046c660 movaz {z0.h-z3.h}, za1v.h \[w14, 4:7\]
> -.*: c086c640 movaz {z0.s-z3.s}, za2v.s \[w14, 0:3\]
> -.*: c0c6c660 movaz {z0.d-z3.d}, za3v.d \[w14, 0:3\]
> -.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
> -.*: c0462660 movaz {z0.h-z3.h}, za1h.h \[w13, 4:7\]
> -.*: c0864640 movaz {z0.s-z3.s}, za2h.s \[w14, 0:3\]
> -.*: c0c66660 movaz {z0.d-z3.d}, za3h.d \[w15, 0:3\]
> diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
> deleted file mode 100644
> index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
> --- a/gas/testsuite/gas/aarch64/sme2p1-1.s
> +++ /dev/null
> @@ -1,39 +0,0 @@
> - movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> - movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
> - movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
> - movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
> -
> - movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> - movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
> - movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
> - movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
> -
> - movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> - movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
> - movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
> - movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
> -
> - movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> - movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
> - movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
> - movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
> -
> - movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
> - movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
> - movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
> - movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
> -
> - movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> - movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
> - movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
> - movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
> -
> - movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
> - movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
> - movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
> - movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
> -
> - movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> - movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
> - movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
> - movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -222,8 +222,6 @@ enum aarch64_feature_bit {
> AARCH64_FEATURE_SEBEP,
> /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
> AARCH64_FEATURE_B16B16,
> - /* SME2.1 instructions. */
> - AARCH64_FEATURE_SME2p1,
> /* SVE2.1 instructions. */
> AARCH64_FEATURE_SVE2p1,
> /* RCPC3 instructions. */
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
> AARCH64_FEATURES (2, D128, THE);
> static const aarch64_feature_set aarch64_feature_b16b16 =
> AARCH64_FEATURE (B16B16);
> -static const aarch64_feature_set aarch64_feature_sme2p1 =
> - AARCH64_FEATURE (SME2p1);
> static const aarch64_feature_set aarch64_feature_sve2p1 =
> AARCH64_FEATURE (SVE2p1);
> static const aarch64_feature_set aarch64_feature_rcpc3 =
> @@ -2713,7 +2711,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> #define THE &aarch64_feature_the
> #define D128_THE &aarch64_feature_d128_the
> #define B16B16 &aarch64_feature_b16b16
> -#define SME2p1 &aarch64_feature_sme2p1
> #define SVE2p1 &aarch64_feature_sve2p1
> #define RCPC3 &aarch64_feature_rcpc3
>
> @@ -2782,9 +2779,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> -#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> - { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
> - FLAGS | F_STRICT, 0, TIED, NULL }
> #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
> { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
> @@ -6348,17 +6342,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
> B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
>
> -/* SME2.1 movaz instructions. */
> - SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
> -
> - SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
> - SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
> -
> /* SVE2p1 Instructions. */
> SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
> SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1
2024-03-01 17:11 ` Richard Earnshaw (lists)
@ 2024-03-01 17:33 ` Andrew Carlotti
0 siblings, 0 replies; 7+ messages in thread
From: Andrew Carlotti @ 2024-03-01 17:33 UTC (permalink / raw)
To: Richard Earnshaw (lists); +Cc: binutils, Nick Clifton, Jan Beulich
On Fri, Mar 01, 2024 at 05:11:39PM +0000, Richard Earnshaw (lists) wrote:
> On 29/02/2024 17:35, Andrew Carlotti wrote:
> > Support for this extension is almost entirely missing in the 2.42
> > branch. This patch removes the flags and documentation, to avoid
> > any further suggestion that this support exists.
>
> I'm uncertain whether or not to completely remove this code. Would it be better to just disable (comment out) the feature flag and then xfail the relevant tests?
>
> Adding:
>
> #xfail *-*-*
>
> to the affected .d files would achieve the latter.
>
> R.
That's what I was originally planning to do, but then I realised that there was
little point in keeping the rest of the code present if the instructions
couldn't be used. I'm also concerned about the possibility of incorrect
opcodes interfering with disassembly of instructions that aren't part of this
extension, although I think the only collision I'm aware of is between two
different instructions in +sve2p1.
> >
> >
> > diff --git a/gas/NEWS b/gas/NEWS
> > index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
> > --- a/gas/NEWS
> > +++ b/gas/NEWS
> > @@ -6,8 +6,6 @@ Changes in 2.42:
> >
> > * Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
> >
> > -* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
> > -
> > * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
> > (B16B16).
> >
> > diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> > index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
> > --- a/gas/config/tc-aarch64.c
> > +++ b/gas/config/tc-aarch64.c
> > @@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> > {"d128", AARCH64_FEATURE (D128),
> > AARCH64_FEATURE (LSE128)},
> > {"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
> > - {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
> > {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
> > {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
> > {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> > diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> > index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
> > --- a/gas/doc/c-aarch64.texi
> > +++ b/gas/doc/c-aarch64.texi
> > @@ -263,8 +263,6 @@ automatically cause those extensions to be disabled.
> > @tab Enable SME I16I64 Extension.
> > @item @code{sme2} @tab @code{sme}
> > @tab Enable SME2.
> > -@item @code{sme2p1} @tab @code{sme2}
> > - @tab Enable SME2.1.
> > @item @code{ssbs} @tab
> > @tab Enable Speculative Store Bypassing Safe state read and write.
> > @item @code{sve} @tab @code{fcma}
> > diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
> > deleted file mode 100644
> > index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
> > --- a/gas/testsuite/gas/aarch64/sme2p1-1.d
> > +++ /dev/null
> > @@ -1,42 +0,0 @@
> > -#name: Test of SME2.1 movaz instructions.
> > -#as: -march=armv9.4-a+sme2p1
> > -#objdump: -dr
> > -
> > -[^:]+: file format .*
> > -
> > -
> > -[^:]+:
> > -
> > -[^:]+:
> > -.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
> > -.*: c046c260 movaz {z0.h-z1.h}, za0v.h \[w14, 6:7\]
> > -.*: c086c220 movaz {z0.s-z1.s}, za0v.s \[w14, 2:3\]
> > -.*: c0c6c200 movaz {z0.d-z1.d}, za0v.d \[w14, 0:1\]
> > -.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
> > -.*: c0462260 movaz {z0.h-z1.h}, za0h.h \[w13, 6:7\]
> > -.*: c0864220 movaz {z0.s-z1.s}, za0h.s \[w14, 2:3\]
> > -.*: c0c66200 movaz {z0.d-z1.d}, za0h.d \[w15, 0:1\]
> > -.*: c006c260 movaz {z0.b-z1.b}, za0v.b \[w14, 6:7\]
> > -.*: c046c2e0 movaz {z0.h-z1.h}, za1v.h \[w14, 6:7\]
> > -.*: c086c2a0 movaz {z0.s-z1.s}, za2v.s \[w14, 2:3\]
> > -.*: c0c6c260 movaz {z0.d-z1.d}, za3v.d \[w14, 0:1\]
> > -.*: c00602e0 movaz {z0.b-z1.b}, za0h.b \[w12, 14:15\]
> > -.*: c04622e0 movaz {z0.h-z1.h}, za1h.h \[w13, 6:7\]
> > -.*: c08642a0 movaz {z0.s-z1.s}, za2h.s \[w14, 2:3\]
> > -.*: c0c66260 movaz {z0.d-z1.d}, za3h.d \[w15, 0:1\]
> > -.*: c006c660 movaz {z0.b-z3.b}, za0v.b \[w14, 12:15\]
> > -.*: c046c620 movaz {z0.h-z3.h}, za0v.h \[w14, 4:7\]
> > -.*: c086c600 movaz {z0.s-z3.s}, za0v.s \[w14, 0:3\]
> > -.*: c0c6c600 movaz {z0.d-z3.d}, za0v.d \[w14, 0:3\]
> > -.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
> > -.*: c0462620 movaz {z0.h-z3.h}, za0h.h \[w13, 4:7\]
> > -.*: c0864600 movaz {z0.s-z3.s}, za0h.s \[w14, 0:3\]
> > -.*: c0c66600 movaz {z0.d-z3.d}, za0h.d \[w15, 0:3\]
> > -.*: c006c640 movaz {z0.b-z3.b}, za0v.b \[w14, 8:11\]
> > -.*: c046c660 movaz {z0.h-z3.h}, za1v.h \[w14, 4:7\]
> > -.*: c086c640 movaz {z0.s-z3.s}, za2v.s \[w14, 0:3\]
> > -.*: c0c6c660 movaz {z0.d-z3.d}, za3v.d \[w14, 0:3\]
> > -.*: c0060660 movaz {z0.b-z3.b}, za0h.b \[w12, 12:15\]
> > -.*: c0462660 movaz {z0.h-z3.h}, za1h.h \[w13, 4:7\]
> > -.*: c0864640 movaz {z0.s-z3.s}, za2h.s \[w14, 0:3\]
> > -.*: c0c66660 movaz {z0.d-z3.d}, za3h.d \[w15, 0:3\]
> > diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
> > deleted file mode 100644
> > index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
> > --- a/gas/testsuite/gas/aarch64/sme2p1-1.s
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > - movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> > - movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
> > - movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
> > - movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
> > -
> > - movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> > - movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
> > - movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
> > - movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
> > -
> > - movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> > - movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
> > - movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
> > - movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
> > -
> > - movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> > - movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
> > - movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
> > - movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
> > -
> > - movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
> > - movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
> > - movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
> > - movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
> > -
> > - movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> > - movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
> > - movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
> > - movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
> > -
> > - movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
> > - movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
> > - movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
> > - movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
> > -
> > - movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> > - movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
> > - movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
> > - movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
> > diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> > index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
> > --- a/include/opcode/aarch64.h
> > +++ b/include/opcode/aarch64.h
> > @@ -222,8 +222,6 @@ enum aarch64_feature_bit {
> > AARCH64_FEATURE_SEBEP,
> > /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
> > AARCH64_FEATURE_B16B16,
> > - /* SME2.1 instructions. */
> > - AARCH64_FEATURE_SME2p1,
> > /* SVE2.1 instructions. */
> > AARCH64_FEATURE_SVE2p1,
> > /* RCPC3 instructions. */
> > diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> > index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
> > --- a/opcodes/aarch64-tbl.h
> > +++ b/opcodes/aarch64-tbl.h
> > @@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
> > AARCH64_FEATURES (2, D128, THE);
> > static const aarch64_feature_set aarch64_feature_b16b16 =
> > AARCH64_FEATURE (B16B16);
> > -static const aarch64_feature_set aarch64_feature_sme2p1 =
> > - AARCH64_FEATURE (SME2p1);
> > static const aarch64_feature_set aarch64_feature_sve2p1 =
> > AARCH64_FEATURE (SVE2p1);
> > static const aarch64_feature_set aarch64_feature_rcpc3 =
> > @@ -2713,7 +2711,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> > #define THE &aarch64_feature_the
> > #define D128_THE &aarch64_feature_d128_the
> > #define B16B16 &aarch64_feature_b16b16
> > -#define SME2p1 &aarch64_feature_sme2p1
> > #define SVE2p1 &aarch64_feature_sve2p1
> > #define RCPC3 &aarch64_feature_rcpc3
> >
> > @@ -2782,9 +2779,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> > #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> > { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> > FLAGS | F_STRICT, 0, TIED, NULL }
> > -#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> > - { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
> > - FLAGS | F_STRICT, 0, TIED, NULL }
> > #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
> > { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> > FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
> > @@ -6348,17 +6342,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> > B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
> > B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
> >
> > -/* SME2.1 movaz instructions. */
> > - SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
> > -
> > - SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
> > - SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
> > -
> > /* SVE2p1 Instructions. */
> > SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
> > SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] [2.42 Backport] aarch64: Remove SVE2p1
2024-02-29 17:33 [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Andrew Carlotti
2024-02-29 17:35 ` [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1 Andrew Carlotti
@ 2024-02-29 17:36 ` Andrew Carlotti
2024-02-29 17:36 ` [PATCH 3/3] [2.42 Backport] aarch64: Remove B16B16 Andrew Carlotti
2024-03-01 7:45 ` [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Jan Beulich
3 siblings, 0 replies; 7+ messages in thread
From: Andrew Carlotti @ 2024-02-29 17:36 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, Nick Clifton, Jan Beulich
Support for this extension is incomplete and has a number of syntax and
opcode bugs in the 2.42 branch. This patch removes the flags and
documentation, to avoid any further suggestion that this extension is
fully and correctly supported.
diff --git a/gas/NEWS b/gas/NEWS
index 86aa7d7334d3b58ee4e0abeba796b7214f356b30..75e6c9465aaa3871bb5acd367d6f8feab9b6d860 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -4,8 +4,6 @@ Changes in 2.42:
* Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
-* Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
-
* Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
(B16B16).
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 62c428cb80ba7114440c9c65f6042259e3f99df9..696283b456ceb7bd57ba4f021dd4b371e3ff15d4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"d128", AARCH64_FEATURE (D128),
AARCH64_FEATURE (LSE128)},
{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
- {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 748e7263428115c56db76b39371f9777248850a7..818f98ef8589228012fe583b56082f3027780434 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -277,8 +277,6 @@ automatically cause those extensions to be disabled.
@tab Enable the SVE2 SHA3 Extension.
@item @code{sve2-sm4} @tab @code{sve2}, @code{sm4}
@tab Enable the SVE2 SM4 Extension.
-@item @code{sve2p1} @tab @code{sve2}
- @tab Enable SVE2.1.
@item @code{the} @tab
@tab Enable the Translation Hardening Extension.
@item @code{tme} @tab
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
deleted file mode 100644
index a2ca49ef487563a55ae8c26ca4318e68da850e64..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#name: Illegal test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a
-#source: sve2p1-1.s
-#error_output: sve2p1-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
deleted file mode 100644
index 50a4bacc73c20324ae50b8688dd8cf5123a238ae..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ /dev/null
@@ -1,96 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `addqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `addqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `addqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `addqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `addqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `andqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `andqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `andqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `andqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `andqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `andqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `smaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `smaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `smaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `smaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `smaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `smaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `umaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `umaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `umaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `umaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `umaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `umaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `sminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `sminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `sminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `sminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `sminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `sminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `uminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `uminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `uminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `uminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `uminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `uminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[0\]'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[15\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[0\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[7\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[0\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[3\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[0\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[1\]'
-.*: Error: selected processor does not support `eorqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `eorqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `eorqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `extq z0.b,z0.b,z10.b\[15\]'
-.*: Error: selected processor does not support `extq z1.b,z1.b,z15.b\[7\]'
-.*: Error: selected processor does not support `extq z2.b,z2.b,z5.b\[3\]'
-.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
-.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
-.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
-.*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `faddqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `faddqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]'
-.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
deleted file mode 100644
index daece899b38bba4daa2ca9e58dba2d551f6cf988..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ /dev/null
@@ -1,105 +0,0 @@
-#name: Test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a+sve2p1
-#objdump: -dr
-
-[^:]+: file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*: 04052200 addqv v0.16b, p0, z16.b
-.*: 04452501 addqv v1.8h, p1, z8.h
-.*: 04852882 addqv v2.4s, p2, z4.s
-.*: 04c52c44 addqv v4.2d, p3, z2.d
-.*: 04c53028 addqv v8.2d, p4, z1.d
-.*: 04853c10 addqv v16.4s, p7, z0.s
-.*: 041e2200 andqv v0.16b, p0, z16.b
-.*: 045e2501 andqv v1.8h, p1, z8.h
-.*: 049e2882 andqv v2.4s, p2, z4.s
-.*: 04de2c44 andqv v4.2d, p3, z2.d
-.*: 04de3028 andqv v8.2d, p4, z1.d
-.*: 049e3c10 andqv v16.4s, p7, z0.s
-.*: 040c2200 smaxqv v0.16b, p0, z16.b
-.*: 044c2501 smaxqv v1.8h, p1, z8.h
-.*: 048c2882 smaxqv v2.4s, p2, z4.s
-.*: 04cc2c44 smaxqv v4.2d, p3, z2.d
-.*: 04cc3028 smaxqv v8.2d, p4, z1.d
-.*: 048c3c10 smaxqv v16.4s, p7, z0.s
-.*: 040d2200 umaxqv v0.16b, p0, z16.b
-.*: 044d2501 umaxqv v1.8h, p1, z8.h
-.*: 048d2882 umaxqv v2.4s, p2, z4.s
-.*: 04cd2c44 umaxqv v4.2d, p3, z2.d
-.*: 04cd3028 umaxqv v8.2d, p4, z1.d
-.*: 048d3c10 umaxqv v16.4s, p7, z0.s
-.*: 040e2200 sminqv v0.16b, p0, z16.b
-.*: 044e2501 sminqv v1.8h, p1, z8.h
-.*: 048e2882 sminqv v2.4s, p2, z4.s
-.*: 04ce2c44 sminqv v4.2d, p3, z2.d
-.*: 04ce3028 sminqv v8.2d, p4, z1.d
-.*: 048e3c10 sminqv v16.4s, p7, z0.s
-.*: 040f2200 uminqv v0.16b, p0, z16.b
-.*: 044f2501 uminqv v1.8h, p1, z8.h
-.*: 048f2882 uminqv v2.4s, p2, z4.s
-.*: 04cf2c44 uminqv v4.2d, p3, z2.d
-.*: 04cf3028 uminqv v8.2d, p4, z1.d
-.*: 048f3c10 uminqv v16.4s, p7, z0.s
-.*: 0530268a dupq z10.b, z20.b\[0\]
-.*: 053f268a dupq z10.b, z20.b\[15\]
-.*: 0521268a dupq z10.h, z20.h\[0\]
-.*: 052f268a dupq z10.h, z20.h\[7\]
-.*: 0522268a dupq z10.s, z20.s\[0\]
-.*: 052e268a dupq z10.s, z20.s\[3\]
-.*: 0524268a dupq z10.d, z20.d\[0\]
-.*: 052c268a dupq z10.d, z20.d\[1\]
-.*: 041d2200 eorqv v0.16b, p0, z16.b
-.*: 045d2501 eorqv v1.8h, p1, z8.h
-.*: 049d2882 eorqv v2.4s, p2, z4.s
-.*: 04dd2c44 eorqv v4.2d, p3, z2.d
-.*: 04dd3028 eorqv v8.2d, p4, z1.d
-.*: 049d3c10 eorqv v16.4s, p7, z0.s
-.*: 056a27c0 extq z0.b, z0.b, z10.b\[15\]
-.*: 056f25c1 extq z1.b, z1.b, z15.b\[7\]
-.*: 056524c2 extq z2.b, z2.b, z5.b\[3\]
-.*: 056c2444 extq z4.b, z4.b, z12.b\[1\]
-.*: 05672508 extq z8.b, z8.b, z7.b\[4\]
-.*: 05612610 extq z16.b, z16.b, z1.b\[8\]
-.*: 6450a501 faddqv v1.8h, p1, z8.h
-.*: 6490a882 faddqv v2.4s, p2, z4.s
-.*: 64d0ac44 faddqv v4.2d, p3, z2.d
-.*: 64d0b028 faddqv v8.2d, p4, z1.d
-.*: 6490bc10 faddqv v16.4s, p7, z0.s
-.*: 6454a501 fmaxnmqv v1.8h, p1, z8.h
-.*: 6494a882 fmaxnmqv v2.4s, p2, z4.s
-.*: 64d4ac44 fmaxnmqv v4.2d, p3, z2.d
-.*: 64d4b028 fmaxnmqv v8.2d, p4, z1.d
-.*: 6494bc10 fmaxnmqv v16.4s, p7, z0.s
-.*: 6456a501 fmaxqv v1.8h, p1, z8.h
-.*: 6496a882 fmaxqv v2.4s, p2, z4.s
-.*: 64d6ac44 fmaxqv v4.2d, p3, z2.d
-.*: 64d6b028 fmaxqv v8.2d, p4, z1.d
-.*: 6496bc10 fmaxqv v16.4s, p7, z0.s
-.*: 6455a501 fminnmqv v1.8h, p1, z8.h
-.*: 6495a882 fminnmqv v2.4s, p2, z4.s
-.*: 64d5ac44 fminnmqv v4.2d, p3, z2.d
-.*: 64d5b028 fminnmqv v8.2d, p4, z1.d
-.*: 6495bc10 fminnmqv v16.4s, p7, z0.s
-.*: 6457a501 fminqv v1.8h, p1, z8.h
-.*: 6497a882 fminqv v2.4s, p2, z4.s
-.*: 64d7ac44 fminqv v4.2d, p3, z2.d
-.*: 64d7b028 fminqv v8.2d, p4, z1.d
-.*: 6497bc10 fminqv v16.4s, p7, z0.s
-.*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\]
-.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\]
-.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-4, mul vl\]
-.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-4, mul vl\]
-.*: a4a2f000 ld2h {z0.h-z1.h}, p4/z, \[x0, #4, mul vl\]
-.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\]
-.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\]
-.*: e4203200 st1q z0.q, p4, \[z16.d, x0\]
-.*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\]
-.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-4, mul vl\]
-.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-4, mul vl\]
-.*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\]
-.*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\]
-.*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
deleted file mode 100644
index 2a1c7c107d757ae922cec5566adbace1f03e0dce..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ /dev/null
@@ -1,107 +0,0 @@
-addqv v0.16b, p0, z16.b
-addqv v1.8h, p1, z8.h
-addqv v2.4s, p2, z4.s
-addqv v4.2d, p3, z2.d
-addqv v8.2d, p4, z1.d
-addqv v16.4s, p7, z0.s
-
-andqv v0.16b, p0, z16.b
-andqv v1.8h, p1, z8.h
-andqv v2.4s, p2, z4.s
-andqv v4.2d, p3, z2.d
-andqv v8.2d, p4, z1.d
-andqv v16.4s, p7, z0.s
-
-smaxqv v0.16b, p0, z16.b
-smaxqv v1.8h, p1, z8.h
-smaxqv v2.4s, p2, z4.s
-smaxqv v4.2d, p3, z2.d
-smaxqv v8.2d, p4, z1.d
-smaxqv v16.4s, p7, z0.s
-
-umaxqv v0.16b, p0, z16.b
-umaxqv v1.8h, p1, z8.h
-umaxqv v2.4s, p2, z4.s
-umaxqv v4.2d, p3, z2.d
-umaxqv v8.2d, p4, z1.d
-umaxqv v16.4s, p7, z0.s
-
-sminqv v0.16b, p0, z16.b
-sminqv v1.8h, p1, z8.h
-sminqv v2.4s, p2, z4.s
-sminqv v4.2d, p3, z2.d
-sminqv v8.2d, p4, z1.d
-sminqv v16.4s, p7, z0.s
-
-uminqv v0.16b, p0, z16.b
-uminqv v1.8h, p1, z8.h
-uminqv v2.4s, p2, z4.s
-uminqv v4.2d, p3, z2.d
-uminqv v8.2d, p4, z1.d
-uminqv v16.4s, p7, z0.s
-dupq z10.b, z20.b[0]
-dupq z10.b, z20.b[15]
-dupq z10.h, z20.h[0]
-dupq z10.h, z20.h[7]
-dupq z10.s, z20.s[0]
-dupq z10.s, z20.s[3]
-dupq z10.d, z20.d[0]
-dupq z10.d, z20.d[1]
-
-eorqv v0.16b, p0, z16.b
-eorqv v1.8h, p1, z8.h
-eorqv v2.4s, p2, z4.s
-eorqv v4.2d, p3, z2.d
-eorqv v8.2d, p4, z1.d
-eorqv v16.4s, p7, z0.s
-
-extq z0.b, z0.b, z10.b[15]
-extq z1.b, z1.b, z15.b[7]
-extq z2.b, z2.b, z5.b[3]
-extq z4.b, z4.b, z12.b[1]
-extq z8.b, z8.b, z7.b[4]
-extq z16.b, z16.b, z1.b[8]
-faddqv v1.8h, p1, z8.h
-faddqv v2.4s, p2, z4.s
-faddqv v4.2d, p3, z2.d
-faddqv v8.2d, p4, z1.d
-faddqv v16.4s, p7, z0.s
-
-fmaxnmqv v1.8h, p1, z8.h
-fmaxnmqv v2.4s, p2, z4.s
-fmaxnmqv v4.2d, p3, z2.d
-fmaxnmqv v8.2d, p4, z1.d
-fmaxnmqv v16.4s, p7, z0.s
-
-fmaxqv v1.8h, p1, z8.h
-fmaxqv v2.4s, p2, z4.s
-fmaxqv v4.2d, p3, z2.d
-fmaxqv v8.2d, p4, z1.d
-fmaxqv v16.4s, p7, z0.s
-
-fminnmqv v1.8h, p1, z8.h
-fminnmqv v2.4s, p2, z4.s
-fminnmqv v4.2d, p3, z2.d
-fminnmqv v8.2d, p4, z1.d
-fminnmqv v16.4s, p7, z0.s
-
-fminqv v1.8h, p1, z8.h
-fminqv v2.4s, p2, z4.s
-fminqv v4.2d, p3, z2.d
-fminqv v8.2d, p4, z1.d
-fminqv v16.4s, p7, z0.s
-ld1q Z0.Q, p4/Z, [Z16.D, x0]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-4, MUL VL]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-4, MUL VL]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4]
-
-st1q Z0.Q, p4, [Z16.D, x0]
-st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-4, MUL VL]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-4, MUL VL]
-st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bb3151d027ccd56f83298083a2e6c744eb1f4573..2e7485f25adfc7001630b50d173bd7ff77b587a6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,8 +222,6 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SEBEP,
/* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
AARCH64_FEATURE_B16B16,
- /* SVE2.1 instructions. */
- AARCH64_FEATURE_SVE2p1,
/* RCPC3 instructions. */
AARCH64_FEATURE_RCPC3,
AARCH64_NUM_FEATURES
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ae4363970b0b8bc6eaa342b4199d96cacac6fd8a..1c9fa61c8f89b32ed1deb1db33cb1b55206dd3a3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
static const aarch64_feature_set aarch64_feature_b16b16 =
AARCH64_FEATURE (B16B16);
-static const aarch64_feature_set aarch64_feature_sve2p1 =
- AARCH64_FEATURE (SVE2p1);
static const aarch64_feature_set aarch64_feature_rcpc3 =
AARCH64_FEATURE (RCPC3);
@@ -2711,7 +2709,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
#define B16B16 &aarch64_feature_b16b16
-#define SVE2p1 &aarch64_feature_sve2p1
#define RCPC3 &aarch64_feature_rcpc3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2788,12 +2785,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
- FLAGS | F_STRICT, 0, TIED, NULL }
-#define SVE2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
- FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@@ -6342,39 +6333,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-/* SVE2p1 Instructions. */
- SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
- SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
- SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
- SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0),
- SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-
- SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/3] [2.42 Backport] aarch64: Remove B16B16
2024-02-29 17:33 [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Andrew Carlotti
2024-02-29 17:35 ` [PATCH 1/3] [2.42 Backport] aarch64: Remove SME2p1 Andrew Carlotti
2024-02-29 17:36 ` [PATCH 2/3] [2.42 Backport] aarch64: Remove SVE2p1 Andrew Carlotti
@ 2024-02-29 17:36 ` Andrew Carlotti
2024-03-01 7:45 ` [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Jan Beulich
3 siblings, 0 replies; 7+ messages in thread
From: Andrew Carlotti @ 2024-02-29 17:36 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, Nick Clifton, Jan Beulich
Support for this extension is incomplete and has opcode bugs in the 2.42
branch. This patch removes the flags and documentation, to avoid any
further suggestion that this extension is fully and correctly supported.
diff --git a/gas/NEWS b/gas/NEWS
index 75e6c9465aaa3871bb5acd367d6f8feab9b6d860..3a9dbc7d2e022d360e5b1a0aaa684ad76b51b17d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -4,9 +4,6 @@ Changes in 2.42:
* Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
-* Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
- (B16B16).
-
* Add support for the AArch64 Reliability, Availability and Serviceability
extension v2 (RASv2).
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 696283b456ceb7bd57ba4f021dd4b371e3ff15d4..a7c29d2f03f74a0384dcb5b96c08a1827cda5a8d 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10425,7 +10425,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
{"d128", AARCH64_FEATURE (D128),
AARCH64_FEATURE (LSE128)},
- {"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 818f98ef8589228012fe583b56082f3027780434..77226a07973c9e9c232c595b14bd82728648170e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,8 +161,6 @@ automatically cause those extensions to be disabled.
@headitem Extension @tab Depends upon @tab Description
@item @code{aes} @tab @code{simd}
@tab Enable the AES and PMULL cryptographic extensions.
-@item @code{b16b16} @tab @code{sve2}
- @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
@item @code{bf16} @tab @code{fp}
@tab Enable BFloat16 extension.
@item @code{chk} @tab
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
deleted file mode 100644
index f0d436bec585ff2aee2e007d63fc672a11a569b9..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ /dev/null
@@ -1,106 +0,0 @@
-#name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions.
-#as: -march=armv9.4-a+b16b16
-#objdump: -dr
-
-[^:]+: file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*: 65008200 bfadd z0.h, p0\/m, z0.h, z16.h
-.*: 65008501 bfadd z1.h, p1\/m, z1.h, z8.h
-.*: 65008882 bfadd z2.h, p2\/m, z2.h, z4.h
-.*: 65009044 bfadd z4.h, p4\/m, z4.h, z2.h
-.*: 65009828 bfadd z8.h, p6\/m, z8.h, z1.h
-.*: 65009c10 bfadd z16.h, p7\/m, z16.h, z0.h
-.*: 65068200 bfmax z0.h, p0\/m, z0.h, z16.h
-.*: 65068501 bfmax z1.h, p1\/m, z1.h, z8.h
-.*: 65068882 bfmax z2.h, p2\/m, z2.h, z4.h
-.*: 65069044 bfmax z4.h, p4\/m, z4.h, z2.h
-.*: 65069828 bfmax z8.h, p6\/m, z8.h, z1.h
-.*: 65069c10 bfmax z16.h, p7\/m, z16.h, z0.h
-.*: 65048200 bfmaxnm z0.h, p0\/m, z0.h, z16.h
-.*: 65048501 bfmaxnm z1.h, p1\/m, z1.h, z8.h
-.*: 65048882 bfmaxnm z2.h, p2\/m, z2.h, z4.h
-.*: 65049044 bfmaxnm z4.h, p4\/m, z4.h, z2.h
-.*: 65049828 bfmaxnm z8.h, p6\/m, z8.h, z1.h
-.*: 65049c10 bfmaxnm z16.h, p7\/m, z16.h, z0.h
-.*: 65078200 bfmin z0.h, p0\/m, z0.h, z16.h
-.*: 65078501 bfmin z1.h, p1\/m, z1.h, z8.h
-.*: 65078882 bfmin z2.h, p2\/m, z2.h, z4.h
-.*: 65079044 bfmin z4.h, p4\/m, z4.h, z2.h
-.*: 65079828 bfmin z8.h, p6\/m, z8.h, z1.h
-.*: 65079c10 bfmin z16.h, p7\/m, z16.h, z0.h
-.*: 65058200 bfminnm z0.h, p0\/m, z0.h, z16.h
-.*: 65058501 bfminnm z1.h, p1\/m, z1.h, z8.h
-.*: 65058882 bfminnm z2.h, p2\/m, z2.h, z4.h
-.*: 65059044 bfminnm z4.h, p4\/m, z4.h, z2.h
-.*: 65059828 bfminnm z8.h, p6\/m, z8.h, z1.h
-.*: 65059c10 bfminnm z16.h, p7\/m, z16.h, z0.h
-.*: 65100080 bfadd z0.h, z4.h, z16.h
-.*: 65080101 bfadd z1.h, z8.h, z8.h
-.*: 65040182 bfadd z2.h, z12.h, z4.h
-.*: 65020204 bfadd z4.h, z16.h, z2.h
-.*: 65010288 bfadd z8.h, z20.h, z1.h
-.*: 65000310 bfadd z16.h, z24.h, z0.h
-.*: 64302480 bfclamp z0.h, z4.h, z16.h
-.*: 64282501 bfclamp z1.h, z8.h, z8.h
-.*: 64242582 bfclamp z2.h, z12.h, z4.h
-.*: 64222604 bfclamp z4.h, z16.h, z2.h
-.*: 64212688 bfclamp z8.h, z20.h, z1.h
-.*: 64202710 bfclamp z16.h, z24.h, z0.h
-.*: 65300000 bfmla z0.h, p0\/m, z0.h, z16.h
-.*: 65280421 bfmla z1.h, p1\/m, z1.h, z8.h
-.*: 65240842 bfmla z2.h, p2\/m, z2.h, z4.h
-.*: 65221084 bfmla z4.h, p4\/m, z4.h, z2.h
-.*: 65211908 bfmla z8.h, p6\/m, z8.h, z1.h
-.*: 65201e10 bfmla z16.h, p7\/m, z16.h, z0.h
-.*: 643e0a00 bfmla z0.h, z16.h, z6.h\[7\]
-.*: 643d0901 bfmla z1.h, z8.h, z5.h\[7\]
-.*: 643409c2 bfmla z2.h, z14.h, z4.h\[5\]
-.*: 642a0aa4 bfmla z4.h, z21.h, z2.h\[3\]
-.*: 64210988 bfmla z8.h, z12.h, z1.h\[1\]
-.*: 64200950 bfmla z16.h, z10.h, z0.h\[1\]
-.*: 65302000 bfmls z0.h, p0\/m, z0.h, z16.h
-.*: 65282421 bfmls z1.h, p1\/m, z1.h, z8.h
-.*: 65242842 bfmls z2.h, p2\/m, z2.h, z4.h
-.*: 65223084 bfmls z4.h, p4\/m, z4.h, z2.h
-.*: 65213908 bfmls z8.h, p6\/m, z8.h, z1.h
-.*: 65203e10 bfmls z16.h, p7\/m, z16.h, z0.h
-.*: 643e0e00 bfmls z0.h, z16.h, z6.h\[7\]
-.*: 643d0d01 bfmls z1.h, z8.h, z5.h\[7\]
-.*: 64340dc2 bfmls z2.h, z14.h, z4.h\[5\]
-.*: 642a0ea4 bfmls z4.h, z21.h, z2.h\[3\]
-.*: 64210d88 bfmls z8.h, z12.h, z1.h\[1\]
-.*: 64200d50 bfmls z16.h, z10.h, z0.h\[1\]
-.*: 65028200 bfmul z0.h, p0\/m, z0.h, z16.h
-.*: 65028501 bfmul z1.h, p1\/m, z1.h, z8.h
-.*: 65028882 bfmul z2.h, p2\/m, z2.h, z4.h
-.*: 65029044 bfmul z4.h, p4\/m, z4.h, z2.h
-.*: 65029828 bfmul z8.h, p6\/m, z8.h, z1.h
-.*: 65029c10 bfmul z16.h, p7\/m, z16.h, z0.h
-.*: 65100880 bfmul z0.h, z4.h, z16.h
-.*: 65080901 bfmul z1.h, z8.h, z8.h
-.*: 65040982 bfmul z2.h, z12.h, z4.h
-.*: 65020a04 bfmul z4.h, z16.h, z2.h
-.*: 65010a88 bfmul z8.h, z20.h, z1.h
-.*: 65000b10 bfmul z16.h, z24.h, z0.h
-.*: 643e2a00 bfmul z0.h, z16.h, z6.h\[7\]
-.*: 643d2901 bfmul z1.h, z8.h, z5.h\[7\]
-.*: 643429c2 bfmul z2.h, z14.h, z4.h\[5\]
-.*: 642a2aa4 bfmul z4.h, z21.h, z2.h\[3\]
-.*: 64212988 bfmul z8.h, z12.h, z1.h\[1\]
-.*: 64202950 bfmul z16.h, z10.h, z0.h\[1\]
-.*: 65018200 bfsub z0.h, p0\/m, z0.h, z16.h
-.*: 65018501 bfsub z1.h, p1\/m, z1.h, z8.h
-.*: 65018882 bfsub z2.h, p2\/m, z2.h, z4.h
-.*: 65019044 bfsub z4.h, p4\/m, z4.h, z2.h
-.*: 65019828 bfsub z8.h, p6\/m, z8.h, z1.h
-.*: 65019c10 bfsub z16.h, p7\/m, z16.h, z0.h
-.*: 65100480 bfsub z0.h, z4.h, z16.h
-.*: 65080501 bfsub z1.h, z8.h, z8.h
-.*: 65040582 bfsub z2.h, z12.h, z4.h
-.*: 65020604 bfsub z4.h, z16.h, z2.h
-.*: 65010688 bfsub z8.h, z20.h, z1.h
-.*: 65000710 bfsub z16.h, z24.h, z0.h
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s
deleted file mode 100644
index 5597d9ef01906f7316149cdf0bb69addeb849926..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ /dev/null
@@ -1,112 +0,0 @@
-bfadd z0.h, p0/m, z0.h, z16.h
-bfadd z1.h, p1/m, z1.h, z8.h
-bfadd z2.h, p2/m, z2.h, z4.h
-bfadd z4.h, p4/m, z4.h, z2.h
-bfadd z8.h, p6/m, z8.h, z1.h
-bfadd z16.h, p7/m, z16.h, z0.h
-
-bfmax z0.h, p0/m, z0.h, z16.h
-bfmax z1.h, p1/m, z1.h, z8.h
-bfmax z2.h, p2/m, z2.h, z4.h
-bfmax z4.h, p4/m, z4.h, z2.h
-bfmax z8.h, p6/m, z8.h, z1.h
-bfmax z16.h, p7/m, z16.h, z0.h
-
-bfmaxnm z0.h, p0/m, z0.h, z16.h
-bfmaxnm z1.h, p1/m, z1.h, z8.h
-bfmaxnm z2.h, p2/m, z2.h, z4.h
-bfmaxnm z4.h, p4/m, z4.h, z2.h
-bfmaxnm z8.h, p6/m, z8.h, z1.h
-bfmaxnm z16.h, p7/m, z16.h, z0.h
-
-bfmin z0.h, p0/m, z0.h, z16.h
-bfmin z1.h, p1/m, z1.h, z8.h
-bfmin z2.h, p2/m, z2.h, z4.h
-bfmin z4.h, p4/m, z4.h, z2.h
-bfmin z8.h, p6/m, z8.h, z1.h
-bfmin z16.h, p7/m, z16.h, z0.h
-
-bfminnm z0.h, p0/m, z0.h, z16.h
-bfminnm z1.h, p1/m, z1.h, z8.h
-bfminnm z2.h, p2/m, z2.h, z4.h
-bfminnm z4.h, p4/m, z4.h, z2.h
-bfminnm z8.h, p6/m, z8.h, z1.h
-bfminnm z16.h, p7/m, z16.h, z0.h
-
-bfadd z0.h, z4.h, z16.h
-bfadd z1.h, z8.h, z8.h
-bfadd z2.h, z12.h, z4.h
-bfadd z4.h, z16.h, z2.h
-bfadd z8.h, z20.h, z1.h
-bfadd z16.h, z24.h, z0.h
-
-bfclamp z0.h, z4.h, z16.h
-bfclamp z1.h, z8.h, z8.h
-bfclamp z2.h, z12.h, z4.h
-bfclamp z4.h, z16.h, z2.h
-bfclamp z8.h, z20.h, z1.h
-bfclamp z16.h, z24.h, z0.h
-bfmla z0.h, p0/m, z0.h, z16.h
-bfmla z1.h, p1/m, z1.h, z8.h
-bfmla z2.h, p2/m, z2.h, z4.h
-bfmla z4.h, p4/m, z4.h, z2.h
-bfmla z8.h, p6/m, z8.h, z1.h
-bfmla z16.h, p7/m, z16.h, z0.h
-
-bfmla z0.h, z16.h, z6.h[7]
-bfmla z1.h, z8.h, z5.h[6]
-bfmla z2.h, z14.h, z4.h[4]
-bfmla z4.h, z21.h, z2.h[2]
-bfmla z8.h, z12.h, z1.h[1]
-bfmla z16.h, z10.h, z0.h[0]
-
-bfmls z0.h, p0/m, z0.h, z16.h
-bfmls z1.h, p1/m, z1.h, z8.h
-bfmls z2.h, p2/m, z2.h, z4.h
-bfmls z4.h, p4/m, z4.h, z2.h
-bfmls z8.h, p6/m, z8.h, z1.h
-bfmls z16.h, p7/m, z16.h, z0.h
-
-bfmls z0.h, z16.h, z6.h[7]
-bfmls z1.h, z8.h, z5.h[6]
-bfmls z2.h, z14.h, z4.h[4]
-bfmls z4.h, z21.h, z2.h[2]
-bfmls z8.h, z12.h, z1.h[1]
-bfmls z16.h, z10.h, z0.h[0]
-
-bfmul z0.h, p0/m, z0.h, z16.h
-bfmul z1.h, p1/m, z1.h, z8.h
-bfmul z2.h, p2/m, z2.h, z4.h
-bfmul z4.h, p4/m, z4.h, z2.h
-bfmul z8.h, p6/m, z8.h, z1.h
-bfmul z16.h, p7/m, z16.h, z0.h
-
-bfmul z0.h, z4.h, z16.h
-bfmul z1.h, z8.h, z8.h
-bfmul z2.h, z12.h, z4.h
-bfmul z4.h, z16.h, z2.h
-bfmul z8.h, z20.h, z1.h
-bfmul z16.h, z24.h, z0.h
-
-bfmul z0.h, z16.h, z6.h[7]
-bfmul z1.h, z8.h, z5.h[6]
-bfmul z2.h, z14.h, z4.h[4]
-bfmul z4.h, z21.h, z2.h[2]
-bfmul z8.h, z12.h, z1.h[1]
-bfmul z16.h, z10.h, z0.h[0]
-
-bfsub z0.h, p0/m, z0.h, z16.h
-bfsub z1.h, p1/m, z1.h, z8.h
-bfsub z2.h, p2/m, z2.h, z4.h
-bfsub z4.h, p4/m, z4.h, z2.h
-bfsub z8.h, p6/m, z8.h, z1.h
-bfsub z16.h, p7/m, z16.h, z0.h
-
-bfsub z0.h, z4.h, z16.h
-bfsub z1.h, z8.h, z8.h
-bfsub z2.h, z12.h, z4.h
-bfsub z4.h, z16.h, z2.h
-bfsub z8.h, z20.h, z1.h
-bfsub z16.h, z24.h, z0.h
-
-
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.d b/gas/testsuite/gas/aarch64/bfloat16-bad.d
deleted file mode 100644
index 10d2b001c1a39851ab020e20997f2774663dc3ba..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#name: Negative test of Bfloat16 instructions.
-#as: -march=armv9.4-a
-#source: bfloat16-1.s
-#error_output: bfloat16-bad.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
deleted file mode 100644
index 5a5192b329cd250914c860de5331ef3952ef846b..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ /dev/null
@@ -1,97 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support `bfadd z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmax z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmax z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmax z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmax z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmax z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmax z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmaxnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmaxnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmaxnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmaxnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmaxnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmaxnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmin z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmin z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmin z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmin z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmin z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmin z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfminnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfminnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfminnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfminnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfminnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfminnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfadd z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfclamp z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfclamp z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfclamp z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfclamp z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfclamp z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfclamp z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmla z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmla z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmla z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmla z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmla z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmla z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmla z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmla z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmla z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmla z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmla z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmla z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmls z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmls z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmls z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmls z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmls z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmls z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmls z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmls z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmls z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmls z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmls z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmls z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmul z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmul z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmul z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmul z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmul z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfsub z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfsub z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2e7485f25adfc7001630b50d173bd7ff77b587a6..cebeb5a5fda1eaffd74e8759295023ce0a6d4e2c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -220,8 +220,6 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PMUv3_ICNTR,
/* Performance Monitors Synchronous-Exception-Based Event Extension. */
AARCH64_FEATURE_SEBEP,
- /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
- AARCH64_FEATURE_B16B16,
/* RCPC3 instructions. */
AARCH64_FEATURE_RCPC3,
AARCH64_NUM_FEATURES
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1c9fa61c8f89b32ed1deb1db33cb1b55206dd3a3..a7556a48f45292898705ca87f8df814b41c5fcfc 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2641,8 +2641,6 @@ static const aarch64_feature_set aarch64_feature_the =
AARCH64_FEATURE (THE);
static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
-static const aarch64_feature_set aarch64_feature_b16b16 =
- AARCH64_FEATURE (B16B16);
static const aarch64_feature_set aarch64_feature_rcpc3 =
AARCH64_FEATURE (RCPC3);
@@ -2708,7 +2706,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define D128 &aarch64_feature_d128
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
-#define B16B16 &aarch64_feature_b16b16
#define RCPC3 &aarch64_feature_rcpc3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2779,12 +2776,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
- FLAGS | F_STRICT, 0, TIED, NULL }
-#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
- FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@@ -6315,24 +6306,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
-/* BFloat16 SVE Instructions. */
- B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
- B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
- B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1
2024-02-29 17:33 [0/3] [2.42 Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 Andrew Carlotti
` (2 preceding siblings ...)
2024-02-29 17:36 ` [PATCH 3/3] [2.42 Backport] aarch64: Remove B16B16 Andrew Carlotti
@ 2024-03-01 7:45 ` Jan Beulich
3 siblings, 0 replies; 7+ messages in thread
From: Jan Beulich @ 2024-03-01 7:45 UTC (permalink / raw)
To: Andrew Carlotti
Cc: Richard Earnshaw, Nick Clifton, binutils, Marcus Shawcroft
On 29.02.2024 18:33, Andrew Carlotti wrote:
> Unfortunately the support for these extensions in the 2.42 release has a large
> number of missing instructions and wrong code bugs. I expect it will still
> take a long time to fix all of these issues and be confident that we haven't
> missed any more problems. This level of new feature support is not something
> we would normally consider backporting, and I don't think it's appropriate to
> do so in this case either.
>
> Instead, this patch series disables support for these extensions in the 2.42
> branch. It will then be possible to make a point release with the broken
> behaviour removed, without waiting for all of the bugs and omissions in these
> extensions to be fixed on master. It also avoids the burden of having to
> manage and verify a large number of bugfix patches on two different branches.
While I'll commit my "gas/NEWS: drop mention of Arm64's SVE2.1 and SME2.1"
then later today, in light of your submission I'll avoid also cherry-picking
it onto the branch, until ...
> Is this ok for the 2.42 branch?
... Arm64 maintainers have decided here. Personally I didn't think we need
to go as far.
Jan
^ permalink raw reply [flat|nested] 7+ messages in thread